CN107546228B

CN107546228B - Semiconductor device, manufacturing method thereof and electronic device

Info

Publication number: CN107546228B
Application number: CN201610489559.4A
Authority: CN
Inventors: 张海洋; 常荣耀; 郑喆
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-06-29
Filing date: 2016-06-29
Publication date: 2020-11-03
Anticipated expiration: 2036-06-29
Also published as: CN107546228A

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate at least comprises a storage region and a contact plug region; forming a plurality of stacked structures on the semiconductor substrate of the storage region, wherein each stacked structure comprises a dielectric layer and a control gate layer positioned above the dielectric layer; forming a first dielectric layer covering the multilayer laminated structure and the contact plug region, and forming a plurality of first contact plugs corresponding to the control gate layer in the multilayer laminated structure in the first dielectric layer in the contact plug region; and forming a second dielectric layer on the first dielectric layer, and forming a plurality of second contact plugs correspondingly connected with the first contact plugs in the second dielectric layer. The manufacturing method can reduce the process difficulty and the cost. The semiconductor device and the electronic device have the advantages of simple structure and low cost.

Description

Semiconductor device, manufacturing method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.

Background

With the development of semiconductor process technology and the demand of high integration density and large storage capacity in the industry, 3D NAND (three-dimensional NAND) memories have been developed. A 3D NAND structure is shown in fig. 6, which includes a multi-layer memory array 1, a bottom select gate ls (lower sg) and a source line sl (source line) below the memory array 1, a top select gate us (upper sg) above the memory array 1, a bit line bl (bit line) above the top select gate, and a control gate cg (control gate) extending from each layer of the memory array 1. For each layer of memory, the memory cell extends from the control gate of the layer and is connected to the control voltage signal input line 2 through contact plugs arranged in a staggered manner. The current is maintained to be output unidirectionally from the memory array by the source line sl (source line). The selection of a specific memory is realized by a selection signal of a word line bl (bit line), a selection signal common to a top layer selection gate us (upper sg) and a bottom layer selection gate ls (lower sg), and a selection signal of a control gate cg (control gate) from three dimensions (3D) of a three-dimensional space. The selection signal of the control gate cg (control gate) controls the selection of the memory cell of each layer in the horizontal direction. The control gates of the memories of each layer extend out of the memory array and are connected by contact plugs to voltage signal input lines 22, which voltage signal input lines 2 serve as bit lines. The control gate CG layers are sequentially stacked up in a step shape, and the contact plugs are sequentially staggered up along the step shape to be connected to different bit lines (voltage signal input lines 2).

In such a structure, the number of control gate layers is proportional to the storage capacity, i.e., the number of steps is proportional to the storage capacity. With the pursuit of memory capacity, a memory with larger capacity needs to be manufactured, and more layers of control gates need to be manufactured, if the number of layers is increased to 128 layers or more, for example, in such a structure, the difficulty of manufacturing through holes with different depths in the same step of process is great, and the control gate structure and the contact plug with the step structure increase the cost per bit (bite), and in addition, the control gate structure and the contact plug with the step structure need to be manufactured by a multi-step photolithography process, which correspondingly increases the manufacturing cost of the device.

Therefore, it is desirable to provide a new semiconductor device and a method for fabricating the same to solve the above problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

Aiming at the defects of the prior art, the invention provides a semiconductor device and a manufacturing method thereof, which can reduce the manufacturing cost of a 3DNAND structure and reduce the cost of each bit.

One aspect of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate, wherein the semiconductor substrate at least comprises a storage region and a contact plug region; forming a plurality of stacked structures on the semiconductor substrate of the storage region, wherein each stacked structure comprises a dielectric layer and a control gate layer positioned above the dielectric layer; forming a first dielectric layer covering the multilayer laminated structure and the contact plug region, forming a plurality of first contact plugs corresponding to the control gate layers in the multilayer laminated structure in the first dielectric layer in the contact plug region, wherein the first contact plugs extend from each control gate layer to the upper surface of the first dielectric layer in an inclined manner; and forming a second dielectric layer on the first dielectric layer, and forming a plurality of second contact plugs correspondingly connected with the first contact plugs in the second dielectric layer, wherein each corresponding first contact plug and second contact plug is connected with one corresponding control gate layer.

Further, the step of forming the plurality of first contact plugs includes: forming a patterned hard mask layer on the first dielectric layer, wherein the patterned hard mask layer defines the opening positions of the first contact plugs on the top surface of the first dielectric layer; etching the first dielectric layer by taking the hard mask layer as a mask to form a plurality of inclined first contact holes, wherein each first contact hole correspondingly extends to one control gate layer; filling the plurality of inclined first contact holes with a conductive material to form the plurality of first contact plugs.

Further, the first dielectric layer is etched by adopting a directional ribbon beam etching process to form a plurality of inclined first contact holes.

Further, the hard mask layer is a metal hard mask layer.

Furthermore, the inclination angle of the first contact plug relative to the semiconductor substrate is 30-60 degrees.

Further, the second contact plug is disposed perpendicular to the semiconductor substrate.

Further, the control gate layer includes a metal tungsten layer.

Further, the first contact plug and the second contact plug comprise a metal tungsten material.

According to the manufacturing method of the semiconductor device, the 3DNAND structure is divided into the storage area and the contact plug area, the inclined first contact plug and the vertical second contact plug are arranged in the contact plug area, and the first contact plug and the second contact plug are connected with the control grid layer, so that the control grid layer does not need to be formed into a step shape, the steps of photoetching and etching are reduced, and the process cost and the difficulty are reduced.

Another aspect of the present invention provides a semiconductor device, including: the semiconductor substrate is at least divided into a storage region and a contact plug region, a multilayer laminated structure is formed on the semiconductor substrate of the storage region, and each laminated structure comprises a dielectric layer and a control gate layer positioned above the dielectric layer; a first dielectric layer covering the multi-layer stack structure and the contact plug region, wherein a plurality of first contact plugs corresponding to the control gate layers in the multi-layer stack structure are formed in the first dielectric layer in the contact plug region, and each first contact plug obliquely extends from each control gate layer to the upper surface of the first dielectric layer; and a second dielectric layer on the first dielectric layer, wherein a plurality of second contact plugs correspondingly connected with the first contact plugs are formed in the second dielectric layer, and each corresponding first contact plug and second contact plug is connected with a corresponding control gate layer.

Preferably, the inclination angle of the first contact plug relative to the semiconductor substrate is 30-60 degrees.

Preferably, the second contact plug is disposed perpendicular to the semiconductor substrate.

Preferably, the control gate layer comprises a metal tungsten layer.

Preferably, the first and second contact plugs include a metal tungsten material.

The semiconductor device provided by the invention does not need to manufacture the contact plug with the step structure, so that the manufacturing process difficulty is reduced, the manufacturing cost is reduced, and the semiconductor device has the advantages of simple structure and low cost.

A further aspect of the invention provides an electronic device comprising a semiconductor device as described above and an electronic component connected to the semiconductor device.

The electronic device provided by the invention has similar advantages due to the semiconductor device.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

fig. 1A to 1F are flowcharts showing a flow of a current step of fabricating a contact plug of a 3D NAND semiconductor device;

FIG. 2 is a flow chart illustrating steps in a method of fabricating a semiconductor device according to an embodiment of the present invention;

fig. 3A to 3D are schematic cross-sectional views of a semiconductor device obtained by sequentially performing steps according to a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 4 shows a cross-sectional view of a semiconductor device according to an embodiment of the invention;

FIG. 5 shows a schematic view of an electronic device according to an embodiment of the invention;

fig. 6 shows a schematic structure of a current 3D NAND semiconductor device.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.

It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As mentioned above, the manufacturing method of the conventional 3D NAND memory is relatively expensive, and the following is a brief description of the manufacturing method of the conventional 3D NAND memory with reference to fig. 1A to 1F to facilitate understanding of the present invention.

The current 3D NAND manufacturing method comprises the following steps:

first, as shown in fig. 1A, a semiconductor substrate 100 is provided, the semiconductor substrate including at least a memory region and a control gate region, and a multi-layer stack structure is formed on the semiconductor substrate 100, each stack structure including a dielectric layer 101 and a sacrificial layer 102 on the dielectric layer 101. Illustratively, the dielectric layer 101 is an oxide, such as silicon oxide, and the sacrificial layer 102 is a nitride, such as silicon nitride.

Then, as shown in fig. 1B, the multi-layered stack structure is etched to form a step-like stack structure in the control gate region, which is formed by a photolithography etching process for a number of times related to the number of layers of the control gate layer, using a conventional method as described above, which is exemplarily shown in fig. 1A to 1F as an 8-layer structure, but may be 64 or even 128. This undoubtedly greatly increases the manufacturing cost of the device and the cost per bit (bit) of the memory, and the manufacturing process is complicated.

Next, as shown in fig. 1C, a dielectric layer 103 of the multilayer stack structure is formed. Illustratively, the dielectric layer 103 is an oxide, such as silicon oxide.

Next, as shown in fig. 1D, the sacrificial layer in the stacked structure is removed, and the control gate layer 104 is deposited. When the sacrificial layer 102 is silicon nitride, wet etching with phosphoric acid may be used for removal. Of course, if the material is other material, the material can be removed by corresponding etching liquid. The control gate layer 104 may be a commonly used control gate material such as polysilicon or a metal material. Here, we use metal tungsten to reduce the control gate resistance, which can be formed at the position of the sacrificial layer 102 by chemical deposition.

Next, as shown in fig. 1E, contact holes 105 corresponding to the plurality of control gate layers 104 are formed in the dielectric layer 103. Specifically, contact holes are formed on each step to contact with each control gate layer by photolithography and etching processes.

Finally, as shown in fig. 1F, the contact hole 105 is filled to form a contact plug 106. Illustratively, a metal tungsten material is deposited by chemical vapor deposition, the contact hole 105 is filled, and after the filling, the metal tungsten above the dielectric layer 103 is removed by a planarization operation such as CMP to form a contact plug.

It is understood that the improvement of the present invention lies in the fabrication of the control gate contact plug, and thus only the regions and fabrication steps related to the control gate contact plug are shown in fig. 1A to 1F, and the fabrication of other regions and device layers is not shown for the sake of brevity. For example, the method for manufacturing the 3D NAND memory shown in fig. 1A to 1F further includes the steps of forming a bottom select gate, a top select gate, and a memory array in the memory area, and the like, which will not be described in detail herein.

In the manufacturing method shown in fig. 1A to 1F, multiple photolithography and etching steps are required to form a control gate structure with a step structure, which increases the process cost and the cost of each bit of the memory, while contact holes with different depths are required to be formed when the contact holes are formed, which makes the manufacturing difficult and increases the process difficulty. As shown in fig. 2, the manufacturing method includes step 201: providing a semiconductor substrate, wherein the semiconductor substrate is at least divided into a storage region and a contact plug region; step 102: forming a plurality of stacked structures on the semiconductor substrate of the storage region, wherein each stacked structure comprises a dielectric layer and a control gate layer positioned above the dielectric layer; step S103: forming a first dielectric layer covering the multilayer laminated structure and the contact plug region, forming a plurality of first contact plugs corresponding to the control gate layers in the multilayer laminated structure in the first dielectric layer in the contact plug region, wherein the first contact plugs extend from each control gate layer to the upper surface of the first dielectric layer in an inclined manner; step S104: and forming a second dielectric layer on the first dielectric layer, and forming a plurality of second contact plugs corresponding to the plurality of first contact plugs in the second dielectric layer.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Example one

A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 3A to 3D.

First, as shown in fig. 3A, a semiconductor substrate 300 is provided, the semiconductor substrate 300 is at least divided into a storage region and a contact plug region, and a multilayer stack structure is formed on the semiconductor substrate of the storage region, each stack structure includes a dielectric layer 301 and a control gate layer 302 located above the dielectric layer 301. A first dielectric layer 303 is formed on the semiconductor substrate 300 to cover the multilayer stack structure and the contact plug region, and a patterned hard mask layer 304 is formed on the first dielectric layer 303.

Among them, the semiconductor substrate 300 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate 300. Also, a conductive member may be formed in the semiconductor substrate 300, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure may be formed in the semiconductor substrate, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure as an example, and in this embodiment, the constituent material of the semiconductor substrate 300 is monocrystalline silicon.

The multi-layer stack structure may be formed by a multiple deposition process, wherein the dielectric layer 301 may be formed of a commonly used dielectric material, such as an oxide, nitride or oxynitride. Illustratively, in the present embodiment, the dielectric layer 301 is silicon oxide, which can be formed by a method such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.

The control gate layer 302 may be a semiconductor material such as polysilicon and formed by one of selective Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG). Or a metal material such as metal tungsten may be used to achieve a lower resistance. When a polysilicon material is used, it may be formed directly by multiple depositions, and when a material such as metal tungsten is used, it is preferably formed by forming a sacrificial layer and removing the redeposition on the sacrificial layer in a manner similar to that shown in fig. 1A to 1F to improve adhesion between the layers. Illustratively, in the present embodiment, the control gate layer 302 is made of metal tungsten, which is formed by a similar method as shown in fig. 1A to 1F, and is not described herein again.

The first dielectric layer 303 covers at least the storage region and the contact plug region, and may be made of a conventional dielectric material, such as PSG, BSG, BPSG, USG, low K dielectric or ultra low K (ulk) dielectric. The first dielectric layer 303 may be formed by a process such as a TEOS CVD process, a PECVD silane process, a PECVD TEOS process, an O3-TEOS process, and commonly used processes such as PVD, CVD, ALD, and the like.

The patterned hard mask layer 304 may be formed using any suitable mask material, such as an oxide, nitride, oxynitride, etc., wherein a high selectivity between the patterned hard mask layer 304 and the first dielectric layer 303 is preferred. Illustratively, in the present embodiment, the patterned hard mask layer 304 is a metal hard mask layer, such as titanium nitride, aluminum nitride, etc., which can be formed by PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), sputtering, magnetron sputtering, etc., and patterned by photolithography and etching processes. The patterned hard mask layer 304 exposes the first contact plugs at the open locations on the upper surface of the first dielectric layer 303.

Next, as shown in fig. 3B, a plurality of inclined first contact plugs 305 are formed in the first dielectric layer 303, and each first contact plug 305 is correspondingly connected to one layer of the control gate layer 302.

For example, in the present embodiment, a directional ribbon beam etching (directional ribbon beam etching) etching process is first used to etch the first dielectric layer 303 with the patterned hard mask layer 304 as a mask, so as to form a plurality of inclined first contact holes. The inclination angle of the first contact hole with respect to the semiconductor substrate 300 is, for example, 30 to 60 degrees. And, as shown in fig. 3B, each of the first contact holes correspondingly extends to one of the control gate layers 302 to realize connection with a control gate, so as to input an electrical signal to each of the control gate layers.

Among them, a directional ribbon beam etching (direct ribbon beam etch) etching process is used to realize etching at various angles, see particularly 06FA02-1j.vac.sci.technol.b33(6), disclosed in the Nov/Dec 2015 document. The etching gas contains CF4, CHF3, and the like, and optionally may further include O2, N2, and the like. The flow rate is 50 sccm-500 sccm, 10 sccm-100 sccm, and the pressure is 2 mTorr-50 mTorr, wherein sccm represents cubic centimeter per minute, and mTorr represents milli-millimeter mercury column.

After the first contact holes are formed, the plurality of inclined first contact holes are filled with a conductive material to form a plurality of first contact plugs 305, and each first contact plug 305 is correspondingly connected to one of the control gate layers 302 to make a connection with a control gate, thereby inputting an electrical signal to each control gate layer.

For example, in the present embodiment, the first contact plug 305 is made of a metal tungsten material, and the forming process thereof is, for example: first, a metal tungsten is deposited on the semiconductor substrate 300 by a CVD method, and the metal tungsten fills the conductive material in the first contact holes, and then the plurality of first contact plugs 305 are formed by a planarization operation such as CMP (chemical mechanical planarization) to form a metal tungsten material with a higher area than the upper surface of the first dielectric layer 303.

Next, as shown in fig. 3C, a second dielectric layer 306 is formed on the first dielectric layer 303.

The second dielectric layer 306 at least covers the storage region and the contact plug region, and may be made of a conventional dielectric material, such as PSG, BSG, BPSG, USG, low K dielectric or ultra low K (ulk) dielectric. The first dielectric layer 303 may be formed by a process such as a TEOS CVD process, a PECVD silane process, a PECVD TEOS process, an O3-TEOS process, and commonly used processes such as PVD, CVD, ALD, and the like.

Finally, as shown in fig. 3D, a plurality of second contact plugs 307 corresponding to the plurality of first contact plugs 305 are formed in the second dielectric layer 306.

Specifically, a patterned mask layer, which may be a photoresist layer or a hard mask layer, is formed on the second dielectric layer 306, and then the patterned mask layer is used as a mask to etch the second dielectric layer 306 through a suitable wet or dry etching process to form a plurality of second contact holes corresponding to the plurality of first contact plugs 305, and then the second contact holes are filled with a conductive material to form the second contact plugs 307.

Exemplarily, in the present embodiment, the second contact plug 307 uses a metal tungsten material, and the forming process thereof is, for example: first, a metal tungsten is deposited on the semiconductor substrate 300 by a CVD method, and the metal tungsten fills the conductive material in the second contact holes, and then the second contact plugs 307 are formed by a planarization operation, such as CMP (chemical mechanical planarization), on the metal tungsten material in the upper surface of the second dielectric layer 306.

Preferably, in this embodiment, the second contact plug 307 is vertically disposed in the second dielectric layer 306, so that when the second contact hole is formed by etching, the depth of each contact hole is consistent, and the etching difficulty is low, thereby reducing the difficulty of the whole manufacturing process and further reducing the manufacturing cost.

Now, the process steps performed by the method according to the embodiment of the present invention are completed, and it is understood that the improvement of the present invention lies in the fabrication of the control gate contact plug, so that only the region and the fabrication steps related to the control gate contact plug are shown in fig. 3A to 3D, and the fabrication of other regions and the device layer are not shown for the sake of brevity. That is, the method for manufacturing a semiconductor device of the present embodiment may include other necessary steps before, during, or after the above steps, as well as the above steps. For example, the method for manufacturing the 3D NAND memory shown in fig. 3A to 3D further includes the steps of forming a bottom select gate, a top select gate, and a memory array in the memory region, etc., which are similar to the manufacturing method in the prior art, and will not be described in detail herein.

Example two

The present invention also provides a semiconductor device manufactured by the above method, as shown in fig. 4, the semiconductor device including: the semiconductor device comprises a semiconductor substrate 400, wherein the semiconductor substrate 400 is at least divided into a storage region and a contact plug region, a multilayer laminated structure is formed on the semiconductor substrate of the storage region, and each laminated structure comprises a dielectric layer 401 and a control gate layer 402 positioned above the dielectric layer 401; a first dielectric layer 403, wherein the first dielectric layer 403 covers the multi-layer stacked structure and the contact plug region, a plurality of first contact plugs 404 corresponding to the control gate layers in the multi-layer stacked structure are formed in the first dielectric layer 403 in the contact plug region, and the first contact plugs 404 extend from each control gate layer to the upper surface of the first dielectric layer 403 in an inclined manner; a second dielectric layer 405, the second dielectric layer 405 being located on the first dielectric layer 403, a plurality of second contact plugs 406 corresponding to the plurality of first contact plugs 404 being formed in the second dielectric layer 405, wherein each corresponding first contact plug 404 and second contact plug 406 is connected to one corresponding control gate layer 402.

Wherein the semiconductor substrate 400 may be at least one of the materials mentioned below: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure as an example, may also be formed in the semiconductor substrate. In this embodiment, the constituent material of the semiconductor substrate 400 is monocrystalline silicon.

The dielectric layer 401 may be made of a commonly used dielectric material such as oxide, nitride, or oxynitride. For example, in the present embodiment, the dielectric layer 401 is silicon oxide, which can be formed by a method such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.

The control gate layer 402 may be a semiconductor material such as polysilicon, and formed by one of selective Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG). Or a metal material such as metal tungsten may be used to achieve a lower resistance. When a polysilicon material is used, it may be formed directly by multiple depositions, and when a material such as metal tungsten is used, it is preferably formed by forming a sacrificial layer and removing the redeposition on the sacrificial layer in a manner similar to that shown in fig. 1A to 1F to improve adhesion between the layers. For example, in the present embodiment, the control gate layer 402 is made of metal tungsten, which is formed by a similar method as shown in fig. 1A to 1F, and is not described herein again.

The first and second

dielectric layers

403 and 405 cover at least the storage region and the contact plug region, which may be made of conventional dielectric materials, such as PSG, BSG, BPSG, USG, low K dielectric or ultra low K (ulk) dielectric. The first dielectric layer 303 may be formed by a process such as a TEOS CVD process, a PECVD silane process, a PECVD TEOS process, an O3-TEOS process, and commonly used processes such as PVD, CVD, ALD, and the like.

Each of the control gate layers of the first contact plugs 404 extends obliquely to the upper surface of the first dielectric layer 403, so that the control gate layer 402 does not need to form a step structure, and the second contact plug 406 is disposed corresponding to the first contact plug 404, preferably, in this embodiment, the second contact plug 406 is disposed in the second dielectric layer 405 perpendicular to the semiconductor substrate 400, thereby reducing the process difficulty and the manufacturing cost.

The semiconductor device of the embodiment does not need to manufacture the contact plug with the step structure, so that the manufacturing process difficulty is reduced, the manufacturing cost is reduced, and the semiconductor device has the advantages of simple structure and low cost.

EXAMPLE III

Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: the semiconductor substrate is at least divided into a storage region and a contact plug region, a multilayer laminated structure is formed on the semiconductor substrate of the storage region, and each laminated structure comprises a dielectric layer and a control gate layer positioned above the dielectric layer; a first dielectric layer covering the multi-layer stack structure and the contact plug region, wherein a plurality of first contact plugs corresponding to the control gate layers in the multi-layer stack structure are formed in the first dielectric layer in the contact plug region, and each first contact plug obliquely extends from each control gate layer to the upper surface of the first dielectric layer; a second dielectric layer on the first dielectric layer, a plurality of second contact plugs corresponding to the plurality of first contact plugs formed in the second dielectric layer, wherein each corresponding first and second contact plug is connected to a respective control gate layer.

Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure as an example, may also be formed in the semiconductor substrate. In this embodiment, the constituent material of the semiconductor substrate is monocrystalline silicon.

Preferably, the control gate layer is a metal tungsten layer.

Preferably, the first contact plug and the second contact plug are made of metal tungsten material.

The electronic component may be any electronic component such as a discrete device and an integrated circuit.

The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.

Fig. 5 shows an example of a mobile phone. The exterior of the cellular phone 500 is provided with a display portion 502, operation buttons 503, an external connection port 504, a speaker 505, a microphone 506, and the like, which are included in a housing 501.

The electronic device of the embodiment of the invention has the advantages of low cost and simple manufacture due to the contained semiconductor device. The electronic device also has similar advantages.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor substrate, wherein the semiconductor substrate at least comprises a storage region and a contact plug region;

forming a plurality of stacked structures on the semiconductor substrate of the storage region, wherein each stacked structure comprises a dielectric layer and a control gate layer positioned above the dielectric layer, the control gate layers are the same in size, and the side walls of the control gate layers are flush;

forming a first dielectric layer covering the multilayer laminated structure and the contact plug region, forming a plurality of first contact plugs corresponding to the control gate layers in the multilayer laminated structure in the first dielectric layer in the contact plug region, wherein the first contact plugs extend from each control gate layer to the upper surface of the first dielectric layer in an inclined manner;

forming a second dielectric layer on the first dielectric layer, and forming a plurality of second contact plugs in the second dielectric layer, the second contact plugs being connected to the plurality of first contact plugs,

wherein each corresponding first contact plug and second contact plug is connected with a corresponding control gate layer, and the step of forming the plurality of first contact plugs comprises:

forming a patterned hard mask layer on the first dielectric layer, wherein the patterned hard mask layer defines the opening positions of the first contact plugs on the top surface of the first dielectric layer;

etching the first dielectric layer by taking the hard mask layer as a mask to form a plurality of inclined first contact holes, wherein each first contact hole correspondingly extends to one control gate layer;

filling the plurality of inclined first contact holes with a conductive material to form the plurality of first contact plugs.

2. The method of claim 1, wherein the first dielectric layer is etched using a directional ribbon beam etching process to form a plurality of slanted first contact holes.

3. The method of claim 1, wherein the hard mask layer is a metal hard mask layer.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein an inclination angle of the first contact plug with respect to the semiconductor substrate is 30 to 60 degrees.

5. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the second contact plug is provided vertically to the semiconductor substrate.

6. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the control gate layer comprises a metal tungsten layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the first contact plug and the second contact plug comprise a metal tungsten material.

8. A semiconductor device, comprising:

the semiconductor substrate at least comprises a storage region and a contact plug region, wherein a multilayer laminated structure is formed on the semiconductor substrate of the storage region, each laminated structure comprises a dielectric layer and a control gate layer positioned above the dielectric layer, the control gate layers are the same in size, and the side walls of the control gate layers are flush;

a first dielectric layer covering the multi-layer stack structure and the contact plug region, wherein a plurality of first contact plugs corresponding to the control gate layers in the multi-layer stack structure are formed in the first dielectric layer in the contact plug region, and each first contact plug obliquely extends from each control gate layer to the upper surface of the first dielectric layer;

a second dielectric layer on the first dielectric layer, a plurality of second contact plugs formed in the second dielectric layer and connected to the plurality of first contact plugs,

wherein each corresponding first contact plug and second contact plug is connected with a corresponding control gate layer.

9. The semiconductor device according to claim 8, wherein an inclination angle of the first contact plug with respect to the semiconductor substrate is 30 to 60 degrees.

10. The semiconductor device according to claim 8, wherein the second contact plug is provided vertically to the semiconductor substrate.

11. The semiconductor device of claim 8, wherein the control gate layer comprises a metal tungsten layer.

12. The semiconductor device according to claim 8, wherein the first contact plug and the second contact plug comprise a metal tungsten material.

13. An electronic device comprising the semiconductor device according to any one of claims 8 to 12 and an electronic component connected to the semiconductor device.