CN108649030B

CN108649030B - Semiconductor device, manufacturing method thereof and electronic device

Info

Publication number: CN108649030B
Application number: CN201710160746.2A
Authority: CN
Inventors: 王胜名; 邹陆军; 李绍彬
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-03-17
Filing date: 2017-03-17
Publication date: 2021-02-26
Anticipated expiration: 2037-03-17
Also published as: CN108649030A

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, forming a stack grid on the semiconductor substrate, and forming a gap wall on the side wall of the stack grid; forming an interlayer dielectric layer surrounding the stack gate on the semiconductor substrate; forming a source contact and a drain contact in the interlayer dielectric layer; wherein the top region of the spacer is entirely made of a material having an etch selectivity with respect to the interlayer dielectric layer. The manufacturing method can overcome the problem of reduced breakdown voltage between the gate and the source/drain caused by the removal of the reverse contact etching stop layer on the top of the gate gap wall. The semiconductor device and the electronic apparatus have similar advantages.

Description

Semiconductor device, manufacturing method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.

Background

With the popularity of portable personal devices, the demand for memory is further increasing, the research on memory technology becomes an important direction for information technology research, and the research and development focus is gradually mainly on non-volatile memory (NVM) in order to better improve the storage density and the reliability of data storage. NOR (NOR) type flash memory can be read or programmed in a random access manner and is widely used in mobile devices due to its non-volatility, endurance, and fast access time.

The self-aligned reverse contact technology is suitable for 45nm NOR devices, and in the self-aligned reverse contact manufacturing, the part of the silicon nitride layer used as the self-aligned reverse contact stop layer on the gate spacer oxide can be removed by over grinding when the interlayer dielectric layer is planarized, which causes the liner oxide in the gate spacer (the spacer is generally an oxide-nitride-oxide structure) to be exposed to hydrofluoric acid during the process of forming the reverse contact through the wet process, so that the liner oxide on the top of the spacer is removed, as shown by the dotted line area in FIG. 1, which causes the breakdown voltage between the gate and the source/drain to be low, and causes leakage current even after tungsten and titanium/titanium nitride and the like are filled in the gap (the gap and the reverse contact hole formed after the liner oxide is removed).

Therefore, a new method for manufacturing a semiconductor device is needed to solve the above problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which can overcome the problem of low breakdown voltage between a grid and a source/drain caused by removing an inversion contact etching stop layer at the top of a grid gap wall.

One aspect of the present invention provides a method for manufacturing a semiconductor device, including:

providing a semiconductor substrate, forming a stack grid on the semiconductor substrate, and forming a gap wall on the side wall of the stack grid;

forming an interlayer dielectric layer surrounding the stack gate on the semiconductor substrate;

forming a source contact and a drain contact in the interlayer dielectric layer;

wherein the top region of the spacer is entirely made of a material having an etch selectivity with respect to the interlayer dielectric layer.

Preferably, the forming of the spacer on the sidewall of the stacked gate includes:

forming an initial gap wall on the side wall of the stacked gate, wherein the initial gap wall at least comprises an oxide layer;

removing the part of the oxide layer in the initial gap wall, which is positioned at the top area of the gap wall;

and filling the top area of the gap wall with a material having etching selectivity with the interlayer dielectric layer, so that the top area of the gap wall is completely composed of the material having etching selectivity with the interlayer dielectric layer.

Preferably, the removing the part of the oxide layer in the initial spacer, which is located at the top region of the spacer, comprises:

forming a filling layer surrounding and covering the stack gate on the semiconductor substrate;

removing part of the filling layer to expose the top areas of the stacked gate and the initial gap wall;

removing the part of the oxide layer in the initial gap wall, which is positioned in the top area of the gap wall, by using a wet process;

and removing the residual filling layer.

Preferably, the initial spacer includes a first oxide layer, a nitride layer, and a second oxide layer stacked in this order.

Preferably, the filling layer is an organic filling layer.

Preferably, the material having an etch selectivity with the interlayer dielectric layer is a nitride.

Preferably, the method further comprises forming an inversion contact etching stop layer covering the surface of the semiconductor substrate, the gap wall and the top of the stack gate.

Preferably, the step of filling the top region of the spacer with a material having an etch selectivity with respect to the interlayer dielectric layer is performed in the same step as the step of forming the inversion contact etch stop layer.

Preferably, the formation of the reverse contact etching stop layer adopts a furnace tube process.

According to the manufacturing method of the semiconductor device, the material of the top area of the gap wall is made of the material having the etching selectivity with the interlayer dielectric layer, so that a gap is not formed at the top of the gap wall when the source-drain contact hole is formed through the reverse contact etching process, the phenomenon that the breakdown voltage between the grid and the source/drain electrode is reduced due to the fact that the conductive material is filled into the top area of the gap wall when the source-drain contact is formed is avoided, and the performance and the yield of the device are improved.

Another aspect of the present invention provides a semiconductor device fabricated by the above method, the semiconductor device comprising:

the semiconductor device comprises a semiconductor substrate, a grid stack and a grid array, wherein a gap wall is formed on the side wall of the grid stack;

Preferably, the top region of the spacer is entirely comprised of nitride. .

The semiconductor device provided by the invention can avoid the reduction of the breakdown voltage between the grid and the source/drain, thereby improving the performance and the yield.

A further aspect of the invention provides an electronic device comprising a semiconductor device as described above and an electronic component connected to the semiconductor device.

The electronic device provided by the invention has similar advantages due to the semiconductor device.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 shows a schematic SEM illustration of a current NOR device with spacers formed with voids;

FIG. 2 is a flow chart illustrating steps in a method of fabricating a semiconductor device according to an embodiment of the present invention

Fig. 3A to 17A show cross-sectional views of a semiconductor device along an active region direction obtained by sequentially performing steps according to a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 3B to 17B show cross-sectional views of the semiconductor device obtained by sequentially performing the steps in the method for manufacturing a semiconductor device according to an embodiment of the present invention, along the direction of the isolation structure;

FIG. 18 shows a schematic view of an electronic device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.

It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As mentioned above, the present invention provides a method for manufacturing a semiconductor device, which overcomes the problem that the gate and source/drain breakdown voltages are reduced due to the removal of part of the spacer oxide during the reverse contact manufacturing of the NOR device.

As shown in fig. 2, the manufacturing method includes: step 200, providing a semiconductor substrate, forming a stack grid on the semiconductor substrate, and forming a gap wall on the side wall of the stack grid; step 201, forming an interlayer dielectric layer surrounding the stack gate on the semiconductor substrate; step 202, forming a source contact and a drain contact in the interlayer dielectric layer; wherein the top region of the spacer is entirely made of a material having an etch selectivity with respect to the interlayer dielectric layer.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Example one

A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 3A to 17A and fig. 3B to 17B, in which fig. 3A to 17A show cross-sectional views along an active region direction of a semiconductor device obtained by sequentially performing steps according to the method of manufacturing a semiconductor device according to an embodiment of the present invention; fig. 3B to 17B show cross-sectional views of the semiconductor device obtained by sequentially performing the steps in the method for manufacturing a semiconductor device according to an embodiment of the present invention, along the direction of the isolation structure.

In this embodiment, a method for manufacturing a semiconductor device according to the present invention is specifically described by taking manufacturing of a source-drain contact of a NOR memory as an example. Referring to the above drawings, the method for manufacturing a semiconductor device of the present embodiment includes the following steps:

first, a semiconductor substrate 300 is provided, a stack gate is formed on the semiconductor substrate, an initial spacer 307 is formed on the sidewall of the stack gate, the initial spacer 307 includes at least one oxide layer, and the structure is as shown in fig. 3A and 3B.

Among them, the semiconductor substrate 300 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate 300. Also, a conductive member may be formed in the semiconductor substrate 300, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.

The isolation structure 301 in the semiconductor substrate 300 may be a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, which may be formed by a method commonly used in the art to define and separate active regions. As an example, a Shallow Trench Isolation (STI) structure is employed in the isolation structure 301.

The tunnel oxide layer 302 is illustratively a silicon oxide layer, which can be formed by a method such as a thermal oxidation method, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.

The stacked gate comprises a floating gate 303, a dielectric layer 304, a control gate 305 and a control gate hard mask layer 306 which are sequentially stacked, wherein the floating gate 303 is close to the semiconductor substrate 300, and the control gate 305 is in source-drain contact with the semiconductor substrate 300. Illustratively, the floating gate 303 and the control gate 305 are formed of a semiconductor material such as polysilicon by one of selective Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG). The dielectric layer 304 is made of a dielectric material such as oxide, nitride, etc., and preferably, in the present embodiment, the dielectric layer 304 is an ONO structure (i.e., oxide-nitride-oxide), which has both good interface performance and good dielectric performance and a suitable thickness. The control gate hard mask layer 306 may be formed using a variety of suitable mask materials, such as oxides, nitrides, oxynitrides, and the like. Illustratively, in the present embodiment, the control gate hard mask layer 306 is made of nitride, illustratively silicon nitride, and may be formed by a method such as PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.

An initial spacer 307 is formed on the sidewalls of the stacked gate and includes at least one side oxide layer. Illustratively, the spacer 307 includes a first oxide layer 3070, a nitride layer 3071, and a second oxide layer 3072. The oxide layer and the nitride layer may be formed using a commonly used oxide and nitride, such as silicon dioxide, silicon nitride, silicon oxynitride, or the like.

Next, a filling layer 308 surrounding and covering the stack gate is formed on the semiconductor substrate 300, and the structure is as shown in fig. 4A and 4B.

Various materials with good coverage are used for the filling layer 308, and in this embodiment, an organic filling layer (ODL) is used for the filling layer 308.

It is understood that the thickness of the fill layer 308 is greater than the thickness of the stacked gate, i.e., the fill layer 308 is above the surface of the stacked gate.

Next, a portion of the filling layer 308 is removed to expose the top regions of the stacked gates and the spacers 307, and the structure is shown in fig. 5A and 5B.

Illustratively, a recess etch is performed by a suitable wet or dry etch process to remove portions of the fill layer 308, leaving the top of the fill layer 308 below the surface of the stack gate to expose the top regions of the stack gate and the spacers 307.

Next, the oxide layer in the initial spacer 307 is removed from the top region of the initial spacer 307, and the resulting structure is as shown in fig. 6A and 6B.

Illustratively, the oxide layer in the initial spacer 307 is removed at a portion of the top region of the initial spacer 307 by a wet etching process, such as etching by hydrofluoric acid (HF) with a suitable concentration, and a void is formed at the top region of the initial spacer 307, as shown by the dashed circle in fig. 6A and 6B.

Next, the remaining filling layer 308 is removed, and the resulting structure is shown in fig. 7A and 7B.

Illustratively, the remaining fill layer 308 is removed by suitable dry and wet processes, such as removing the remaining fill layer 308 by a suitable solvent.

Next, an inversion contact etch stop layer 309 is formed covering the semiconductor substrate 300, the spacers, and the stack gate, and the resulting structure is shown in fig. 8A and 8B.

The reverse contact etch stop layer 309 is used as a stop layer when performing a reverse contact etch subsequently, and the reverse contact etch stop layer 309 covers the surface of the semiconductor substrate 300 and the sidewalls (also covering the initial spacers 307) and the top of the stack gate. The reverse contact etch stop layer 309 is made of a conventional material, and in this embodiment, the reverse contact etch stop layer 309 is made of silicon nitride, which is formed by a step-wise well-covered fabrication process to refill the gap in the top region of the initial spacer 307. Illustratively, in the present embodiment, the reverse contact etch stop layer 309 is formed by a furnace process.

In this embodiment, the gap in the top region of the initial spacer 307 is refilled while the reverse contact etch stop layer 309 is formed, so that the top region of the newly formed spacer 307A is entirely composed of silicon nitride, and thus the top of the spacer 307A is entirely composed of a material having an etch selectivity with a subsequently formed interlayer dielectric layer (typically, an oxide), and therefore, the gap is not formed in the top region of the spacer by the reverse contact etch, and accordingly, the conductive material is not refilled.

It is understood that although in the present embodiment, silicon nitride is used to fill the gap in the top region of the spacer, and the top region of the spacer is also made to be entirely silicon nitride, in other embodiments, other materials may be used as long as the material has an etching selectivity with respect to the subsequently formed interlayer dielectric layer, where the etching selectivity refers to an etching selectivity of the material with respect to the subsequently formed interlayer dielectric layer being less than 1:50, so that when the interlayer dielectric layer is subsequently removed by a wet etching process, the material is not affected, i.e., the material is not removed by a wet etching process for subsequently removing the interlayer dielectric layer.

Next, an interlayer dielectric layer 310 covering and surrounding the stack gate is formed on the semiconductor substrate 300, and the resulting structure is as shown in fig. 9A and 9B.

An interlayer dielectric layer 310 is formed in the space between the stacked gates for isolating the respective stacked gates. The interlayer dielectric layer 310 may employ various suitable materials, such as USG (undoped silicon glass), PSG (phosphorus doped silicon glass), BSG (boron doped silicon glass), BPSG (boron phosphorus silicon glass), etc., which may be formed by PVD, CVD, ALD, spin-coating method, etc. It is understood that the dielectric material initially deposited when forming the dielectric layer 310 is inevitably higher than the stacked gate, and thus a planarization operation, such as CMP (chemical mechanical polishing), is performed after the deposition is completed to make the height of the inter-layer dielectric layer 310 and the stacked gate uniform.

Next, an oxide cap layer 311 is formed to cover the inter-layer dielectric layer 310 and the stacked gate, and the structure is shown in fig. 10A and 10B.

The oxide capping layer 311 may be formed of any suitable oxide, such as silicon oxide, which may be formed by PVD, CVD, ALD, or the like. In the embodiment, the oxide layer cover layer 311 is formed by PEOX, i.e., an oxide formed by a plasma enhanced chemical vapor deposition process, which can improve the uniformity of the surface and is beneficial to the completion of the subsequent photolithography process.

Next, an inversion contact hole etching is performed to form an inversion contact hole 312, and the resulting structure is as shown in fig. 11A and 11B.

Illustratively, the inversion contact hole 312 may be formed by:

first, a patterned photoresist layer is formed on the oxide capping layer 311, which defines the shape and position of the inversion contact hole. Illustratively, the inversion contact holes are located in the gaps between the control gates 305 and between the drain contacts.

Next, the oxide capping layer 311 and the interlayer dielectric layer 310 are etched by a suitable wet or dry etching process using the patterned photoresist layer as a mask, and stopped on the inversion contact etch stop layer 309, thereby forming an inversion contact hole 312. The wet etching includes a wet etching process such as hydrofluoric acid, and the dry etching includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. Illustratively, in this implementation, the etching is performed by using a dry etching process, and as an example, in this implementation, the etching is dry etching, and process parameters of the dry etching include: the etching gas includes CF4, CHF3, and the like.

And then, removing the patterned photoresist layer and cleaning.

Next, the inversion contact hole 312 is filled with an insulating material, and the resulting structure is as shown in fig. 12A and 12B.

The insulating material may be any suitable material having a high selectivity with respect to the interlayer dielectric layer 310. In the present embodiment, silicon nitride is used as the insulating material, which may be formed by a furnace process, PVD, CVD, ALD, or the like, so that the insulating layer 313 is formed in the inversion contact hole 312.

It is understood that the height of the insulating layer 313 is higher than that of the oxide cap layer 311 in order to fill the inversion contact hole 312.

Next, an etch back process is performed to remove the portion of the insulating layer 313 higher than the oxide layer cap layer 311, and the resulting structure is shown in fig. 13A and 13B.

Illustratively, an etch back is performed by a suitable wet or dry etching process with the oxide layer capping layer 311 as a stop layer to remove a portion of the insulating layer 3132 above the oxide layer capping layer 311.

Next, planarization is performed to remove the oxide layer cap layer 311 and a portion of the insulating layer 313, and the resulting structure is shown in fig. 14A and 14B.

Illustratively, the oxide cap layer 311 and a portion of the insulating layer 313 are removed by a planarization process such as CMP (chemical mechanical polishing) and stopped on the reverse contact etch stop layer 309, thereby improving surface uniformity and conforming the planarized insulating layer 312 to the stacked gate height.

Next, the interlayer dielectric layer 310 in the region where the contact hole is to be formed is removed to form a source contact hole 314A and a drain contact hole 314B, and the resulting structure is as shown in fig. 15A and 15B.

Illustratively, the interlayer dielectric layer 310 in the region where the contact hole is to be formed is etched by a hydrofluoric acid (HF) wet etching process, thereby forming a source contact hole 314A and a drain contact hole 314B. In the present embodiment, the source contact hole 314A has a vertically long groove shape, and the drain contact hole 314B has a vertical hole shape.

It is understood that although the planarization process is performed to ensure that the capping layer 311 and the insulating layer 313 are removed above the stack gate in the previous step, the reverse contact etch stop layer 309 on the top of the stack gate and on the top of the spacer 307A is removed, since the top region of the spacer 307A is entirely made of a material (silicon nitride) having an etch selectivity with respect to the interlayer dielectric layer 310, no void is formed in the top region of the spacer 307A when the wet process is used to remove the interlayer dielectric layer 310 in this step.

Next, the portion of the reverse contact etch stop layer 309 on the surface of the semiconductor substrate 300 is removed, and the portion 309A on the sidewall of the stack gate is remained, so as to form the structure shown in fig. 16A and 16B.

Illustratively, the portion of the reverse contact etch stop layer 309 on the surface of the semiconductor substrate 300 is removed by a suitable dry etch or physical bombardment to expose the surface of the semiconductor substrate 300 for subsequent formation of source and drain contacts.

Finally, the source contact hole 314A and the drain contact hole 314B are filled with a conductive material, thereby forming a source contact 315A and a drain contact 315B, and the resulting structure is as shown in fig. 17A and 17B.

Illustratively, the conductive material is tungsten (W), and the filling process thereof is, for example: an adhesion layer is formed first, then metal tungsten is deposited on the adhesion layer through a process such as CVD, and finally a planarization operation is performed to remove the part higher than the stacked gate.

Now, the process steps performed by the method according to the embodiment of the present invention are completed, and it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps, but also other required steps, such as LDD implantation, source/drain formation, etc., before, during, or after the above steps

According to the manufacturing method of the semiconductor device, the oxide layer at the top area of the gate spacer is removed, and then the top area is refilled, so that the material at the top area of the spacer is completely the material with the etching selectivity with the interlayer dielectric layer, and therefore, a gap is not formed at the top of the spacer when the source-drain contact hole is formed through the reverse contact etching process, and therefore the situation that the breakdown voltage between the gate and the source/drain is reduced due to the fact that the conductive material is filled into the top area of the spacer when the source-drain contact is formed is avoided, and the performance and the yield of the device are improved.

Example two

The present invention also provides a semiconductor device manufactured by the above method, as shown in fig. 17A and 17B, the semiconductor device including: a semiconductor substrate 300 having a stack gate formed on the semiconductor substrate 300, and a spacer 307A formed on a sidewall of the stack gate 300; an interlayer dielectric layer surrounding the stack gate is formed on the semiconductor substrate 300; forming a source contact 315A and a drain contact 315B in the interlayer dielectric layer; wherein the top region of the spacer 307A is entirely made of a material having an etching selectivity with the interlayer dielectric layer.

The isolation structure 301 in the semiconductor substrate 300 may be a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, which may be formed by a method commonly used in the art to define and separate active regions. As an example, a Shallow Trench Isolation (STI) structure is employed in the isolation structure 301. The tunnel oxide layer 302 is illustratively a silicon oxide layer

The stacked gate comprises a floating gate 303, a dielectric layer 304, a control gate 305 and a control gate hard mask layer 306 which are sequentially stacked, wherein the floating gate 303 is close to the semiconductor substrate 300, and the control gate 305 is in source-drain contact with the semiconductor substrate 300. Illustratively, the floating gate 303 and the control gate 305 are made of a semiconductor material such as polysilicon, and the dielectric layer 304 is made of a dielectric material such as oxide, nitride, etc., preferably, in the present embodiment, the dielectric layer 304 is made of an ONO structure (i.e., oxide-nitride-oxide), which has both good interface performance and good dielectric performance and a suitable thickness.

Spacers 307A are formed on the sidewalls of the stacked gate, and the top regions of the spacers 307A are all comprised of a material having an etch selectivity with the interlayer dielectric layer. Illustratively, the bottom region of the spacer 307A includes a first oxide layer 3070, a nitride layer 3071 and a second oxide layer 3072. The oxide layer and the nitride layer may be formed using a commonly used oxide and nitride, such as silicon dioxide, silicon nitride, silicon oxynitride, or the like. The top region of the spacer 307A is entirely silicon nitride.

The source contact 315A is in the form of a vertically long trench and the drain contact 315B is in the form of a vertical hole. The adjacent drain contacts 315B are isolated from each other by an insulating layer 313.

The semiconductor device of the embodiment can prevent the breakdown voltage between the gate and the source/drain from being reduced, thereby improving the performance and the yield.

EXAMPLE III

Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: the semiconductor device comprises a semiconductor substrate, a grid stack and a grid array, wherein a gap wall is formed on the side wall of the grid stack; forming an interlayer dielectric layer surrounding the stack gate on the semiconductor substrate; forming a source contact and a drain contact in the interlayer dielectric layer; wherein the top region of the spacer is entirely made of a material having an etch selectivity with respect to the interlayer dielectric layer.

Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, may be formed in the semiconductor substrate. As an example, in the present embodiment, the constituent material of the semiconductor substrate is single crystal silicon.

The isolation structure may be a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, which may be formed by methods commonly used in the art to define and separate the active regions. As an example, a Shallow Trench Isolation (STI) structure is employed in the isolation structure.

The stacked gate includes a floating gate, a dielectric layer, a control gate, a hard mask layer, and the like, for example, formed by the manufacturing method described in the first embodiment of the present invention, and details are not described herein.

The electronic component may be any electronic component such as a discrete device and an integrated circuit.

The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.

Among them, fig. 18 shows an example of a cellular phone. The exterior of the cellular phone 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.

The electronic device of the embodiment of the invention has similar advantages because the semiconductor device can prevent the breakdown voltage between the grid and the source/drain from being reduced, thereby improving the performance and the yield.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of fabricating a semiconductor device for fabricating a NOR device, comprising:

the forming a spacer on a sidewall of the stacked gate includes: forming an initial gap wall on the side wall of the stacked gate, wherein the initial gap wall at least comprises an oxide layer; removing the part of the oxide layer in the initial gap wall, which is positioned at the top area of the gap wall; filling the top area of the gap wall with a material having etching selectivity with the interlayer dielectric layer, so that the top area of the gap wall is entirely composed of the material having etching selectivity with the interlayer dielectric layer;

forming source and drain contacts in the interlayer dielectric layer.

2. The method for manufacturing the semiconductor device according to claim 1, wherein the removing the portion of the oxide layer in the initial spacer located at the top region of the spacer comprises:

and removing the residual filling layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the initial spacer comprises a first oxide layer, a nitride layer, and a second oxide layer stacked in this order.

4. The method for manufacturing a semiconductor device according to claim 2, wherein the filling layer is an organic filling layer.

5. The method according to claim 1, wherein the material having an etching selectivity with respect to the interlayer dielectric layer is a nitride.

6. The method of claim 1, further comprising forming an inverted contact etch stop layer overlying the surface of the semiconductor substrate, the spacer, and the top of the stacked gate.

7. The method of manufacturing a semiconductor device according to claim 6, wherein the step of filling the top region of the spacer with a material having an etch selectivity with respect to the interlayer dielectric layer is performed in the same step as the step of forming an inversion contact etch stop layer.

8. The method for manufacturing a semiconductor device according to claim 6 or 7, wherein the reverse contact etch stop layer is formed by a furnace process.

9. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 8, comprising:

the semiconductor device comprises a semiconductor substrate, a grid stack and a grid array, wherein a gap wall is formed on the side wall of the grid stack; the spacer comprises at least one oxide layer; the part of the oxide layer in the clearance wall, which is positioned in the top area of the clearance wall, is made of a material with etching selectivity with the interlayer dielectric layer;

forming source and drain contacts in the interlayer dielectric layer.

10. The semiconductor device of claim 9, wherein a top region of the spacer is entirely comprised of nitride.

11. An electronic device comprising the semiconductor device according to claim 9 or 10 and an electronic component connected to the semiconductor device.