CN107437549A - A kind of semiconductor devices and preparation method thereof, electronic installation - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic installation Download PDFInfo
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of preparation method of semiconductor devices, semiconductor devices and electronic installation, and the preparation method includes：Semiconductor substrate is provided, forms multiple stacking gate structures on the semiconductor substrate, going back remnants on the stacking gate structure has hardmask material；Form the spacer material layer for covering the Semiconductor substrate, stacking gate structure and hardmask material；The remaining hardmask material and the portion gap wall material bed of material are removed with exposed portion control gate；The part control gate exposed is set to be changed into silicide；The separation layer for covering the multiple stacking gate structure is formed, the separation layer to form the height space consistent with the stacking gate structure between the stacking gate structure.The preparation method can reduce wordline interference, improve cycle period/read-write number of flash memory.The semiconductor devices has the advantages of similar with electronic installation.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its
Preparation method, electronic installation.
Background technology
With the development of manufacture of semiconductor technology, access speed has been developed in terms of storage device
Faster flash memory (flash memory).Flash memory have can repeatedly enter row information
The action such as deposit, reading and erasing, and the spy that the information being stored in will not also disappear after a loss of power
Property, therefore, flash memory is as the widely used one kind of PC and electronic equipment
Nonvolatile memory.And NAND (NAND gate) fast storages with big storage due to holding
Amount and relatively high performance, it is widely used in the field that read/write requires higher.Recently, NAND
The capacity of flash memory chip has reached 2GB, and size increases sharply.Develop
Go out the solid state hard disc based on NAND quick-flash memory chip, and be used as in pocket computer
Storage device.Therefore, in recent years, NAND quick-flash memory is widely used as in embedded system
Storage device, also serve as the storage device in personal computer system.
However, interference problem is prevalent in conventional NAND flash memory, interference is asked
Topic is Capacitance Coupled caused by the electric field action of juxtaposition memory cell (bit cell) when programmed
Effect, in NAND quick-flash memory, the interference between wordline is to the total dry of whole device
To disturb and play a major role, the interference between wordline is bigger, and total interference is bigger, and total interference is bigger,
The cycle period of device/read-write number is with regard to smaller.
Therefore, in order to improve the cycle period of NAND quick-flash memory, it is necessary to propose one
The new preparation method of kind, to solve the above problems.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply and be further described in mode part.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean to attempt the protection domain for determining technical scheme claimed.
In view of the shortcomings of the prior art, the present invention proposes a kind of preparation method of semiconductor devices,
The interference problem of flash memory can be reduced, so as to improve the cycle period of flash memory/
Read and write number.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of semiconductor devices
Preparation method, this method include：Semiconductor substrate is provided, formed on the semiconductor substrate
Multiple stacking gate structures, each stacking gate structure include the floating boom sequentially formed from bottom to top
Oxide layer, floating boom, gate dielectric layer and control gate, the also remnants on the stacking gate structure
There is hardmask material；Formed and cover Semiconductor substrate, stacking gate structure and the hard mask material
The spacer material layer of the bed of material；Remove the remaining hardmask material and portion gap wall
Material layer is with exposed portion control gate；The part control gate exposed is set to be changed into silicide；
The separation layer for covering the multiple stacking gate structure is formed, the separation layer causes the stacking gate
The height space consistent with the stacking gate structure is formed between structure.
Further, it is described to remove remaining hardmask material and the portion gap wall material bed of material
Included with the step of exposed portion control gate：Formed and surround the slow of the remaining hardmask material
Rush layer；The sacrifice separation layer in gap between the multiple stacking gate structure is filled in formation, described sacrificial
Domestic animal separation layer has space；Remove remaining hardmask material, cushion and the part
Separation layer and the portion gap wall material bed of material are sacrificed with exposed portion control gate.
Further, it is described to remove remaining hardmask material and the portion gap wall material bed of material
Also included with the step of exposed portion control gate：Remove the remaining sacrifice separation layer and institute
State the spacer material layer of stacking gate structural top sidewall residue.
Further, it is described to remove remaining hardmask material and the portion gap wall material bed of material
Included with the step of exposed portion control gate：Etching is formed on the spacer material layer to stop
Only layer；The sacrifice separation layer in gap between the multiple stacking gate structure is filled in formation；Remove institute
State remnants hardmask material, and partial sacrifice separation layer and the portion gap wall material bed of material with
Exposed portion control gate；Remove the remaining sacrifice separation layer；Remove the remaining etching
Stop-layer.
Further, the remaining hardmask material, and partial sacrifice isolation are being removed
Layer and the portion gap wall material bed of material are also to include before the step of the control gate of exposed portion：Form the
One dielectric layer.
Further, the space is in mushroom.
The preparation method of the semiconductor devices of the present invention, formed and cover the multiple stacking gate structure
Separation layer, the separation layer to form height and the stacking between the stacking gate structure
The consistent space of grid structure, so that the dielectric coefficient between stacking gate structure diminishes, so as to
So that wordline interference reduces as caused by capacitance coupling effect, and then improve flash memory
Cycle period/read-write number.
Another aspect of the present invention provides a kind of semiconductor devices, and the semiconductor devices includes：Partly lead
Body substrate, formed with multiple stacking gate structures, each stacking gate in the Semiconductor substrate
Structure includes floating gate oxide layers, floating boom, gate dielectric layer and the control sequentially formed from bottom to top
Grid, formed with clearance wall in the side wall of the stacking gate, control described in the clearance wall exposed portion
Grid processed, the part control gate exposed are formed as silicide, and the multiple stacking of covering
The separation layer of grid structure, the separation layer to form height and institute between the stacking gate structure
State the consistent space of stacking gate structure.
Further, the space is in mushroom.
Semiconductor devices proposed by the present invention, due to having and the heap between stacking gate structure
The consistent space of stacked gate structure so that the dielectric coefficient between stacking gate structure diminishes, so that
Obtaining the wordline interference as caused by capacitance coupling effect reduces, and then improves following for flash memory
The ring cycle/read-write number.
Further aspect of the present invention provides a kind of electronic installation, it include a kind of semiconductor devices and
The electronic building brick being connected with the semiconductor devices, the semiconductor devices include：Semiconductor
Substrate, formed with multiple stacking gate structures, each stacking gate knot in the Semiconductor substrate
Structure includes floating gate oxide layers, floating boom, gate dielectric layer and the control gate sequentially formed from bottom to top,
Formed with clearance wall in the side wall of the stacking gate, control described in the clearance wall exposed portion
Grid, the part control gate exposed are formed as silicide, and the multiple stacking gate of covering
The separation layer of structure, the separation layer to be formed between the stacking gate structure height with it is described
The consistent space of stacking gate structure.
Electronic installation proposed by the present invention, due to above-mentioned semiconductor device, thus there is class
As advantage.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the preparation method of semiconductor devices according to an embodiment of the present invention
Flow chart of steps；
Fig. 2A~Fig. 2 I show the making of semiconductor devices according to an embodiment of the present invention
Method implements the diagrammatic cross-section that each step obtains semiconductor devices successively；
Fig. 3 shows the preparation method of semiconductor devices according to an embodiment of the present invention
Flow chart of steps；
Fig. 4 A~Fig. 4 F show the system of the semiconductor devices according to another embodiment of the present invention
Make method and implement the diagrammatic cross-section that each step obtains semiconductor devices successively；
The preparation method that Fig. 5 shows the semiconductor devices according to another embodiment of the present invention
Step flow chart；
Fig. 6 shows the structural representation of semiconductor devices according to an embodiment of the present invention；
Fig. 7 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is it is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, those skilled in the art be will fully convey the scope of the invention to and.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated identical accompanying drawing from beginning to end
Mark represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term limits.These terms be used merely to distinguish an element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., herein can for convenience description and by use from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, "one" and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, the presence or addition of element, part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
As it was previously stated, in order to reduce the interference problem of flash memory, to improve flash memory
Cycle period/read-write number, the present invention provides a kind of preparation method of semiconductor devices, uses
In making flash memory, as shown in figure 1, this method includes：Step 101：Offer is partly led
Body substrate, multiple stacking gate structures are formed on the semiconductor substrate, each stacking gate
Structure includes floating gate oxide layers, floating boom, gate dielectric layer and the control sequentially formed from bottom to top
Grid, on the stacking gate structure going back remnants has hardmask material；Step 102：Formed
Cover the spacer material layer of the Semiconductor substrate, stacking gate structure and hardmask material；
Step S103：Remove the remaining hardmask material and the portion gap wall material bed of material with
Exposed portion control gate；Step S104：The part control gate exposed is set to be changed into silication
Thing；Step S105：Form the separation layer for covering the multiple stacking gate structure, the isolation
Layer to form the height space consistent with the stacking gate structure between the stacking gate structure.
The preparation method of semiconductor devices proposed by the present invention, the multiple heap is covered by being formed
The separation layer of stacked gate structure, and the separation layer to form height between the stacking gate structure
The space consistent with the stacking gate structure, the dielectric coefficient between so described stacking gate structure
Diminish, so that wordline interference reduces as caused by capacitance coupling effect, and then improve fast
The cycle period of flash memory/read-write number.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail
It is as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
Semiconductor below with reference to Fig. 2A~Fig. 2 I and Fig. 3 to an embodiment of the present invention
The preparation method of device is described in detail.It is understood that for flash memory, not only
Including memory (cell), in addition to external zones, and the making of the semiconductor devices of the present embodiment
The memory block mainly for flash memory of method, thus only shown in Fig. 2A~Fig. 2 I
The diagrammatic cross-section in flash memory storage area.
First, step 301 is performed：Semiconductor substrate 200 is provided, in the Semiconductor substrate
Upper to form multiple stacking gate structures, each stacking gate structure includes sequentially forming from bottom to top
Floating gate oxide layers (not shown), floating boom 201, gate dielectric layer 202 and control gate 203,
Going back remnants on the stacking gate structure has hardmask material 204, and described in formation
Formed after stacking gate structure and cover Semiconductor substrate 200, stacking gate structure and the hard mask
The side wall of material layer 204 and the spacer material layer 205 on the surface of hardmask material 204, institute
The structure of formation is as shown in Figure 2 A.
Wherein, Semiconductor substrate 200 can be at least one of following material being previously mentioned：
Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V chemical combination
Thing semiconductor, in addition to sandwich construction etc. for forming of these semiconductors or be silicon-on-insulator
(SOI), be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example,
In the present embodiment, the constituent material of Semiconductor substrate 200 selects monocrystalline silicon.
Stacking gate structure is formed by method commonly used in the art, in the present embodiment the stacking gate
Structure be used as fast storage memory block (cell area) wordline, it is exemplary can be under
State step making：Floating gate oxide layers, floating gate material layer, grid are deposited in half conductive substrate 200
Dielectric layer and control gate material layer, and hardmask material, then pass through the works such as chemical wet etching
Skill graphically the floating gate oxide layers, floating gate material layer, gate dielectric and control gate material layer
So as to form multiple stacking gate structures, the hardmask material is then removed.In the process,
Although the hard mask layer is removed by suitable technique, by a variety of causes is in institute
Stating still remnants on stacking gate structure has hardmask material, as shown in Fig. 2A 204.
Exemplarily, in the present embodiment, the remaining hardmask material 204 is oxide layer, than
Such as the oxide of silicon.
Spacer material layer 205 is formed in the Semiconductor substrate 200, stacking gate structure and hard
On the side wall of mask layer 204 and the surface of hardmask material 204, it can use all
Such as oxide, nitride material, and (physical vapor is sunk by PVD commonly used in the art
Product), CVD (chemical vapor deposition), ALD (ald) the methods of formed.Show
Example property, spacer material layer 205 uses oxide in the present embodiment, and it passes through thermal oxide
Method is formed, and thickness is
It is understood that the quantity of stacking gate structure is true according to device design requirement and specification
It is fixed, in the present embodiment, 6 stacking gate structures are only schematically shown, it does not represent stacking gate knot
The exact amount of structure.
Then, step 302 is performed, etching is formed on the spacer material layer 205 and is stopped
Only layer 206, the structure formed is as shown in Figure 2 B.
Etching stopping layer 206 can also use the materials such as oxide, nitride, and pass through
PVD (physical vapour deposition (PVD)) commonly used in the art, CVD (chemical vapor deposition), ALD
The methods of (ald), is formed.Exemplarily, separation layer is sacrificed in the present embodiment
207 use oxide, such as the oxide of silicon, and it is formed by Atomic layer deposition method, thick
Spend and be
Then, step 303 is performed, is formed and fills gap between the multiple stacking gate structure
Separation layer 207 is sacrificed, the structure formed is as shown in Figure 2 C.
The materials such as oxide, nitride can also be used by sacrificing separation layer 207, and be passed through
PVD (physical vapour deposition (PVD)) commonly used in the art, CVD (chemical vapor deposition), ALD
The methods of (ald), is formed.Exemplarily, in the present embodiment between etching stopping layer
206 use nitride, such as silicon nitride, and it is formed by Atomic layer deposition method, and thickness is
Then, step 304 is performed, forms the first dielectric layer 208, the structure formed is as schemed
Shown in 2D.
As previously described, because device includes external zones and memory block, therefore carved for the ease of follow-up
Erosion, in the present embodiment, preferably depositing first dielectric layer (ILD0) 208 is simultaneously in this step
Planarization is performed, so that external zones and memory block are highly consistent.First dielectric layer (ILD0)
208 can be formed using method commonly used in the art, and it can use conventional PSG, and (phosphorus is mixed
Miscellaneous silica glass) or BPSG (boron-phosphorosilicate glass), it will not be repeated here.
Then, step 305 is performed, execution is etched back to, to remove the on stacking gate structure
One dielectric layer and remaining hard mask layer, and remove the portion gap wall material bed of material, etching stopping layer and
Separation layer is sacrificed with exposed portion control gate, and the structure formed is as shown in Figure 2 E.
In the present embodiment, removed by etch-back (etch back) on stacking gate structure
First dielectric layer 208 and remaining hard mask layer 204, and remove the portion gap wall material bed of material 205,
Etching stopping layer 206 and sacrifice separation layer 207 are with exposed portion control gate 203.Exemplarily,
In the present embodiment, the depth h being etched back to is
The etch back process can be wet etching process or dry method etch technology, dry etching
Technique includes but is not limited to：Reactive ion etching (RIE), ion beam milling, plasma erosion
Carve or be cut by laser.In addition, no matter which kind of etching technics used, according to the first dielectric need to be caused
Layer and remaining hard mask layer, spacer material layer, etching stopping layer and the relative control of sacrifice separation layer
Grid processed have high selectivity, in order to avoid the Damage Coutrol grid when being etched back to.
It is exemplary, in this embodiment, in this embodiment, eatch-back is performed using dry etch process
Carve, and as an example, in the present embodiment, described to be etched to dry etching, the dry method is lost
The technological parameter at quarter includes：Etching gas includes the gases such as CF4, CHF3, its flow difference
For 50sccm~500sccm, 10sccm~100sccm, pressure is 2mTorr~50mTorr, its
In, sccm represents cc/min, and mTorr represents milli millimetres of mercury.
Then, step 306 is performed, removes remaining sacrifice separation layer 207, the knot formed
Structure is as shown in Figure 2 F.
In this step, can be removed by suitable dry etching or wet etching remaining sacrificial
Domestic animal separation layer 207.Exemplarily, due in this embodiment, sacrificing isolation in the present embodiment
Layer 207 uses expensive oxide, thus can be carved by HF (hydrofluoric acid) wet method of dilution
Etching off is stopped on etching stopping layer 206 except remaining sacrifice separation layer 207.Certainly,
If sacrificing separation layer 207 uses other materials, can be gone by other suitable methods
Remove.
Then, step 307 is performed, removes remaining etching stopping layer 206, the knot formed
Structure is as shown in Figure 2 G.
In this step, remaining erosion can be removed by suitable dry etching or wet etching
Carve stop-layer 206.Exemplarily, in the present embodiment, because etching stopping layer 206 uses
Silicon nitride, thus remaining etching stopping layer 206 can be removed by hot phosphoric acid.Certainly,
If etching stopping layer 206 uses other materials, can be gone by other suitable methods
Remove.
Then, step 308 is performed, makes to expose control gate formation silicide 209, is formed
Structure is as illustrated in figure 2h.
Exemplarily, silicide 209 can be formed by method commonly used in the art, for example be passed through
The step such as nickel deposition, first time rapid thermal annealing, wet etching, second thermal annealing is formed,
It will not be repeated here.
Finally, step 309 is performed, forms the separation layer 210 for covering multiple stacking gate structures,
The separation layer 210 to form height and the stacking gate structure one between stacking gate structure
The space 211 of cause, the structure formed is as shown in figure 2i.
It is exemplary, in the present embodiment, work is deposited by the oxide for implementing step coverage difference
Skill, the separation layer 210 for covering multiple stacking gate structures is formed, and the separation layer 210 causes
The height space 211 consistent with the stacking gate structure is formed between stacking gate structure, this be by
Gap depth-to-width ratio is larger between stacking gate structure, when oxide terraced spreadability difference and deposition
Gao Shi, separation layer 210 is before the interval between having filled stacking gate just in stacking gate knot
Structure top close, so as between stacking gate structure formed height it is consistent with stacking gate structure from
Layer space 211.So, due to the presence in space 211, between stacking gate structure (or isolation
The dielectric coefficient of layer 210) reduces so that and the capacitance coupling effect between stacking gate reduces, from
And the wordline interference of device is reduced, improve cycle period/read-write number of device.It is exemplary
Ground, in the present embodiment, space 211 are in mushroom, i.e. top is big, and middle part and bottom are small
Structure.
It should be noted that so-called height is consistent with stacking gate structure herein refers to space
211 height is identical or close with the height of stacking gate structure, or, in other words, space is certainly
The surface of substrate 200 upwardly extends the region for reaching separation layer 210 close at the top of stacking gate.
So far, the processing step that method according to embodiments of the present invention is implemented, Ke Yili are completed
Solution, the present embodiment manufacturing method of semiconductor device not only includes above-mentioned steps, in above-mentioned step
Before rapid, among or may also include other desired step, such as ion doping afterwards, it is all
It is included in the range of this implementation preparation method.
It is understood that the manufacture method for the semiconductor devices that the present embodiment proposes, not only may be used
For fast storage device processed, and it can be used for manufacturing other and apply analogously for this method
The device with stacking gate structure.
Embodiment two
Semiconductor below with reference to Fig. 4 A~Fig. 4 F and Fig. 5 to an embodiment of the present invention
The preparation method of device is described in detail.It is understood that for flash memory, not only
Including memory (cell), in addition to external zones, and the making of the semiconductor devices of the present embodiment
The memory block mainly for flash memory of method, thus only shown in Fig. 4 A~Fig. 4 F
The diagrammatic cross-section in flash memory storage area.
First, step 501 is performed：Semiconductor substrate 400 is provided, in the Semiconductor substrate
Upper to form multiple stacking gate structures, each stacking gate structure includes sequentially forming from bottom to top
Floating gate oxide layers (not shown), floating boom 401, gate dielectric layer 402 and control gate 403,
Going back remnants on the stacking gate structure has hardmask material 404, and described in formation
Formed after stacking gate structure and cover Semiconductor substrate 400, stacking gate structure and the hard mask
The side wall of material layer 404 and the spacer material layer 405 on the surface of hardmask material 404, with
And form the cushion 406 for surrounding the remaining hardmask material 404, the structure formed
As shown in Figure 4 A.
Wherein, Semiconductor substrate 400 can be at least one of following material being previously mentioned：
Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V chemical combination
Thing semiconductor, in addition to sandwich construction etc. for forming of these semiconductors or be silicon-on-insulator
(SOI), be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example,
In the present embodiment, the constituent material of Semiconductor substrate 400 selects monocrystalline silicon.
Stacking gate structure is formed by method commonly used in the art, in the present embodiment the stacking gate
Structure be used as fast storage memory block (cell area) wordline, it is exemplary can be under
State step making：Floating gate oxide layers, floating gate material layer, grid are deposited in half conductive substrate 400
Dielectric layer and control gate material layer, and hardmask material, then pass through the works such as chemical wet etching
Skill graphically the floating gate oxide layers, floating gate material layer, gate dielectric and control gate material layer
So as to form multiple stacking gate structures, the hardmask material is then removed.In the process,
Although the hard mask layer is removed by suitable technique, by a variety of causes is in institute
Stating still remnants on stacking gate structure has hardmask material, as shown in 404 in Fig. 4 A.
Exemplarily, in the present embodiment, the remaining hardmask material 404 is oxide layer, than
Such as the oxide of silicon.
Spacer material layer 405 is formed in the Semiconductor substrate 400, stacking gate structure and hard
On the side wall of mask layer 404 and the surface of hardmask material 404, it can use all
Such as oxide, nitride material, and (physical vapor is sunk by PVD commonly used in the art
Product), CVD (chemical vapor deposition), ALD (ald) the methods of formed.Show
Example property, spacer material layer 405 uses oxide in the present embodiment, and it passes through thermal oxide
Method is formed, and thickness is
Cushion 406 can pass through PECVD (plasma reinforced chemical vapour deposition technique)
Material layer deposited atop oxide is covered in stacking gate and remnants firmly to be formed, the cushion 406 causes
Larger pattern is formed at the top of stacked structure, as shown in Figure 4 A.
It is understood that the quantity of stacking gate structure is true according to device design requirement and specification
It is fixed, in the present embodiment, 6 stacking gate structures are only schematically shown, it does not represent stacking gate knot
The exact amount of structure.
Then, step 502 is performed, is formed and fills gap between the multiple stacking gate structure
Separation layer 407 is sacrificed, the sacrifice separation layer has space 408, and the structure formed is as schemed
Shown in 4B.
The materials such as oxide, nitride can also be used by sacrificing separation layer 407, and be passed through
PVD (physical vapour deposition (PVD)) commonly used in the art, CVD (chemical vapor deposition), ALD
The methods of (ald), is formed.Exemplarily, separation layer is sacrificed in the present embodiment
407 use oxide, such as the oxide of silicon, and it is formed by Atomic layer deposition method, thick
Spend and beAnd due at the top of stacked structure formed with larger pattern (cushion 406),
So that the distance between stacked structure top is shortened, thus when deposited sacrificial separation layer 407,
Stacked structure top area can be closed first, and now major part space in middle and lower part region is not yet filled out
Fill so that the separation layer 407 of formation has space 408.
Then, step 503 is performed, removes the remaining hardmask material 404, buffering
Layer 406 and partial sacrifice separation layer 407 and the portion gap wall material bed of material 405 are with exposed portion
Control gate 403, the structure formed is as shown in Figure 4 C.
In the present embodiment, the remaining hard mask is removed by etch-back (etch back)
Material layer 404, cushion 406 and partial sacrifice separation layer 407 and portion gap wall material
Layer 405 is with exposed portion control gate 403.Exemplarily, in the present embodiment, it is etched back to
Depth h is
The etch back process can be wet etching process or dry method etch technology, dry etching
Technique includes but is not limited to：Reactive ion etching (RIE), ion beam milling, plasma erosion
Carve or be cut by laser.In addition, no matter which kind of etching technics used, according to the first dielectric need to be caused
Layer and remaining hard mask layer, spacer material layer, etching stopping layer and the relative control of sacrifice separation layer
Grid processed have high selectivity, in order to avoid the Damage Coutrol grid when being etched back to.
It is exemplary, in this embodiment, in this embodiment, eatch-back is performed using dry etch process
Carve, and as an example, in the present embodiment, described to be etched to dry etching, the dry method is lost
The technological parameter at quarter includes：Etching gas includes the gases such as CF4, CHF3, its flow difference
For 50sccm~500sccm, 10sccm~100sccm, pressure is 2mTorr~50mTorr, its
In, sccm represents cc/min, and mTorr represents milli millimetres of mercury.
Then, step 504 is performed, removes the remaining sacrifice separation layer 407 and described
The spacer material layer 405 of stacking gate structural top sidewall residue, the structure formed such as Fig. 4 D
It is shown.
In this step, it can be removed, gone by suitable dry etching or wet-etching technology
Except remaining separation layer 407 and the stacking gate structural top sidewall residue of sacrificing
Spacer material layer 405.Exemplarily, due to spacer material layer 405 in the present embodiment,
Sacrifice separation layer 407 and use oxide, therefore can be removed by the HF of dilution.Certainly,
If the intermediate gap wall material bed of material 405, sacrificing the material of separation layer 407 difference, or use other materials
Material, then it can be removed by other suitable methods.
Then, step 505 is performed, the control gate for making to expose forms silicide 409, is formed
Structure as shown in Figure 4 E.
Exemplarily, silicide 409 can be formed by method commonly used in the art, for example be passed through
The step such as nickel deposition, first time rapid thermal annealing, wet etching, second thermal annealing is formed,
It will not be repeated here.
Finally, step 506 is performed, forms the separation layer 410 for covering multiple stacking gate structures,
The separation layer 410 to form height and the stacking gate structure one between stacking gate structure
The space 411 of cause, the structure formed is as illustrated in figure 4f.
It is exemplary, in the present embodiment, work is deposited by the oxide for implementing step coverage difference
Skill, the separation layer 410 for covering multiple stacking gate structures is formed, and the separation layer 410 causes
The height space 411 consistent with the stacking gate structure is formed between stacking gate structure, this be by
Gap depth-to-width ratio is larger between stacking gate structure, when oxide terraced spreadability difference and deposition
Gao Shi, separation layer 410 is before the interval between having filled stacking gate just in stacking gate knot
Structure top close, so as between stacking gate structure formed height it is consistent with stacking gate structure from
Layer space 411.So, due to the presence in space 411, between stacking gate structure (or isolation
The dielectric coefficient of layer 410) reduces so that and the capacitance coupling effect between stacking gate reduces, from
And the wordline interference of device is reduced, improve cycle period/read-write number of device.It is exemplary
Ground, in the present embodiment, space 411 are in mushroom, i.e. top is big, and middle part and bottom are small
Structure.
It should be noted that so-called height is consistent with stacking gate structure herein refers to space
411 height is identical or close with the height of stacking gate structure, or, in other words, space is certainly
The surface of substrate 400 upwardly extends the region for reaching separation layer 410 close at the top of stacking gate.
So far, the processing step that method according to embodiments of the present invention is implemented, Ke Yili are completed
Solution, the present embodiment manufacturing method of semiconductor device not only includes above-mentioned steps, in above-mentioned step
Before rapid, among or may also include other desired step, such as ion doping afterwards, it is all
It is included in the range of this implementation preparation method.It is understood that the half of the present embodiment proposition
The manufacture method of conductor device, fast storage device processed is can be not only used for, and can used
The device with stacking gate structure that other apply analogously for this method in manufacture.
Embodiment three
The present invention also provides a kind of semiconductor devices, as shown in fig. 6, the semiconductor devices includes：
Semiconductor substrate 600, formed with multiple stacking gate structures in the Semiconductor substrate 600, often
The individual stacking gate structure include sequentially form from bottom to top floating gate oxide layers (not shown),
Floating boom 601, gate dielectric layer 602 and control gate 603, formed in the side wall of the stacking gate
Clearance wall 604, control gate described in the exposed portion of clearance wall 604, the part exposed
Control gate forms silicide 605, and the separation layer 606 of the multiple stacking gate structure of covering,
The separation layer 606 to form height and the stacking gate knot between the stacking gate structure
The consistent space 607 of structure.
Wherein Semiconductor substrate 600 can be at least one of following material being previously mentioned：Si、
Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compounds half
Conductor, in addition to sandwich construction etc. for forming of these semiconductors or for silicon-on-insulator (SOI),
Silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulator are laminated on insulator
Upper SiGe (SiGeOI) and germanium on insulator (GeOI) etc..Can in Semiconductor substrate
With formed with device, such as NMOS and/or PMOS etc..Equally, in Semiconductor substrate also
Conductive member is could be formed with, conductive member can be the grid, source electrode or drain electrode of transistor,
It can also be metal interconnection structure electrically connected with transistor, etc..
Further, floating gate oxide layers, spacer material layer 604, separation layer 606 can be adopted
With material commonly used in the art, such as silica, floating boom 601 and can be with control gate 603
Using common used materials such as polysilicons.And gate dielectric layer 602 is then preferably by ONO
Structure, i.e. oxide, nitride, oxide structure, so both there is well interface characteristics
Can, it may have higher dielectric constant.
The semiconductor devices of the present embodiment, due between stacking gate structure there is height to be tied with stacking
The consistent space of structure, thus the dielectric coefficient between stacking gate diminishes so that imitated by Capacitance Coupled
Wordline interference reduces caused by answering, so as to improve cycle period/read-write of flash memory time
Number.
Example IV
Yet another embodiment of the present invention provides a kind of electronic installation, including semiconductor devices and
The electronic building brick being connected with the semiconductor devices.Wherein, the semiconductor devices includes：Partly lead
Body substrate, formed with multiple stacking gate structures, each stacking gate in the Semiconductor substrate
Structure includes floating gate oxide layers, floating boom, gate dielectric layer and the control sequentially formed from bottom to top
Grid, clearance wall, control described in the clearance wall exposed portion are formed in the side wall of the stacking gate
Grid, the part control gate exposed form silicide, and the multiple stacking gate knot of covering
The separation layer of structure, the separation layer to form height and the heap between the stacking gate structure
The consistent space of stacked gate structure.
Wherein Semiconductor substrate can be at least one of following material being previously mentioned：Si、Ge、
SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors,
Also include sandwich construction that these semiconductors are formed etc. or be silicon-on-insulator (SOI), insulate
Silicon (SSOI) is laminated on body, SiGe (S-SiGeOI), germanium on insulator are laminated on insulator
SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Can be with shape in Semiconductor substrate
Into having device, such as NMOS and/or PMOS etc..Equally, can be with Semiconductor substrate
Formed with conductive member, conductive member can be the grid, source electrode or drain electrode of transistor, also may be used
To be metal interconnection structure for being electrically connected with transistor, etc..In addition, in the semiconductor substrate
Can also formed with isolation structure, the isolation structure be shallow trench isolate (STI) structure or
Person's selective oxidation silicon (LOCOS) isolation structure is as example.In the present embodiment, partly lead
The constituent material of body substrate selects monocrystalline silicon.
Further, floating gate oxide layers, spacer material layer, separation layer can use this area
Conventional material, such as silica, floating boom and can use polysilicon etc. with control gate
Common used material.And gate dielectric layer is then preferably by ONO structure, i.e. oxide, nitrogen
Compound, oxide structure, so both there is good interface performance, it may have higher dielectric
Constant.
Wherein, the electronic building brick, can be any electronic building bricks such as discrete device, integrated circuit.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, on
Net sheet, game machine, television set, VCD, DVD, navigator, camera, video camera,
Any electronic product such as recording pen, MP3, MP4, PSP or equipment, or it is any including
The intermediate products of the semiconductor devices.
Wherein, Fig. 7 shows the example of mobile phone.The outside of mobile phone 700, which is provided with, is included in shell
Display portion 702, operation button 703 in 701, external connection port 704, loudspeaker
705th, microphone 706 etc..
The electronic installation of the embodiment of the present invention, by the stacking gate knot of semiconductor devices included
There is the height space consistent with stacked structure, thus the dielectric coefficient between stacking gate between structure
Diminish so that wordline interference reduces as caused by capacitance coupling effect, so as to improve flash memory
The cycle period of reservoir/read-write number.Therefore the electronic installation equally has the advantages of similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modifications can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of preparation method of semiconductor devices, it is characterised in that comprise the steps：
Semiconductor substrate is provided, forms multiple stacking gate structures on the semiconductor substrate, often
The individual stacking gate structure include sequentially form from bottom to top floating gate oxide layers, floating boom, grid
Dielectric layer and control gate, on the stacking gate structure going back remnants has hardmask material；
Form the clearance wall for covering the Semiconductor substrate, stacking gate structure and hardmask material
Material layer；
Remaining hardmask material and portion gap the wall material bed of material is removed with exposed division
Divide control gate；
The part control gate exposed is set to be changed into silicide；
The separation layer for covering the multiple stacking gate structure is formed, the separation layer causes the heap
The height space consistent with the stacking gate structure is formed between stacked gate structure.
2. the preparation method of semiconductor devices according to claim 1, it is characterised in that
Remaining hardmask material and the portion gap wall material bed of material of removing is with exposed division sub-control
The step of grid processed, includes：
Form the cushion for surrounding the remaining hardmask material；
The sacrifice separation layer in gap between the multiple stacking gate structure, the sacrifice are filled in formation
Separation layer has space；
Remove the remaining hardmask material, cushion and partial sacrifice separation layer and portion
The subdivided gap wall material bed of material is with exposed portion control gate.
3. the preparation method of semiconductor devices according to claim 2, it is characterised in that
Remaining hardmask material and the portion gap wall material bed of material of removing is with exposed division sub-control
The step of grid processed, also includes：
Remove the remaining sacrifice separation layer and the stacking gate structural top sidewall residue
Spacer material layer.
4. the preparation method of semiconductor devices according to claim 1, it is characterised in that
Remaining hardmask material and the portion gap wall material bed of material of removing is with exposed division sub-control
The step of grid processed, includes：
Etching stopping layer is formed on the spacer material layer；
The sacrifice separation layer in gap between the multiple stacking gate structure is filled in formation；
Remove the remaining hardmask material, and partial sacrifice separation layer and portion gap
The wall material bed of material is with exposed portion control gate；
Remove the remaining sacrifice separation layer；
Remove the remaining etching stopping layer.
5. the preparation method of semiconductor devices according to claim 4, it is characterised in that
Removing the remaining hardmask material, and partial sacrifice separation layer and portion gap wall
Material layer is also to include before the step of the control gate of exposed portion：
Form the first dielectric layer.
6. according to semiconductor devices of the claim as described in claim 1-5 any one
Preparation method, it is characterised in that
The space is in mushroom.
7. the preparation method of the semiconductor devices according to claim 1-5 any one,
The semiconductor devices is NAND quick-flash memory.
A kind of 8. semiconductor devices, it is characterised in that including：Semiconductor substrate, described half
Formed with multiple stacking gate structures on conductor substrate, each stacking gate structure include from lower and
On the floating gate oxide layers, floating boom, gate dielectric layer and the control gate that sequentially form, the stacking gate
Side wall on formed with clearance wall, control gate described in the clearance wall exposed portion is described to expose
Part control gate be formed as silicide, and the isolation of the multiple stacking gate structure of covering
Layer, the separation layer to form height and the stacking gate structure between the stacking gate structure
Consistent space.
9. semiconductor devices as claimed in claim 8, it is characterised in that the space is in
Mushroom.
A kind of 10. electronic installation, it is characterised in that including a kind of semiconductor devices and with institute
The electronic building brick that semiconductor devices is connected is stated, the semiconductor devices includes：Semiconductor substrate,
Include in the Semiconductor substrate formed with multiple stacking gate structures, each stacking gate structure
Floating gate oxide layers, floating boom, gate dielectric layer and the control gate sequentially formed from bottom to top, it is described
Formed with clearance wall in the side wall of stacking gate, control gate described in the clearance wall exposed portion, institute
State the part control gate exposed and be formed as silicide, and cover the multiple stacking gate structure
Separation layer, the separation layer to form height and the stacking gate between the stacking gate structure
The consistent space of structure.
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| CN108511454A (en) * | 2018-03-30 | 2018-09-07 | 长江存储科技有限责任公司 | A kind of 3D nand memories and preparation method thereof |
| CN109994484A (en) * | 2017-12-28 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | Nand memory and forming method thereof |
| CN110061007A (en) * | 2018-01-18 | 2019-07-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111653571A (en) * | 2020-07-23 | 2020-09-11 | 上海华力微电子有限公司 | Method for forming semiconductor structure |
| CN112086398A (en) * | 2019-06-14 | 2020-12-15 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and forming method |
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| CN109994484A (en) * | 2017-12-28 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | Nand memory and forming method thereof |
| CN110061007A (en) * | 2018-01-18 | 2019-07-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110061007B (en) * | 2018-01-18 | 2021-06-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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