CN1763931A - Quickflashing memory unit and its manufacturing method - Google Patents
Quickflashing memory unit and its manufacturing method Download PDFInfo
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- CN1763931A CN1763931A CN 200410085790 CN200410085790A CN1763931A CN 1763931 A CN1763931 A CN 1763931A CN 200410085790 CN200410085790 CN 200410085790 CN 200410085790 A CN200410085790 A CN 200410085790A CN 1763931 A CN1763931 A CN 1763931A
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- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 99
- 239000002184 metal Substances 0.000 claims abstract description 99
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 98
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000010410 layer Substances 0.000 claims description 200
- 238000000034 method Methods 0.000 claims description 63
- 239000011229 interlayer Substances 0.000 claims description 43
- 238000005516 engineering process Methods 0.000 claims description 42
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000007667 floating Methods 0.000 claims description 12
- 230000005641 tunneling Effects 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims 5
- 210000004027 cell Anatomy 0.000 description 45
- 239000004020 conductor Substances 0.000 description 14
- 230000008569 process Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical group F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
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- 238000001459 lithography Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000000547 structure data Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- Non-Volatile Memory (AREA)
Abstract
The quick flash storage unit comprises mainly: a first conductive substrate with formed second conductive shallow-well zone, a grid stack structure, a first conductive source/drain zone, a metal silicide layer arranged on the drain zone, a dielectric layer between layers, and a contact plug in dielectric layer connected to metal silicide layer to reduce the resistance value between plug and drain zone and shallow-well zone. This invention can increase the read-write speed.
Description
Technical field
The present invention relates to a kind of memory component and manufacture method thereof, particularly relate to structure and the manufacture method thereof of a kind of flash memory cell (Flash memory cell).
Background technology
Non-volatility memorizer (Nonvolatile memory) is applied in the use of various electronic components at present more, as memory structure data, routine data and other can repeated access data.And but wherein a kind of non-volatility memorizer of repeated access data is called flash memory.Flash memory is a kind of can erasing and programmable read only memory (Electrically Erasable Programmable Read Only Memory by electricity, EEPROM), it has the advantage that the actions such as depositing in, read, erase that can carry out repeatedly data and the data that deposit in also can not disappear after outage, thus become personal computer and electronic equipment a kind of memory component of extensively adopting.
Fig. 1 illustrates the generalized section for existing a kind of flash memory cell (for example being United States Patent (USP) the 6th, 418, No. 060 disclosed flash memory cell).Please refer to Fig. 1, flash memory cell 70 mainly comprises deep-well district 42, shallow well district 46, stack structure 40, source area 48, drain region 44, lead (bit line) 72 and contact hole 60a.Wherein, lead 72 via contact plunger 60a with drain region 44 and shallow well district 46 electric property couplings, in other words, contact plunger 60a runs through drain region 44 and shallow well district 46, therefore when forming contact plunger 60a, need etching interlayer dielectric layer (not indicating) and deep-well district 42, run through the contact plunger opening in interlayer dielectric layer, drain region 44 and shallow well district 46 with formation.But because the depth-to-width ratio of this contact plunger opening is very big, and needs two kinds of different materials of etching, so the difficult control of the degree of depth of contact plunger opening, so the difficulty in process degree is higher.And, in last part technology, because must separating, the contact plunger of the contact plunger of memory cell areas and periphery circuit region forms, so also can increase the complexity of last part technology.
In addition, (contact hole 60a is rectilinear the contact with drain region 44 because contact plunger 60a is not good with contacting of drain region 44 and shallow well district 46, both contacts area are little), therefore when this memory cell of operation (particularly when memory cell is carried out read operation), can cause the drain region 44 and the resistance value in shallow well district 46 to become big or unstable, cause element operation speed slack-off, and then influence element efficiency.
Summary of the invention
Therefore, purpose of the present invention just provides a kind of manufacture method of flash memory cell, can reduce the resistance of its drain region, and improves the reading speed of flash memory cell.
Another object of the present invention provides a kind of flash memory cell, can have preferred reading speed.
The present invention proposes a kind of manufacture method of flash memory cell, and the method forms the second conductivity type shallow well district earlier in the first conductivity type substrate, then forms the stack structure in the first conductivity type substrate.Wherein, this stack structure is risen in regular turn by the first conductivity type substrate and is made of dielectric layer between tunneling dielectric layer, floating grid, grid and control grid, and this stack structure is positioned in the second conductivity type shallow well district.Then, form the first conductivity type source electrode and the drain electrode of second conductivity type in the second conductivity type shallow well district in the first conductivity type substrate of grid structure both sides.Afterwards, in the first conductivity type drain region, form metal silicide layer again, and metal silicide layer runs through the knot in the first conductivity type drain region and the second conductivity type shallow well district.Then on the first conductivity type substrate and stack structure, form interlayer dielectric layer.Afterwards, in interlayer dielectric layer, form contact plunger, and this contact plunger is electrically connected with the first conductivity type drain region and the second conductivity type shallow well district via metal silicide layer.
In the manufacture method of above-mentioned flash memory cell, after forming interlayer dielectric layer with the formation contact plunger before, for example be to comprise with interlayer dielectric layer carrying out ion implantation technology, in the first conductivity type drain region and the second conductivity type shallow well district below it, to form doped region as mask.Wherein, the first conductivity type drain region for example be by this doped region and with the second electrical short circuit in conductivity type shallow well district.
The present invention proposes a kind of manufacture method of flash memory cell, and the method forms the second conductivity type shallow well district earlier in the first conductivity type substrate, then forms the stack structure in the first conductivity type substrate.Wherein, this stack structure is risen in regular turn by the first conductivity type substrate and is made of dielectric layer between tunneling dielectric layer, floating grid, grid and control grid, and this stack structure is positioned in the second conductivity type shallow well district.Then, form the first conductivity type source electrode and the drain electrode of second conductivity type in the second conductivity type shallow well district in the first conductivity type substrate of grid structure both sides.Then, in the first conductivity type drain region, form metal silicide layer.Afterwards, the first conductivity type drain region and below the second conductivity type shallow well district in form doped region, and the first conductivity type drain region promptly be by this doped region with the second electrical short circuit in conductivity type shallow well district.Then, on the first conductivity type substrate and stack structure, form interlayer dielectric layer, in interlayer dielectric layer, form contact plunger again and be electrically connected with metal silicide layer.And contact plunger is by metal silicide layer and doped region and be electrically connected to the first conductivity type drain region and the second conductivity type shallow well district.
The present invention proposes a kind of manufacture method of flash memory cell, and the method forms the second conductivity type shallow well district earlier in the first conductivity type substrate, then forms the stack structure in the first conductivity type substrate.Wherein, this stack structure is risen in regular turn by the first conductivity type substrate and is made of dielectric layer between tunneling dielectric layer, floating grid, grid and control grid, and this stack structure is positioned in the second conductivity type shallow well district.Then, form the first conductivity type source electrode and the drain electrode of second conductivity type in the second conductivity type shallow well district in the first conductivity type substrate of grid structure both sides.Then, the first conductivity type drain region and below the second conductivity type shallow well district in form doped region, and the first conductivity type drain region promptly be by this doped region with the second electrical short circuit in conductivity type shallow well district.Afterwards, in the first conductivity type drain region, form metal silicide layer.Then, on the first conductivity type substrate and stack structure, form interlayer dielectric layer, in interlayer dielectric layer, form contact plunger again and be electrically connected with metal silicide layer.And contact plunger is by metal silicide layer and doped region and be electrically connected to the first conductivity type drain region and the second conductivity type shallow well district.
The manufacture method of flash memory cell of the present invention forms metal silicide layer in the first conductivity type drain region, and utilize metal silicide layer or below metal silicide layer, form doped region in addition, so that the first conductivity type drain region and the second electrical short circuit in conductivity type shallow well district, and contact plunger can and be electrically connected with the first conductivity type drain region and the second conductivity type shallow well district through metal silicide layer.So the present invention can solve in the existing technology because of contact plunger mouth depth-to-width ratio is too big, and the problem that causes the difficulty in process degree to improve.
The present invention also proposes a kind of flash memory cell, mainly comprises the first conductivity type substrate, stack structure, the first conductivity type source electrode, the first conductivity type drain electrode, metal silicide layer, interlayer dielectric layer and contact plunger.Wherein, be formed with the second conductivity type shallow well district in the first conductivity type substrate.The stack structural arrangements is in the first conductivity type substrate, and it is risen in regular turn by dielectric layer between tunneling dielectric layer, floating grid, grid and control grid by the first conductivity type substrate and is constituted.The drain electrode of the first conductivity type source electrode and first conductivity type then is configured in respectively in the second conductivity type shallow well district in the first conductivity type substrate of stack structure both sides.Metal silicide layer is configured in the first conductivity type drain region, and interlayer dielectric layer is configured on the first conductivity type substrate and the stack structure.Contact plunger then is formed in the interlayer dielectric layer, and is electrically connected with the first conductivity type drain region and the second conductivity type shallow well district via metal silicide layer.
In flash memory cell of the present invention, the first conductivity type drain region by metal silicide layer or doped region and with the second electrical short circuit in conductivity type shallow well district, contact plunger then is electrically connected with metal silicide.Because metal silicide layer can reduce the resistance value between contact plunger and the first conductivity type drain region and the second conductivity type shallow well district, therefore can promote reading rate, and then improve element efficiency.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Fig. 1 illustrates and is United States Patent (USP) the 6th, 418, No. 060 memory cell structure schematic diagram.
Fig. 2 A to Fig. 2 E illustrates the manufacturing process profile into a kind of flash memory cell of one embodiment of the present invention.
Fig. 3 A to Fig. 3 B promptly illustrates the part manufacturing process profile into a kind of flash memory cell of another preferred embodiment of the present invention.
Fig. 4 A to Fig. 4 B illustrates the part manufacturing process generalized section into a kind of flash memory cell of another embodiment of the present invention.
The simple symbol explanation
40,112: the stack structure
42: the deep-well district
44: the drain region
46: the shallow well district
48: source area
60a, 132: contact plunger
70,150,160: flash memory cell
72,134: lead
The substrate of 100:n type
102:p type shallow well district
104,108: dielectric layer
104a: tunneling dielectric layer
106,110: conductor layer
106a: floating grid
108a: dielectric layer between grid
110a: control grid
114a:n type source area
114b:n type drain region
116: clearance wall
124,142: opening
120,120a: metal silicide layer
122: the photoresist layer
126: doped region
128: interlayer dielectric layer
130: ion
140: mask layer
Embodiment
Flash memory cell of the present invention has preferred reading speed and preferred consistency, and the present invention can utilize multiple different technology to make this flash memory cell, below will the technology that these are different be described, and be that example is done explanation with two NOR gate formulas (BiNOR) type array flash memory for a plurality of embodiment.Yet following embodiment is in order to explanation the present invention, but not in order to limit the present invention.Therefore those skilled in the art can be according to the disclosed technology of the present invention according to actual required the variation, and it also belongs to curtain in the scope of the present invention.It should be noted that following examples are is the n type with first conductivity type, second conductivity type illustrates for the p type, but those skilled in the art should know that if first conductivity type is replaced as the p type, second conductivity type is replaced as the n type, and then following embodiment still can implement according to this.
First embodiment
Fig. 2 A to Fig. 2 E illustrates the manufacturing process profile into a kind of flash memory cell of one embodiment of the present invention.
Please refer to Fig. 2 A, at first in n type substrate 100, form p type shallow well district 102, then in n type substrate 100, form dielectric layer 104, conductor layer 106, dielectric layer 108 and conductor layer 110 in regular turn.Wherein, the material of dielectric layer 104 for example is a silica, and its formation method for example is a thermal oxidation method.The material of dielectric layer 108 for example is a silicon oxide/silicon nitride/silicon oxide etc., or is made of institutes such as silicon oxide layer or silicon oxide/nitride layer, and its formation method for example be low-pressure chemical vapor deposition (Low PressureCVD, LPCVD).And the material of conductor layer 106 and conductor layer 110 for example is the polysilicon that is mixed with impurity, and its formation method for example is to form unadulterated polysilicon with chemical vapour deposition technique earlier, and then for example to be ion implantation and admixture is mixed in the unadulterated polysilicon.Certainly, conductor layer 106 also can be in the mode of (In-Situ) dopant ion of coming personally with the formation method of conductor layer 110, utilizes chemical vapour deposition technique to form it.
In addition, those skilled in the art can know that the present invention can also form one deck cap layer (not illustrating) on conductor layer 110, can be not impaired in subsequent technique (for example being etch process etc.) with protection conductor layer 110.
Please refer to Fig. 2 B, for example to be photoetching/etched mode pattern dielectric layer 104, conductor layer 106, dielectric layer 108 and conductor layer 110, in n type substrate 100, to form a plurality of stack structures 112.Wherein, each stack structure 112 is made of dielectric layer 108a between tunneling dielectric layer 104a, floating grid 106a, grid and control grid 110a in regular turn 100 of n type substrates.Then, form n type source area 114a and n type drain region 114b in the p type shallow well district 102 in the n type substrate 100 of stack structure 112 both sides.Wherein, the formation method of n type source area 114a and n type drain region 114b for example is with the ion injection p type shallow well district 102 of ion implantation with n type admixture.In a preferred embodiment, then can on the sidewall of stack structure 112, form clearance wall 116.The material of clearance wall 116 for example is an insulating material, and its formation method for example is to form the conformal insulating barrier of one deck (not illustrating) earlier in n type substrate 100, more conformal insulating barrier is carried out anisotropic etch process afterwards, to form clearance wall 116.It should be noted that, in another embodiment of the present invention, can also have less distance (that is the width of n type source area 114a is less) between the two stack structures 112, make stack structure 112 link to each other and cover n type source area 114a at the clearance wall 116 of n type source area 114a side.
Please refer to Fig. 2 C, form metal silicide layer 120 in the n type substrate 100 above the n type drain region 114b, its material for example is nickle silicide, tungsten silicide, cobalt silicide, titanium silicide, platinum silicide or palladium silicide.And the formation method of metal silicide layer 120 for example is to aim at metal silicide technology voluntarily, its step for example be prior to n type substrate 100 with stack structure 112 on physical vaporous deposition (Physical Vapor Deposition, PVD) or sputtering method (Sputtering) form layer of metal layer (as: nickel, tungsten, cobalt, titanium, platinum, palladium etc.) (not illustrating), then carry out thermal process so that the pasc reaction in metal level and the n type substrate 100, and form metal silicide.Remove then and have neither part nor lot in silicification reaction or react incomplete metal, the metal silicide layer 120 that only stays.In a preferred embodiment, silicon among the control grid 110a of stack structure 112 and the n type source area 114a is in this thermal process, also can produce reaction and form metal silicide with above-mentioned metal level, thereby formation metal silicide layer 120 on control grid 110a and in the n type source area 114a, shown in Fig. 2 C.
Certainly, if the distance less (that is the width of n type source area 114a is less) between the adjacent two stack structures 112 of shared same n type source area 114a, make stack structure 112 link to each other and cover n type source area 114a at the clearance wall 116 of n type source area 114a side, then in the above-mentioned silicide process of aligning voluntarily, can not form metal silicide layer 120 on the n type source area 114a.In addition, it should be noted that, in the above description, only aim at metal silicide technology voluntarily, but in fact this high-k metal gate devices technology (CMOS) of aiming at metal silicide technology and peripheral circuit voluntarily combines in memory cell areas.
Please refer to Fig. 2 D, form the photoresist layer 122 with opening 124 on n type substrate 100 and stack structure 112, its formation method for example is a lithography/etch process.Be mask with photoresist layer 122 more then, carry out ion implantation technology, among the n type drain region 114b and p type shallow well district 102 with the below of ion 130 being injected the metal silicide layer 120 that openings 124 are exposed, run through the doped region 126 of the knot in n type drain region 114b and p type shallow well district 102 with formation.Wherein, ion 130 for example is boron difluoride (BF
2) ion.
Please refer to Fig. 2 E, remove photoresist layer 122, on n type substrate 100 and stack structure 112, form interlayer dielectric layer 128 afterwards again.The material of interlayer dielectric layer 128 for example is boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG), and the formation method of interlayer dielectric layer 128 for example is a chemical vapour deposition technique.Carry out flatening process (for example etch-back method, chemical mechanical milling method (ChemicalMechanical Polishing)) then, make the flattening surface of interlayer dielectric layer 128.Then, form the contact plunger 132 that is electrically connected with metal silicide layer 120 in interlayer dielectric layer 128, its material for example is the tungsten metal.The formation method of contact plunger 132 for example is prior to forming the opening (not illustrating) that exposes the metal silicide layer 120 within the n type drain region 114b in the interlayer dielectric layer 128, inserting conductor material then to form it in opening.
Afterwards, on interlayer dielectric layer 128, form the lead 134 that is electrically connected with contact plunger 132.Promptly finish the technology of the flash memory cell 150 that Fig. 2 E illustrated this moment.The formation method of lead 134 for example is after forming conductor layer (not illustrating) on the interlayer dielectric layer 128, carries out photoetching and etching step again and forms the lead 134 of strip.The follow-up technology of finishing flash memory is known by existing skill person, does not repeat them here.
The present invention forms metal silicide layer 120 in n type drain region 114b, and forms doped region 126 in metal silicide layer 120 belows, and runs through the knot in n type drain region 114b and p type shallow well district 102, so that n type drain region 114b and the 102 electrical short circuits of p type shallow well district.Form contact plunger 132 afterwards again to be electrically connected to metal silicide layer 120, in the technology of avoiding existing contact plunger, because of the too big difficulty that suffers from of contact plunger opening depth-to-width ratio.Therefore, the present invention can reduce the degree of difficulty of technology.
It should be noted that especially, in another embodiment of the present invention, can also before the ion implantation technology of carrying out Fig. 2 D, form interlayer dielectric layer 128 (shown in Fig. 2 E) earlier, be that mask carries out ion implantation technology with interlayer dielectric layer 128 then, to form doped region 126 (shown in Fig. 2 D).Afterwards again in inserting conductor material in the opening shown in Fig. 2 D 124 to form contact plunger 132 (shown in Fig. 2 E).That is to say that the present invention can directly utilize interlayer dielectric layer 128 as mask, and needn't form the mask of photoresist layer as ion implantation technology in the technology that forms doped region 126.Can save one photomask thus, and then reduce the technology cost.
Below will describe the flash memory cell 150 that forms according to above-mentioned technology in detail.Please refer to Fig. 2 E, flash memory cell 150 mainly comprises n type substrate 100, stack structure 112, n type source area 114a, n type drain region 114b, metal silicide layer 120, interlayer dielectric layer 128 and lead 134.Wherein, be formed with p type shallow well district 102 in the n type substrate 100.Stack structure 112 is configured in the n type substrate 100, and it is made of dielectric layer 108a between tunneling dielectric layer 104a, floating grid 106a, grid and control grid 110a in regular turn 100 of n type substrates.N type source area 114a and n type drain region 114b then are configured in respectively in the p type shallow well district 102 in the n type substrate 100 of stack structure 112 both sides.Metal silicide layer 120 is configured in the n type drain region 114b, and interlayer dielectric layer 128 is configured on n type substrate 100 and the stack structure 112.132 of contact plungers are formed in the interlayer dielectric layer 128, and are electrically connected with metal silicide layer 120 in the n type drain region 114b.In addition, also dispose lead 134 on the interlayer dielectric layer 128, it is electrically connected with n type drain region 114b by contact plunger 132, with the bit line (bit line) as flash memory cell 150.
Specifically, flash memory cell 150 also includes a doped region 126, be formed in the p type shallow well district 102 of n type drain region 114b and below thereof so that n type drain region 114b by doped region 126 with the 102 electrical short circuits of p type shallow well district.In addition, also can dispose metal silicide layer 120 on the stack structure 112, to reduce the resistance of control grid 110a.
Dispose metal silicide layer 120 in the n type drain region 114b of flash memory cell 150, therefore can reduce the resistance of n type drain region 114b, and improve the consistency of element resistance.In addition, because contact plunger 132 is electrically connected with n type drain region 114b and p type shallow well district 102 by metal silicide layer 120, therefore can reduce the resistance between contact plunger 132 and n type drain region 114b and the p type shallow well district 102, and then the reading speed of raising flash memory cell 150, to improve the usefulness of element.
Second embodiment
The present invention can also form doped region earlier in n type drain region and p type shallow well district, and then forms metal silicide layer in n type drain region, to reduce energy needed in the technology that forms doped region.Fig. 3 A to Fig. 3 B promptly illustrates the part manufacturing process profile into a kind of flash memory cell of another preferred embodiment of the present invention.And the identical person with first embodiment of the element in the present embodiment promptly shows it with identical label, and its formation method and material etc. please refer to the explanation of first embodiment, below repeat no more.
Please refer to Fig. 3 A, according to the explanation of Fig. 2 A to Fig. 2 B of the foregoing description and after finishing the structure shown in Fig. 2 B, then on n type substrate 100 and stack structure 112, form photoresist layer 122 with opening 124, be mask with photoresist layer 122 more then, carry out ion implantation technology, among the n type drain region 114b and p type shallow well district 102 with the below of ion 130 being injected the metal silicide layer 120 that openings 124 are exposed, to form doped region 126.
Please refer to Fig. 3 B, remove photoresist layer 122, then in n type drain region 114b, form metal silicide layer 120.In a preferred embodiment, this step also can be simultaneously in n type source area 114a with stack structure 112 on form metal silicide layer 120.And then then carry out the described technology of Fig. 2 E among first embodiment, to form the flash memory cell 150 that Fig. 2 E is illustrated.
In addition, the present invention can also be directly with metal silicide layer as the media that electrically conducts between n type drain region 114b and the p type shallow well district 102.Below will it be described for the 3rd embodiment.
The 3rd embodiment
Fig. 4 A to Fig. 4 B illustrates the part manufacturing process generalized section into a kind of flash memory cell of another embodiment of the present invention.Please refer to Fig. 4 A, after finishing the structure shown in Fig. 2 B, then in n type substrate 100, form mask layer 140 with opening 142 according to the described technology of Fig. 2 A to Fig. 2 B of first embodiment.Wherein, opening 142 exposes n type drain region 114b.And then form metal silicide layer 120a as mask and in n type drain region 114b with mask layer 140.Specifically, metal silicide layer 120 runs through the knot in n type drain region 114b and p type shallow well district 102.At this moment, n type drain region 114b promptly be by metal silicide layer 120 with the 102 electrical short circuits of p type shallow well district.
In a preferred embodiment, the formation method of metal silicide layer 120a for example is to be that hard mask (hard mask) carries out etch process with mask layer 140 earlier, to form the knot that opening (not illustrating) runs through n type drain region 114b and p type shallow well district 102 in n type substrate 100.Again the metal material described in first embodiment is inserted in the opening afterwards, and carried out thermal process and make the silicon in itself and n type drain region 114b and the p type shallow well district 102 produce reaction and form metal silicide layer 120a.In addition, the method that forms metal silicide layer 120a can also be to be that mask carries out ion implantation technology with mask layer 140, metal ion is injected n type substrate 100, make the silicon in itself and n type drain region 114b and the p type shallow well district 102 produce reaction and form metal silicide layer 120a.Yet the present invention is not defined as above-mentioned two kinds of technologies with the formation method of metal silicide layer 120a.Those skilled in the art can decide the technology of metal silicide layer 120a according to spirit of the present invention and actual process.
Please refer to Fig. 4 B, after forming metal silicide layer 120a, remove mask layer 140 again, and proceed the described technology of Fig. 2 E of first embodiment, to form the flash memory cell 160 that Fig. 4 B is illustrated.
It should be noted that especially; in another embodiment of the present invention; if the distance less (that is the width of n type source area 114a is less) between the adjacent two stack structures 112 of shared same n type source area 114a; make stack structure 112 link to each other and cover n type source area 114a at the clearance wall 116 of n type source area 114a side; and because the technology of general memory element all can form cap layer (not illustrating) with protection control grid 110a on control grid 110a; so can be that mask is aimed at silicide process voluntarily with clearance wall 116 directly this moment, and needn't form mask layer 140 again.Therefore can save and form mask layer 140 and remove mask layer 140 these twice technologies.
The present invention forms metal silicide layer 120 in n type drain region 114b, and runs through the knot in n type drain region 114b and p type shallow well district 102, so that n type drain region 114b and the 102 electrical short circuits of p type shallow well district.Form contact plunger 132 afterwards again to be electrically connected to metal silicide layer 120, so that contact plunger 132 can be electrically connected with n type drain region 114b and p type shallow well district 102 by metal silicide layer 120.Therefore can avoid in the technology of existing contact plunger, because of the too big difficulty that suffers from of contact plunger opening depth-to-width ratio.Therefore, the present invention can reduce the degree of difficulty of technology.
The different place of the flash memory cell 150 that the flash memory cell 160 that forms according to above-mentioned technology and Fig. 2 E are illustrated only is the medium that is electrically connected between n type drain region 114b and the p type shallow well district 102.In more detail, in flash memory cell 150, n type drain region 114b by doped region 126 (seeing Fig. 2 E) with the 102 electrical short circuits of p type shallow well district, and in flash memory cell 160, n type drain region 114b then by metal silicide layer 120a (seeing Fig. 4 B) with the 102 electrical short circuits of p type shallow well district.Other element is all same or similar with the element that Fig. 1 E is illustrated, and therefore repeats no more herein.
In sum, the present invention has following advantage:
1. the present invention directly utilizes metal silicide layer or form doped region again under metal silicide layer, so that n type drain region and the electrical short circuit in p type shallow well district, make contact plunger be electrically connected to metal silicide layer again, directly run through in the technology of knot in n type drain region and p type shallow well district, to avoid existing because of the too big difficulty that suffers from of contact plunger opening depth-to-width ratio with contact plunger.Therefore, the present invention can reduce the degree of difficulty of technology.And, in last part technology, because the contact plunger of the contact plunger of memory cell areas and periphery circuit region can form simultaneously, so also can simplify last part technology.
2. the present invention is formed with metal silicide layer in n type drain region, therefore can reduce the resistance of n type drain region, and improves the consistency of element resistance.
3. contact plunger of the present invention is electrically connected with n type drain region and p type shallow well district by metal silicide layer, therefore can reduce the resistance between contact plunger and n type drain region and the p type shallow well district, and then the reading speed of raising memory cell, to improve the usefulness of element.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (23)
1, a kind of manufacture method of flash memory cell comprises:
In one first conductivity type substrate, form one second conductivity type shallow well district;
In this first conductivity type substrate, form a stack structure, and this stack structure is risen by this first conductivity type substrate and comprises a dielectric layer and a control grid between a tunneling dielectric layer, a floating grid, grid in regular turn, and this stack structure is positioned in this second conductivity type shallow well district;
Form one first conductive type source region and one first conductivity type drain region respectively in this second conductivity type shallow well district in this first conductivity type substrate of these stack structure two sides;
In this first conductivity type drain region, form a metal silicide layer, and this metal silicide layer runs through the knot in this first conductivity type drain region and this second conductivity type shallow well district;
On this first conductivity type substrate and this stack structure, form an interlayer dielectric layer; And
In this interlayer dielectric layer, form a contact plunger, and this contact plunger is electrically connected with this first conductivity type drain region and this second conductivity type shallow well district by this metal silicide layer.
2, the manufacture method of flash memory cell as claimed in claim 1, wherein after forming this first conductive type source region and this first conductivity type drain region with form this interlayer dielectric layer before, the sidewall that also is included in this stack structure forms a clearance wall.
3, the manufacture method of flash memory cell as claimed in claim 1 also is included in and forms this metal silicide layer on this control grid of this stack structure.
4, the manufacture method of flash memory cell as claimed in claim 1, wherein this first conductivity type is a n type conductivity type, and this second conductivity type is a p type conductivity type.
5, a kind of manufacture method of flash memory cell comprises:
In one first conductivity type substrate, form one second conductivity type shallow well district;
In this first conductivity type substrate, form a stack structure, and this stack structure is risen by this first conductivity type substrate and comprises a dielectric layer and a control grid between a tunneling dielectric layer, a floating grid, grid in regular turn, and this stack structure is positioned in this second conductivity type shallow well district;
Form one first conductive type source region and one first conductivity type drain region respectively in this second conductivity type shallow well district in this first conductivity type substrate of these stack structure two sides;
In this first conductivity type drain region, form a metal silicide layer;
Form a doped region in this metal silicide layer below, and this doped region is electrically connected with this metal silicide layer, and runs through the knot in this first conductivity type drain region and this second conductivity type shallow well district;
Form an interlayer dielectric layer on this first conductivity type substrate and this stack structure, this interlayer dielectric layer has an opening, and this opening corresponds to this first conductivity type drain region; And
In this opening of this interlayer dielectric layer, form a contact plunger, and this contact plunger is electrically connected with this first conductivity type drain region and this second conductivity type shallow well district by this metal silicide layer and this doped region.
6, the manufacture method of flash memory cell as claimed in claim 5, wherein after forming this metal silicide layer with this interlayer dielectric layer of formation before, also comprise:
In this gate stack structure and this first conductivity type substrate, form a patterning photoresist layer, to expose this metal silicide layer;
With this patterning photoresist layer is that mask forms this doped region; And
Remove this patterning photoresist layer.
7, the manufacture method of flash memory cell as claimed in claim 5, the method that wherein forms this doped region comprises ion implantation technology.
8, the manufacture method of flash memory cell as claimed in claim 5 also is included in and forms this metal silicide layer on this control grid of this stack structure.
9, the manufacture method of flash memory cell as claimed in claim 5, wherein this first conductivity type is a n type conductivity type, and this second conductivity type is a p type conductivity type.
10, a kind of manufacture method of flash memory cell comprises:
In one first conductivity type substrate, form one second conductivity type shallow well district;
In this first conductivity type substrate, form a stack structure, and this stack structure is risen in regular turn by this first conductivity type substrate and is made of a dielectric layer between a tunneling dielectric layer, a floating grid, grid and a control grid, and this stack structure is positioned in this second conductivity type shallow well district;
Form one first conductive type source region and one first conductivity type drain region respectively in this second conductivity type shallow well district in this first conductivity type substrate of these stack structure two sides;
In this first conductivity type drain region, form a doped region, and this doped region runs through the knot in this first conductivity type drain region and this second conductivity type shallow well district;
In this first conductivity type drain region, form a metal silicide layer, and this metal silicide is electrically connected with this doped region;
Form an interlayer dielectric layer on this first conductivity type substrate and this stack structure, this interlayer dielectric layer has an opening, and this opening corresponds to this first conductivity type drain region; And
In this opening of this interlayer dielectric layer, form a contact plunger, be electrically connected to this metal silicide layer.
11, the manufacture method of flash memory cell as claimed in claim 10, wherein after forming this first conductive type source region and this first conductivity type drain region and before forming this metal silicide layer, the sidewall that also is included in this stack structure forms a clearance wall, and this metal silicide layer is arranged in the first conductivity type drain region of the part that this clearance wall exposes.
12, the manufacture method of flash memory cell as claimed in claim 10 also is included in and forms this metal silicide layer on this control grid of this stack structure.
13, the manufacture method of flash memory cell as claimed in claim 10 wherein comprises in the step that forms this doped region:
On this first conductivity type substrate and this stack structure, form a patterning photoresist layer, to expose this first conductivity type drain region of part;
In this second conductivity type shallow well district of this first conductivity type drain region that this patterning photoresist floor is exposed and below thereof, form this doped region; And
Remove this photoresist layer.
14, the manufacture method of flash memory cell as claimed in claim 10, the method that wherein forms this doped region comprises ion implantation technology.
15, the manufacture method of flash memory cell as claimed in claim 10, wherein this first conductivity type is a n type conductivity type, and this second conductivity type is a p type conductivity type.
16, a kind of flash memory cell comprises:
One first conductivity type substrate has been formed with one second conductivity type shallow well district in this first conductivity type substrate;
One stack structure is disposed in this first conductivity type substrate, and this stack structure is risen in regular turn by a dielectric layer between a tunneling dielectric layer, a floating grid, grid and a control grid by this first conductivity type substrate and constituted;
One first conductive type source region is disposed in this second conductivity type shallow well district in this first conductivity type substrate of a side of this stack structure;
One first conductivity type drain region is disposed in this second conductivity type shallow well district in this first conductivity type substrate of another example of this stack structure;
One metal silicide layer is disposed in this first conductivity type drain region, and this metal silicide layer runs through the knot in this first conductivity type drain region and this second conductivity type shallow well district;
One interlayer dielectric layer is disposed on this first conductivity type substrate and this stack structure; And
One contact plunger is formed in this interlayer dielectric layer, and is electrically connected to this first conductivity type drain region and this second conductivity type shallow well district via this metal silicide layer.
17, flash memory cell as claimed in claim 16 also comprises a clearance wall, is disposed at the sidewall of this stack structure, and this metal silicide layer is disposed in this first conductivity type drain region of the part that this clearance wall exposes.
18, flash memory cell as claimed in claim 16 also comprises a cap layer, is disposed on this control grid of this stack structure.
19, flash memory cell as claimed in claim 16, wherein this first conductivity type is the n type, and this second conductivity type is the p type.
20, a kind of flash memory cell comprises:
One first conductivity type substrate has been formed with one second conductivity type shallow well district in this first conductivity type substrate;
One stack structure is disposed in this first conductivity type substrate, and this stack structure is risen in regular turn by a dielectric layer between a tunneling dielectric layer, a floating grid, grid and a control grid by this first conductivity type substrate and constituted;
One first conductive type source region is disposed in this second conductivity type shallow well district in this first conductivity type substrate of a side of this stack structure;
One first conductivity type drain region is disposed in this second conductivity type shallow well district in this first conductivity type substrate of opposite side of this stack structure;
One metal silicide layer is disposed in this first conductivity type drain region;
One doped region is disposed in this first conductivity type drain region and this second conductivity type shallow well district of this metal silicide layer below, and this first conductivity type drain region via this doped region with this electrical short circuit in second conductivity type shallow well district.
One interlayer dielectric layer is disposed on this first conductivity type substrate and this stack structure; And
One contact plunger is formed in this interlayer dielectric layer, and via this metal silicide layer and this doped region and be electrically connected to this first conductivity type drain region and this second conductivity type shallow well district.
21, flash memory cell as claimed in claim 20 also comprises a clearance wall, is disposed at the sidewall of this stack structure, and this metal silicide layer is disposed in this first conductivity type drain region of the part that this clearance wall exposes.
22, flash memory cell as claimed in claim 20 also comprises a cap layer, is disposed on this control grid of this stack structure.
23, flash memory cell as claimed in claim 20, wherein this first conductivity type is the n type, and this second conductivity type is the p type.
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| CN101807579A (en) * | 2010-03-16 | 2010-08-18 | 复旦大学 | Charge-captured non-volatilization semiconductor memory and manufacturing method thereof |
| CN101335209B (en) * | 2007-06-27 | 2010-12-01 | 东部高科股份有限公司 | Flash memory device and methods for fabricating the same |
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| JP3425882B2 (en) * | 1999-03-04 | 2003-07-14 | Ｎｅｃエレクトロニクス株式会社 | Method for manufacturing semiconductor device |
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| CN101335209B (en) * | 2007-06-27 | 2010-12-01 | 东部高科股份有限公司 | Flash memory device and methods for fabricating the same |
| CN101399204B (en) * | 2007-09-30 | 2010-08-11 | 中芯国际集成电路制造(上海)有限公司 | Grid structure, flash memory and method for producing the same |
| CN101777562A (en) * | 2010-01-15 | 2010-07-14 | 复旦大学 | Non-volatile semiconductor memory with floating gate and manufacturing method thereof |
| CN101777562B (en) * | 2010-01-15 | 2015-05-20 | 复旦大学 | Non-volatile semiconductor memory with floating gate and manufacturing method thereof |
| CN101807579A (en) * | 2010-03-16 | 2010-08-18 | 复旦大学 | Charge-captured non-volatilization semiconductor memory and manufacturing method thereof |
| CN108124495A (en) * | 2015-07-24 | 2018-06-05 | 桑迪士克科技有限责任公司 | Three-dimensional storage device with metal and silicide control gate |
| CN108124495B (en) * | 2015-07-24 | 2021-11-26 | 桑迪士克科技有限责任公司 | Three-dimensional memory device with metal and silicide control gates |
| CN107437549A (en) * | 2016-05-26 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN107437549B (en) * | 2016-05-26 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN108122743A (en) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | contact openings and forming method thereof |
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