CN109994480A - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN109994480A CN109994480A CN201711470321.8A CN201711470321A CN109994480A CN 109994480 A CN109994480 A CN 109994480A CN 201711470321 A CN201711470321 A CN 201711470321A CN 109994480 A CN109994480 A CN 109994480A
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic device, the production method includes: offer semiconductor substrate, the semiconductor substrate includes core space, storage unit and selection grid are formed on the core space of the semiconductor substrate, the storage unit includes the floating gate, separation layer and control gate for stacking gradually setting；It is formed and covers the storage unit, the selection grid and the semiconductor substrate, and fill the free-flowing material layer in the gap between the adjacent storage unit and between the storage unit and the selection grid；The free-flowing material layer is handled, it is made to be changed into dielectric layer.The production method can overcome wordline inclination/buckling problem, reduce the interference between the line wordline of flash memory and cross-interference issue, to improve the performance and cycle period/read-write number of flash memory.The semiconductor devices has the advantages that similar with electronic device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technique
With the development of manufacture of semiconductor technology, the faster flash of access speed has been developed in terms of storage device
Device (flash memory).Flash memory is acted with can repeatedly carry out deposit, reading and erasing of information etc., and be stored in
The characteristic that information will not disappear after a loss of power, therefore, flash memory has become PC and electronic equipment is adopted extensively
A kind of nonvolatile memory.And NAND (NAND gate) fast storage is due to large storage capacity and relatively high property
Can, it is widely used in the more demanding field of read/write.
However, as technique enters 2Xnm (such as 20nm) and hereinafter, the depth-to-width ratio (AR) of wordline (word line) is more next
It is bigger, often there is wordline inclination/buckling problem, and it is dry between wordline when inclination/bending of wordline will lead to read-write operation
It disturbs that problem is more serious, upsets neighbouring bit location.
It is therefore desirable to propose a kind of semiconductor devices and preparation method thereof, electronic device, to solve the above problems.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention proposes a kind of semiconductor devices and preparation method thereof, electronic device, can be with
Overcome wordline inclination/buckling problem, reduce the interference between the line wordline of flash memory and cross-interference issue, to improve quick flashing
Performance and cycle period/read-write number of memory.
In order to overcome the problems, such as that presently, there are one aspect of the present invention provides a kind of production method of semiconductor devices, the system
Include: as method
Semiconductor substrate is provided, the semiconductor substrate includes core space, the shape on the core space of the semiconductor substrate
At having storage unit and selection grid, the storage unit includes the floating gate, separation layer and control gate for stacking gradually setting；
It is formed and covers the storage unit, the selection grid and the semiconductor substrate, and fill the adjacent storage
The free-flowing material layer in the gap between unit and between the storage unit and the selection grid；
The free-flowing material layer is handled, it is made to be changed into dielectric layer.
In an embodiment of the invention, the free-flowing material is formed by mobility chemical vapor deposition or spin-coating method
Layer.
In an embodiment of the invention, the free-flowing material layer includes four silicon substrate nitrogen.
In an embodiment of the invention, before forming the free-flowing material layer, further includes:
Clearance wall is formed on the side wall of the selection grid.
In an embodiment of the invention, clearance wall is formed on the side wall of the selection grid includes:
Patterned mask layer is formed on the semiconductor substrate, and it is single that the patterned mask layer covers the storage
Member, and the opening in the gap between the selection grid for having exposure adjacent；
Form the spacer material layer of the covering patterned mask layer and the semiconductor substrate；
The part that the clearance material layer is located at the patterned mask layer and the semiconductor substrate surface is removed, is protected
The part being located on the selection grid side wall is stayed, to form clearance wall on the side wall of the selection grid；
Remove the patterned mask layer.
In an embodiment of the invention, the semiconductor substrate further includes external zones, in the outer of the semiconductor substrate
It encloses and is formed with logic gate in area,
Wherein, it while forming clearance wall on the side wall of the selection grid, is also formed on the side wall of the logic gate
Clearance wall.
In an embodiment of the invention, the patterned mask layer does not cover the external zones of the semiconductor substrate.
In an embodiment of the invention, handled to the free-flowing material layer, make its be changed into dielectric layer it
Afterwards, further includes:
Form the contact pitting for covering the storage unit, the selection grid, the logic gate and the semiconductor substrate
Carve stop-layer；
Formed cover the storage unit, the selection grid, the logic gate and the semiconductor substrate initial interlayer
Dielectric layer；
Remove the part initial interlayer dielectric layer, the part contact etch stop layer, the part mobility material
The bed of material and the part clearance wall, with the selection grid of control gate, part described in exposed portion and the part logic gate；
Silicification technics is executed, so that the part control gate exposed, the part selection grid and the part logic gate
It is changed into silicide；
Formed cover the storage unit, the selection grid, the logic gate and the semiconductor substrate the first interlayer
Dielectric layer.
The production method of semiconductor device according to the invention fills the adjacent storage by using free-flowing material
Gap between unit and between the storage unit and the selection grid so that between the adjacent storage unit and
Gap between the storage unit and the selection grid is completely and homogeneously filled, to make wordline (i.e. storage unit) two
Stress suffered by side is consistent, to overcome wordline inclination/buckling problem, and improves the crosstalk between wordline and interference problem,
Improve device performance.
Another aspect of the present invention provides a kind of semiconductor devices, which includes: semiconductor substrate, described partly to lead
Body substrate includes core space, and storage unit and selection grid are formed on the core space of the semiconductor substrate, and the storage is single
Member includes the floating gate, separation layer and control gate for stacking gradually setting；Between the adjacent storage unit and the storage
Dielectric layer is filled in gap between unit and the selection grid, wherein the dielectric layer is by filling free-flowing material layer simultaneously
Processing is carried out to be formed.
In an embodiment of the invention, the free-flowing material layer includes four silicon substrate nitrogen.
In an embodiment of the invention, between being formed on the non-side wall adjacent with the storage unit of the selection grid
Gap wall.
In an embodiment of the invention, the semiconductor substrate further includes external zones, in the outer of the semiconductor substrate
It encloses and is formed with logic gate in area, be formed with clearance wall on the side wall of the logic gate.
Semiconductor device according to the invention, filled by using free-flowing material between the adjacent storage unit with
And the gap between the storage unit and the selection grid, so that between the adjacent storage unit and the storage is single
Gap between the first and described selection grid is completely and homogeneously filled, to make to answer suffered by wordline (i.e. storage unit) two sides
Power is consistent, to overcome wordline inclination/buckling problem, and improves the crosstalk between wordline and interference problem, improves device
Energy.
Further aspect of the present invention provides a kind of electronic device comprising as described above kind of semiconductor devices and with it is described
The electronic building brick that semiconductor devices is connected
Electronic device proposed by the present invention due to above-mentioned semiconductor device, thus has the advantages that similar.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows the step flow chart of the production method of semiconductor devices according to an embodiment of the present invention；
The production method that Fig. 2A~Fig. 2 J shows semiconductor devices according to an embodiment of the present invention is successively implemented respectively
The diagrammatic cross-section of the obtained semiconductor devices of step；
Fig. 3 shows the structural schematic diagram of semiconductor devices according to an embodiment of the present invention；
Fig. 4 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated phase from beginning to end
Identical element is indicated with appended drawing reference.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further include using with
The different orientation of device in operation.For example, then, being described as " below other elements " if the device in attached drawing is overturn
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
As previously mentioned, the depth-to-width ratio with flash memory (such as nand memory part) word-line/bit-line (WL/BL) increases
Add, be easy to appear wordline bending/tilt problem, to the various films (such as LPTEOS (low pressure in gap between filling adjacent word line
Tetraethoxy-silicane alkoxide), HTO (high-temperature oxide), ALDOXIDE (atomic layer deposition oxide)) tested, find
It will lead to tilt problem, think that these materials are easy to cause stress suffered by wordline two sides different, such as wordline two sides
There are gaps not of uniform size or side there are gap, and the other side is not present gap, can all make stress suffered by wordline two sides
Difference, so as to cause wordline bending/inclination., the present invention is based on this, the production method for proposing a kind of semiconductor devices, for making
Make flash memory, as shown in Figure 1, the production method includes: step 101, provides semiconductor substrate, the semiconductor substrate
Include core space, be formed with storage unit and selection grid on the core space of the semiconductor substrate, the storage unit include according to
Secondary floating gate, separation layer and the control gate for stacking setting；Step 102, which is formed, covers the storage unit, the selection grid and described
Semiconductor substrate, and fill between the adjacent storage unit and the gap between the storage unit and the selection grid
Free-flowing material layer.
The production method of semiconductor device according to the invention fills the adjacent storage by using free-flowing material
Gap between unit and between the storage unit and the selection grid so that between the adjacent storage unit and
Gap between the storage unit and the selection grid is completely and homogeneously filled, to make wordline (i.e. storage unit) two
Stress suffered by side is consistent, to overcome wordline inclination/buckling problem, and improves the crosstalk between wordline and interference problem,
Improve device performance.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiments.
Embodiment one
It does below with reference to production method of Fig. 2A~Fig. 2 J to the semiconductor devices of an embodiment of the present invention and retouches in detail
It states.
Firstly, shown in Fig. 2A, provide semiconductor substrate 200, the semiconductor substrate 200 include at least core space 200A and
External zones 200B is formed with storage unit and selection grid SG on the core space 200A of the semiconductor substrate 200, described half
The external zones 200B of conductor substrate 200 is formed with logic gate Gate.The storage unit includes the floating gate for stacking gradually setting
201, separation layer 202, control gate 203 and hard mask layer 204, the control gate are connect with wordline WL.It the selection grid SG and patrols
Collecting grid Gate equally includes the floating gate 201 for stacking gradually setting, separation layer 202, control gate 203 and hard mask layer 204, with storage
Unit is the difference is that there is opening in the separation layer 202 in the selection grid SG and logic gate Gate, so that upper and lower is floating
Grid 201 and control gate 203 are electrically connected to each other.
Wherein, semiconductor substrate 200 can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, semiconductor substrate 200
Constituent material select monocrystalline silicon.
In addition, can also be formed with isolation structure in semiconductor substrate 200, the isolation structure is shallow trench isolation
(STI) structure or selective oxidation silicon (LOCOS) isolation structure.The active area of semiconductor lining is defined by isolation structure, and will
Active area is divided into core space 200A and external zones 200B.Core space 200A is used to form storage unit and selection grid, external zones
200B is used to form external zones grid, such as logic gate or other grids.
Storage unit can be formed by method commonly used in the art, illustratively, can be made by following step:
Floating gate material layer, separation layer and control gate material layer and hard mask layer are deposited in semiconductor substrate 200, then pass through photoetching
Graphically the floating gate material layer, separation layer and control gate material layer are to form multiple storage units for the techniques such as etching, simultaneously
Selection grid and logic gate are formed, wherein the separation layer between selection grid and the floating gate and control gate of logic gate is formed with opening, makes
The floating gate and control gate for obtaining selection grid and logic gate link together.In the process, although hard mask layer 204 is consumed one
Part, but going back remnants on the storage unit, selection grid and external zones grid has hard mask layer, as shown in 204 in Fig. 2A.
Illustratively, in the present embodiment, the hard mask layer 204 of the remnants is oxide, such as silicon oxide layer.
Then, as shown in Figure 2 B, patterned mask layer 205 is formed on the semiconductor substrate, it is described patterned
Mask layer 205 covers the storage unit, and the opening in the gap between the selection grid for having exposure adjacent.
Patterned mask layer 205 can also be adopted using various suitable hard exposure masks, such as oxide or nitride
Use photoresist.Illustratively, in the present embodiment, patterned mask layer 205 uses photoresist layer, normal by this field
The operations such as coating, exposure, development production.Illustratively, the photoresist layer with a thickness of
Patterned mask layer 205 covers the storage unit in the core space 200A, and the exposure core space 200A
In gap between adjacent selection grid SG and external zones 200B namely patterned mask layer 205 do not cover external zones 200B
Gap between adjacent selection grid SG.Illustratively, in the present embodiment, the mask layer 205 that selection grid SG is patterned hides
The width for the part covered is the half of entire selection grid SG width.
Then, as shown in Figure 2 C, clearance wall 206 is formed on the side wall of the selection grid and logic gate.
Clearance wall 206 can use various suitable materials, such as oxide or nitride.In the present embodiment, due to
Patterned mask layer 205 uses photoresist, non-refractory, therefore clearance wall 206 preferably to use cryogenic material.Illustratively,
In the present embodiment, clearance wall 206 passes through atomic layer deposition work using the atomic layer deposition oxide (ALDOXIDE) of low temperature
The oxide that skill is formed.
Illustratively, the forming process of clearance wall 206 can be with are as follows:
Firstly, the spacer material layer for covering the patterned mask layer 205 and the semiconductor substrate 200 is formed,
The spacer material layer is, for example, the oxide for passing through the formation of ALD (atomic layer deposition) technique, illustratively, the oxide
With a thickness of
Then, the clearance material layer is removed by suitable dry etch process and is located at the patterned mask layer
205 and 200 surface of the semiconductor substrate part, retain be located at the selection grid and the logic gate side wall on part,
To form clearance wall 206 on the side wall of the selection grid and the logic gate.
Finally, the removal patterned mask layer 205.
Then, as shown in Figure 2 D, formed and cover the storage unit, the selection grid, the logic gate and described partly lead
Body substrate 200, and fill between the adjacent storage unit and the gap between the storage unit and the selection grid
Free-flowing material layer, and it is carried out processing formed dielectric layer 207.
The free-flowing material layer can use various suitable materials can be uniform with good filling capacity
And it is filled up completely between the adjacent storage unit and the gap between the storage unit and the selection grid.It is exemplary
Ground, in this embodiment, the free-flowing material layer 207 include four silicon substrate nitrogen.As an example, spin-coating method or mobility can be passed through
Chemical vapor deposition (FCVD) forms the free-flowing material layer.
Illustratively, the free-flowing material layer with a thickness of
After forming free-flowing material layer, then it is handled, such as oxidation processes and tempering, make its transformation
For dielectric layer.For example, being changed into it after carrying out oxygen shield (handling in deionized water), tempering by four silicon substrate nitrogen
Silica.
Then, as shown in Figure 2 E, formed and cover the storage unit, selection grid, logic gate and the semiconductor substrate 200
Contact etch stop layer 208.
Contact etch stop layer 208 can use various suitable materials, such as oxide or nitride etc., can be with
It is formed by the methods of thermal oxidation method, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (atomic layer deposition).Show
Example property, in the present embodiment, contact etch stop layer 2080 uses nitride, passes through furnace process (furnace) shape
At in subsequent progress contact hole etching as stop-layer.Illustratively, in the present embodiment, contact etch stop layer 208
With a thickness of
Then, it as described in Fig. 2 F, is formed and covers the storage unit, selection grid, logic gate and the semiconductor substrate
Initial interlayer dielectric layer 209.
Initial interlayer dielectric layer 209 can use various suitable materials, such as oxide or nitride etc., can lead to
Cross the methods of thermal oxidation method, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (atomic layer deposition) formation.Example
Property, in the present embodiment, initial interlayer dielectric layer 209 uses oxide, passes through high-aspect-ratio processing procedure (HARP), high density
Plasma (HDP) or plasma enhancing tetraethoxysilane (PETEOS) technique are formed.
Further, after having deposited initial interlayer dielectric layer 209, further include the steps that planarization, pass through such as machine
The flatening process such as tool grinding, chemically mechanical polishing (CMP), and using contact etch stop layer 208 as stop-layer to initial
Interlayer dielectric layer 209 is planarized, so that height is consistent everywhere on surface.
Then, as shown in Figure 2 G, initial interlayer dielectric layer remaining on the storage unit, selection grid and logic gate is removed
209。
Illustratively, recess etching is carried out by wet-etching technology, to remove the storage unit, selection grid and logic
Remaining initial interlayer dielectric layer 209 on grid.The wet-etching technology is for example, by using diluted hydrofluoric acid or hydrofluoric acid and BOE
The mixed solution of (buffer oxide etcher, buffered oxide etch agent).
It should be appreciated that the initial interlayer dielectric layer of oxygen remaining on the storage unit described in this process, selection grid and logic gate
209 have been removed a part.
Then, as illustrated in figure 2h, the removal part initial interlayer dielectric layer 209, the part contact etch stop
Layer 208, the part free-flowing material layer 207 and the part clearance wall 206, with control gate described in exposed portion, part institute
State selection grid and the part logic gate.
Illustratively, by dry etch process execute etch-back, with remove the part initial interlayer dielectric layer 209,
The part contact etch stop layer 208, the part free-flowing material layer 207 and the part clearance wall 206, to expose
The part control gate, the part selection grid and the part logic gate.The dry method etch technology includes but is not limited to: anti-
Answer ion(ic) etching (RIE), ion beam milling, plasma etching or laser cutting.Illustratively, in the present embodiment, it adopts
With reactive ion etching (RIE), the technological parameter of the dry etching includes: that etching gas includes the gases such as CF4 or CHF3,
Flow is respectively 50sccm~500sccm, 10sccm~100sccm, and pressure is 2mTorr~50mTorr, wherein sccm is represented
Cc/min, mTorr represent Hao Tuo.
Illustratively, in the present embodiment, when carrying out etch-back by dry etch process, etching depth is
It should be appreciated that in the process, the hard mask layer 204 at the top of the storage unit, selection grid and logic gate is gone
It removes.
Then, as shown in figure 2i, silicification technics is executed, so that the part control gate exposed, the part selection grid
It is changed into silicide 210 with the part logic gate.
Illustratively, can be made by silicification technics commonly used in the art described in the part control gate exposed, part
Selection grid and the part logic gate are changed into silicide 210, more specifically for example, on storage unit, selection grid and logic gate top
Portion's deposited metal layer, such as nickel, then execute one or many thermal annealings, so that metal layer and pasc reaction form silicide, most
Removal is the metal layer of reaction afterwards.
Finally, as shown in fig. 2j, is formed and cover the storage unit, the selection grid, the logic gate and described partly lead
First interlayer dielectric layer 211 of body substrate 200.
First interlayer dielectric layer 211 can use various suitable dielectric materials, such as oxide or nitride.It is exemplary
Ground, in the present embodiment, the first interlayer dielectric layer 211 use oxide, such as USG (non-impurity-doped silica glass), BSG (boron-doped silicon
Glass), BPSG (boron-phosphorosilicate glass) etc., can be made by techniques such as CVD, ALD.
So far, the processing step implemented according to the method for the embodiment of the present invention is completed, it is to be understood that the present embodiment
The production method of semiconductor devices not only includes above-mentioned steps, before above-mentioned steps, among or may also include later other need
The step of wanting, such as source-drain area ion implanting, annealing, it is included in the range of the present embodiment production method.
According to the production method of the semiconductor devices of the present embodiment, by using free-flowing material fill it is adjacent described in deposit
Gap between storage unit and between the storage unit and the selection grid so that between the adjacent storage unit with
And the gap between the storage unit and the selection grid is completely and homogeneously filled, to make wordline (i.e. storage unit)
Stress suffered by two sides is consistent, to overcome wordline inclination/buckling problem, and improves the crosstalk between wordline and interference is asked
Topic improves device performance.
Embodiment two
The present invention also provides a kind of semiconductor devices, as shown in figure 3, the semiconductor devices includes: semiconductor substrate 300,
The semiconductor substrate 300 includes at least core space 300A and external zones 300B, in the core space of the semiconductor substrate 300
It is formed with storage unit and selection grid on 300A, is formed with logic gate in the external zones 300B of the semiconductor substrate 300, it is described
Storage unit includes the floating gate 301 for stacking gradually setting, separation layer 302, control gate 303 and silicide 304；In the selection grid
With the first clearance wall 305 is formed on the side wall of the logic gate；Between the adjacent storage unit and the storage
Dielectric layer 306 is filled in gap between unit and the selection grid, dielectric layer 306 is gone forward side by side by filling free-flowing material layer
Row processing is formed；Interlayer dielectric layer 307, the interlayer dielectric layer 307 cover the storage unit, and the selection grid described is patrolled
Collect grid and the semiconductor substrate 300.
Wherein semiconductor substrate 300 can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode are also possible to the metal interconnection structure, etc. being electrically connected with transistor.
Isolation structure can also be formed in semiconductor substrate 300, the isolation structure is shallow trench isolation (STI) knot
Structure or selective oxidation silicon (LOCOS) isolation structure.The active area of semiconductor lining is defined by isolation structure, and by active differentiation
It is divided into core space 300A and external zones 300B.Core space 300A is used to form storage unit and selection grid, and external zones 300B is used for
Form external zones grid, such as logic gate or other grids.
The storage unit includes the floating gate 301 for stacking gradually setting, separation layer 302, control gate 303 and silicide 304,
The control gate is connect with wordline WL.The selection grid SG and logic gate Gate equally include the floating gate 301 for stacking gradually setting,
Separation layer 302, control gate 303 and silicide 304, with storage unit the difference is that the selection grid SG and logic gate
There is opening in the separation layer 302 in Gate, so that upper and lower floating gate 301 and control gate 303 is electrically connected to each other.Wherein, floating gate 301
It can be using common used materials such as materials commonly used in the art, such as polysilicon with control gate 303.And separation layer 302 is then preferably
Using ONO structure, that is, oxide, nitride, oxide structure both have good interface performance, it may have higher in this way
Dielectric constant.
Clearance wall 305 can use various spacer materials, such as oxide or nitride.Illustratively, in this reality
It applies in example, clearance wall 305 uses oxide, for example, ALDOXIED (oxide that atomic layer deposition is formed).Further, exist
In the present embodiment, clearance wall 305 is made only on the non-side wall adjacent with the storage unit of selection grid.
Dielectric layer 306 passes through filling free-flowing material layer and carries out processing and formed.Illustratively, in the present embodiment, it is situated between
Matter layer 306 is silicon oxide layer, by between the adjacent storage unit and the storage unit and the selection grid
Between gap in fill free-flowing material layer, and through peroxide shield and tempering formed.The free-flowing material layer is, for example,
Four silicon substrate nitrogen.
Interlayer dielectric layer 307 can use various suitable dielectric materials, such as oxide or nitride.Illustratively,
In the present embodiment, the first interlayer dielectric layer 211 uses oxide, such as USG (non-impurity-doped silica glass), BSG (boron-doped silicon glass
Glass), BPSG (boron-phosphorosilicate glass) etc..
According to the semiconductor devices of the present embodiment, filled by using free-flowing material between the adjacent storage unit
And the gap between the storage unit and the selection grid, so that between the adjacent storage unit and the storage
Gap between unit and the selection grid is completely and homogeneously filled, to make suffered by wordline (i.e. storage unit) two sides
Stress is consistent, to overcome wordline inclination/buckling problem, and improves the crosstalk between wordline and interference problem, improves device
Performance.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic device, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, which includes: semiconductor substrate, and the semiconductor substrate includes core space,
Storage unit and selection grid are formed on the core space of the semiconductor substrate, the storage unit includes stacking gradually setting
Floating gate, separation layer and control gate；Between the adjacent storage unit and between the storage unit and the selection grid
Gap in be filled with dielectric layer, wherein the dielectric layer is by filling free-flowing material layer and carries out processing and is formed.
Wherein, semiconductor substrate can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode are also possible to the metal interconnection structure, etc. being electrically connected with transistor.In the present embodiment, semiconductor substrate
Constituent material select monocrystalline silicon.
Further, floating gate and control gate can be using common used materials such as materials commonly used in the art, such as polysilicon.And
Separation layer then preferably uses ONO structure, that is, oxide, nitride, oxide structure had both had good interface characteristics in this way
It can, it may have higher dielectric constant.
Further, free-flowing material layer 306 can use various suitable materials, with good filling capacity,
Can uniformly and be filled up completely between the adjacent storage unit and between the storage unit and the selection grid between
Gap.Illustratively, the free-flowing material layer 306 be, for example, organic distribution layer (Organic distribution layer,
ODL) or organic bottom antireflective coating (BARC), constituent material include but is not limited to polysulfones, polyureas, polysulfones ureas,
Polyacrylate and polyvinylpyridine.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.
Wherein, Fig. 4 shows the example of mobile phone.The outside of mobile phone 400 is provided with including the display portion in shell 401
402, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..
The electronic device of the embodiment of the present invention changes since the semiconductor devices for being included overcomes wordline bending/tilt problem
The crosstalk and interference problem being apt between bit line, improve device performance.Therefore the electronic device equally has the advantages that similar.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of production method of semiconductor devices characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate includes core space, is formed on the core space of the semiconductor substrate
Storage unit and selection grid, the storage unit include the floating gate, separation layer and control gate for stacking gradually setting；
It is formed and covers the storage unit, the selection grid and the semiconductor substrate, and fill the adjacent storage unit
Between and gap between the storage unit and the selection grid free-flowing material layer；
The free-flowing material layer is handled, it is made to be changed into dielectric layer.
2. the production method of semiconductor devices according to claim 1, which is characterized in that pass through mobility chemical vapor deposition
Long-pending or spin-coating method forms the free-flowing material layer.
3. the production method of semiconductor devices according to claim 1, which is characterized in that the free-flowing material layer includes
Four silicon substrate nitrogen.
4. the production method of semiconductor devices described in any one of -3 according to claim 1, which is characterized in that forming institute
Before the free-flowing material layer stated, further includes:
Clearance wall is formed on the side wall of the selection grid.
5. the production method of semiconductor devices according to claim 4, which is characterized in that on the side wall of the selection grid
Forming clearance wall includes:
Patterned mask layer is formed on the semiconductor substrate, the patterned mask layer covers the storage unit,
And the opening in the gap between the selection grid for having exposure adjacent；
Form the spacer material layer of the covering patterned mask layer and the semiconductor substrate；
Remove the part that the clearance material layer is located at the patterned mask layer and the semiconductor substrate surface, reserved bit
Part on the selection grid side wall, to form clearance wall on the side wall of the selection grid；
Remove the patterned mask layer.
6. the production method of semiconductor devices according to claim 5, which is characterized in that the semiconductor substrate further includes
External zones is formed with logic gate in the external zones of the semiconductor substrate,
Wherein, while forming clearance wall on the side wall of the selection grid, gap also is formed on the side wall of the logic gate
Wall.
7. the production method of semiconductor devices according to claim 6, which is characterized in that the patterned mask layer is not
Cover the external zones of the semiconductor substrate.
8. the production method of semiconductor devices according to claim 6, which is characterized in that the free-flowing material layer
It is handled, is changed into it after dielectric layer, further includes:
The contact etch for forming the covering storage unit, the selection grid, the logic gate and the semiconductor substrate stops
Only layer；
It is formed and covers the storage unit, the selection grid, the initial interlayer dielectric of the logic gate and the semiconductor substrate
Layer；
Remove the part initial interlayer dielectric layer, the part contact etch stop layer, the part free-flowing material layer
With the part clearance wall, with the selection grid of control gate, part described in exposed portion and the part logic gate；
Silicification technics is executed, so that the part control gate exposed, the logic gate transformation of the part selection grid and part
For silicide；
It is formed and covers the storage unit, the selection grid, the first interlayer dielectric of the logic gate and the semiconductor substrate
Layer.
9. a kind of semiconductor devices characterized by comprising
Semiconductor substrate, the semiconductor substrate include core space, and storage is formed on the core space of the semiconductor substrate
Unit and selection grid, the storage unit include the floating gate, separation layer and control gate for stacking gradually setting；
Filled media in gap between the adjacent storage unit and between the storage unit and the selection grid
Layer is formed wherein the dielectric layer passes through filling free-flowing material layer and carries out processing.
10. semiconductor devices as claimed in claim 9, which is characterized in that the free-flowing material layer includes four silicon substrate nitrogen.
11. semiconductor devices as claimed in claim 9, which is characterized in that non-with the storage unit phase in the selection grid
Clearance wall is formed on adjacent side wall.
12. semiconductor devices as claimed in claim 10, which is characterized in that the semiconductor substrate further includes external zones,
It is formed with logic gate in the external zones of the semiconductor substrate, is formed with clearance wall on the side wall of the logic gate.
13. a kind of electronic device, which is characterized in that including semiconductor devices described in any one of claim 9 to 12 with
And the electronic building brick being connected with the semiconductor devices.
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