CN105244322A - Formation method of semiconductor structure - Google Patents
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- CN105244322A CN105244322A CN201410272775.4A CN201410272775A CN105244322A CN 105244322 A CN105244322 A CN 105244322A CN 201410272775 A CN201410272775 A CN 201410272775A CN 105244322 A CN105244322 A CN 105244322A
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Abstract
The invention relates to a formation method of a semiconductor structure, which comprises the steps of providing a substrate, and forming a trench in the substrate; forming a precursor material with which the trench is filled by adopting a mobility chemical vapor deposition technology; carrying out annealing treatment on the precursor material, transforming the precursor material layer into a first dielectric layer, wherein materials of the first dielectric layer contain nitrogen atoms, and the nitrogen atoms have a first atom quantity; and adopting oxygen atoms to replace the nitrogen atoms in the materials of the first dielectric layer, and transforming the first dielectric layer into a second dielectric layer, wherein nitrogen atoms in materials of the second dielectric layer have a second atom quantity, and the second atom quantity is less than the first atom quantity. According to the invention, the quantity of Si-N bonds and Si-N-H bonds in the second dielectric layer is reduced through a method of replacing the nitrogen atoms with the oxygen atoms, thereby improving the compactness and the hardness of the formed second dielectric layer, and optimizing electrical properties of the semiconductor structure.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, particularly a kind of formation method of semiconductor structure.
Background technology
Along with the development of manufacture of semiconductor technology, in storage device, develop access speed flash memory (flashmemory) faster.Flash memory have information of can repeatedly carrying out stored in, read and the action such as erasing, and stored in the information characteristic that also can not disappear after a loss of power, therefore, flash memory has become a kind of nonvolatile memory that PC and electronic equipment extensively adopt.Wherein, flash memory is according to the difference of array structure, main point NAND gate flash memory and NOR gate flash memory, because NAND gate flash memory is higher than the integrated level of NOR gate flash memory, so NAND gate flash memory has wider range of application.
Typical NAND gate flash memory is using the polysilicon of doping as floating grid (floatinggate) and control gate (controlgate); Wherein, control gate is formed on floating grid, and is separated by by dielectric layer between grid; Floating grid is formed on substrate, is separated by by one deck tunneling medium layer (tunneloxide).When carrying out the write operation of information to flash memory, by applying bias voltage in control gate and source/drain regions, make in electron injection floating grid; When reading flash memory information, apply an operating voltage in control gate, now the electriferous state of floating grid can affect the ON/OFF of its lower channels (channel), and the ON/OFF of this raceway groove is the foundation judging the value of information 0 or 1; When flash memory is at erasure information, the relative potentials of substrate, source region, drain region or control gate is improved, and utilize tunneling effect to make electronics enter in substrate, source region or drain region by floating grid through tunneling medium layer, or enter in control gate through dielectric layer between grid.
Along with the continuous reduction of semiconductor structure size, the electric property of the semiconductor structure containing flash memory and reliability need to be improved further.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, improves density and the hardness of the dielectric layer adopting mobility chemical vapor deposition method to be formed, improves the performance of dielectric layer material.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprising: substrate is provided, in described substrate, being formed with groove; Mobility chemical vapor deposition method is adopted to form the precursor material layer of filling full described groove; Carry out annealing in process to described precursor material, precursor material layer is converted into first medium layer, containing nitrogen-atoms in described first medium layer material, and described nitrogen-atoms has the first atomic quantity; Employing oxygen atom replaces the nitrogen-atoms in described first medium layer material, and first medium layer is converted into second dielectric layer, and in described second medium layer material, nitrogen-atoms has the second atomic quantity, and the second atomic quantity is less than the first atomic quantity.
Optionally, silicon atom and nitrogen-atoms is at least comprised in described precursor material layer material.
Optionally, the precursor material that described mobility chemical vapor deposition method adopts comprises one or more in three silica-based nitrogen, silane, disilane, methyl-monosilane, dimethylsilane, trimethyl silane, tetramethylsilane, tetraethoxysilane, triethoxysilane, octamethylcy-clotetrasiloxane, tetramethyl disiloxane, tetramethyl-ring tetrasiloxane, trimethylsilyl amine, dimethyl silanyl amine.
Optionally, described mobility chemical vapor deposition method is carried out under nitrogenous atmosphere.
Optionally, the method adopting oxygen atom to replace the nitrogen-atoms of described first medium layer material is: adopt oxygen containing deionized water to carry out immersion treatment to described first medium layer.
Optionally, the oxygen element in described oxygen containing deionized water is ozone ion.
Optionally, in described oxygen containing deionized water, the mass percent of ozone ion is 5% to 25%.
Optionally, the duration of described immersion treatment is 30min to 60min, and temperature during immersion treatment is 50 degree to 80 degree.
Optionally, also step is comprised: plasma bombardment is carried out to described second dielectric layer surface.
Optionally, the technological parameter of described plasma bombardment is: described plasma is formed by He, Ne, Xe, Kr or Ar gaseous plasmaization, He, Ne, Xe, Kr or Ar gas flow is 50sccm to 500sccm, low frequency RF power is 100 watts to 1500 watts, and HFRF power is 100 watts to 1500 watts.
Optionally, described annealing in process is being carried out containing under oxygen atmosphere.
Optionally, the anneal duration of described annealing in process comprises continuous print first duration, the second duration and the 3rd duration, wherein, annealing temperature in first duration is the first temperature, annealing temperature in second duration is by the first temperature increment to the second temperature, and the annealing temperature in the 3rd duration is the second temperature.
Optionally, described first temperature is 200 degree to 450 degree, and described second temperature is 550 degree to 650 degree.
Optionally, also step is comprised: the second annealing in process is carried out to described second dielectric layer; Return the second dielectric layer that etching removes segment thickness.
Optionally, the technological parameter of described second annealing in process is: annealing temperature is 800 degree to 950 degree, and anneal duration is 20min to 40min.
Optionally, described substrate comprises substrate, is positioned at the tunneling medium layer of substrate surface and is positioned at the floating boom conductive layer on tunneling medium layer surface.
Optionally, return the second dielectric layer that etching removes segment thickness, make remaining second dielectric layer top lower than floating boom conductive layer top surface.
Optionally, also step is comprised: form dielectric layer between grid at described floating boom conductive layer top surface and sidewall surfaces, remaining second dielectric layer surface; Dielectric layer surface formation control grid conductive layer between described grid.
Optionally, the processing step forming described groove comprises: form patterned mask layer at described floating boom conductive layer surface; With described patterned mask layer for mask, etch the substrate of described floating boom conductive layer, tunneling medium layer and segment thickness, form groove.
Optionally, after formation first medium layer, also step is comprised: remove the first medium layer higher than patterned mask layer surface; Remove described patterned mask layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the embodiment of the present invention, adopt mobility chemical vapor deposition method to form the precursor material layer of filling full groove, annealing in process is carried out to described precursor material layer, precursor material layer is converted into first medium layer, containing nitrogen-atoms in first medium layer material, and nitrogen-atoms has the first atomic quantity; Adopt the nitrogen-atoms in atomic substitutions first medium layer material, first medium layer is converted into second dielectric layer, and in described second medium layer material, nitrogen-atoms has the second atomic quantity, and the second atomic quantity is less than the first atomic quantity.In first medium layer Si-N key and Si-N-H bond number amount more, and after adopting the nitrogen-atoms in oxygen atom displacement first medium layer, in the second dielectric layer formed, Si-N key and Si-N-H bond number amount significantly decrease, and the quantity of Si-O key and O-Si-O key obviously increases in second dielectric layer, compactness and the hardness of second dielectric layer are improved, improve the performance of the second dielectric layer formed, and then optimize the electric property of semiconductor structure.
Further, the oxygen element in described oxygen containing deionized water is ozone ion, and the oxygen content of ozone ion is high and active high in aqueous, easily spreads in first medium layer, improves the efficiency of oxygen atom displacement nitrogen-atoms.
Further, the embodiment of the present invention also comprises step: carry out plasma bombardment to second dielectric layer surface, and under high-octane plasma bombardment, second dielectric layer surface property is improved, and improves the compactness on second dielectric layer surface further.
Further, in the embodiment of the present invention after formation first medium layer, remove the first medium layer higher than patterned mask layer, make the lower thickness of first medium layer, therefore in immersion treatment process, the evolving path that oxygen atom diffuses in first medium layer shortens, and the difficulty that oxygen atom diffuses in first medium layer reduces, thus improves the efficiency of oxygen atom displacement nitrogen-atoms; Reduce the duration of immersion treatment simultaneously, reduce the harmful effect that immersion treatment causes as far as possible, improve the performance of second dielectric layer.
Further, in the embodiment of the present invention, substrate comprises substrate, is positioned at the tunneling medium layer of substrate surface and is positioned at the floating boom conductive layer on tunneling medium layer surface; Return the second dielectric layer that etching removes segment thickness, make remaining second dielectric layer top lower than floating boom conductive layer top surface, expose floating boom Conductive layer portions sidewall surfaces, increase the overlapping area between floating boom conductive layer and control gate conductive layer, increase the coupling efficiency of semiconductor structure, optimize electric property and the reliability of semiconductor structure.
Further, because the second dielectric layer material property formed after embodiment of the present invention employing oxygen atom displacement nitrogen-atoms is higher, second dielectric layer compactness and hardness high, return etching technics to reach unanimity to each region etch speed of second dielectric layer, therefore after time etching technics completes, remaining second dielectric layer surface flatness is higher, makes the thickness evenness of dielectric layer between the grid of described second dielectric layer surface formation high, improves electric property and the reliability of semiconductor structure.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of an embodiment method for forming semiconductor structure;
The cross-sectional view of the semiconductor structure formation process that Fig. 2 to Figure 12 provides for another embodiment of the present invention.
Embodiment
From background technology, the electric property of the semiconductor structure that prior art is formed and reliability have much room for improvement.
Formation method for semiconductor structure is studied, please refer to Fig. 1, the formation method of semiconductor structure comprises the following steps: step S1, provide substrate, forms tunneling medium layer, is positioned at the floating boom conductive layer on tunneling medium layer surface successively at described substrate surface; Step S2, etch the substrate of described floating boom conductive layer, tunneling medium layer and segment thickness, form groove; The dielectric layer of step S3, the full described groove of formation filling, and described dielectric layer surface is higher than floating boom conductive layer surface; Step S4, time etching remove the dielectric layer of segment thickness, expose floating boom conductive layer sidewall surfaces; Step S5, form dielectric layer between grid at described remaining dielectric layer surface, floating boom conductive layer sidewall surfaces and top surface; Step S6, between described grid dielectric layer surface formation control grid conductive layer.
Along with the continuous reduction of semiconductor structure size, the electric property of the semiconductor structure adopting said method to be formed is deteriorated, reliability step-down.Find after deliberation, after the dielectric layer returning etching removal segment thickness, remaining dielectric layer surface poor performance, remaining dielectric layer surface is uneven, cause dielectric layer in uneven thickness between the grid that formed at dielectric layer surface, this is one of major reason for the electric property difference causing semiconductor structure.Find by analysis, after causing back etching, the rough reason of dielectric layer surface is as follows:
Along with the continuous reduction of semiconductor structure size, the width of groove constantly reduces, in groove, the difficulty of filled media layer is increasing, in order to improve filling gap (gap-filling) ability of dielectric layer, avoid forming cavity wherein during filled media material in groove, usually adopt the precursor material of mobility to form the precursor material layer of filling full groove.As an embodiment, the technique forming the precursor material layer of filling full groove adopts mobility chemical vapour deposition (CVD) (FCVD, FlowableCVD) technology, and then form the dielectric layer of filling full groove, concrete, the processing step forming the dielectric layer of filling full groove comprises: adopt FCVD technology to form the precursor material layer of filling full groove, containing silicon atom and nitrogen-atoms in precursor material layer material; Being cured process to described precursor material layer, is dielectric layer by precursor material layer change.
Above-mentioned solidification process is normally containing the annealing in process of carrying out under oxygen atmosphere, the material of oxygen and precursor material layer is reacted, formed in Si-O or O-Si-O one or both, nitrogen-atoms is taken out of from forerunner's material layer, makes precursor material layer change be the dielectric layer of isolation structure.If the temperature of annealing in process is too high, the precursor material layer of flute surfaces then can be caused to change dielectric layer into completely at short notice, the compactness of the dielectric layer of flute surfaces is comparatively strong and cause oxygen to be difficult to enter in the precursor material layer of channel bottom, the transforming degree of the precursor material layer of channel bottom is limited, therefore, annealing in process generally adopts comparatively low temperature thermal oxidation (being less than 700 degrees Celsius).
But, the lower harmful effect that can bring again other of annealing temperature of annealing in process, concrete, because annealing temperature is lower, the limitation of the material generation chemical reaction of oxygen and precursor material layer, after solidification process completes, nitrogen atom content in precursor material layer is still higher, in precursor material layer, the content of Si-N key and Si-N-H key is higher, and the existence of described Si-N key and Si-N-H key causes the compactness of the dielectric layer formed poor, and the quality of dielectric layer is softer.When to described compactness difference and the softer dielectric layer of quality carries out back etching processing time, return the etch rate of etching technics to each region of dielectric layer surface to be difficult to reach unanimity, therefore after time etching completes, remaining dielectric layer surface presents rough state, cause the thickness evenness of dielectric layer between the grid of dielectric layer surface poor, so cause the reliability of semiconductor structure and electric property poor.
For this reason, the invention provides a kind of formation method of semiconductor structure, substrate is provided, in described substrate, be formed with groove; Mobility chemical vapor deposition method is adopted to form the precursor material layer of filling full described groove; Carry out annealing in process to described precursor material, precursor material layer is converted into first medium layer, containing nitrogen-atoms in described first medium layer material, and described nitrogen-atoms has the first atomic quantity; Employing oxygen atom replaces the nitrogen-atoms in described first medium layer material, and first medium layer is converted into second dielectric layer, and in described second medium layer material, nitrogen-atoms has the second atomic quantity, and the second atomic quantity is less than the first atomic quantity.The present invention is by adopting the method for oxygen atom displacement nitrogen-atoms, reduce the quantity of Si-N and Si-N-H key in second dielectric layer, add the quantity of Si-O and O-Si-O key in second dielectric layer, thus improve density and the hardness of second dielectric layer, optimize electric property and the reliability of semiconductor structure.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The cross-sectional view of the semiconductor structure formation process that Fig. 2 to Figure 12 provides for another embodiment of the present invention.
Please refer to Fig. 2, provide substrate, described substrate comprises substrate 200, is positioned at the tunneling medium layer 201 on substrate 200 surface and is positioned at the floating boom conductive layer 202 on tunneling medium layer 201 surface.
The material of described substrate 200 is silicon, germanium, SiGe, GaAs, carborundum or isolate supports.In the present embodiment, the material of described substrate 200 is silicon.
Described tunneling medium layer 201 is at the bottom of isolation liner 200 and floating boom conductive layer 202.
The material of described tunneling medium layer 201 is silica, silicon nitride or silicon oxynitride, and formation process is thermal oxidation method or chemical vapour deposition technique.
In the present embodiment, the material of described tunneling medium layer 201 is silica, and thickness is 50 dust to 150 dusts, adopts thermal oxidation method to be formed.
After formation tunneling medium layer 201, also comprise step: well region ion doping is carried out to substrate 200.Concrete, when the semiconductor structure of formation is PMOS device, N-type ion doping is carried out to substrate 200 and forms N-type well region; When the semiconductor structure formed is nmos device, P type ion doping is carried out to substrate 200 and forms P type trap zone.
The material of described floating boom conductive layer 202 is polysilicon, is formed by chemical vapor deposition method and diffusion technology.
In the present embodiment, described floating boom conductive layer 202 is formed by depositing polysilicon and phosphorus doping, and the thickness of described floating boom conductive layer 202 is 200 dust to 2000 dusts.
The present embodiment is for the semiconductor structure formed for flash memory does exemplary illustrated, and in other embodiments, the semiconductor structure of formation also can be transistor.
Please refer to Fig. 3, form patterned mask layer 203 on described floating boom conductive layer 202 surface, described patterned mask layer 203 has the opening 204 exposing floating boom conductive layer 202 surface.
The material of described patterned mask layer 203 is silica or silicon nitride, and described patterned mask layer 203 is single layer structure or multilayer lamination structure, and the present embodiment does exemplary illustrated for described patterned mask layer 203 for single layer structure.
The position of described opening 204 and size correspond to position and the size of the isolation structure of follow-up formation.
As an embodiment, the forming step of described patterned mask layer 203 comprises: form original mask layer on described floating boom conductive layer 202 surface; Patterned photoresist layer is formed on described original mask layer surface; With described patterned photoresist layer for mask, etch described original mask layer, form patterned mask layer 203, described patterned mask layer 203 has opening 204; Remove described patterned photoresist layer.
In the present embodiment, the material of described patterned mask layer 203 is silicon nitride, and the thickness of described patterned mask layer 203 is 2000 dust to 10000 dusts.
Please refer to Fig. 4, with described patterned mask layer 203 for mask, etch the substrate 200 of described floating boom conductive layer 202, tunneling medium layer 201 and segment thickness along opening 204 (please refer to Fig. 3), form groove 205.
In the present embodiment, adopt dry etch process, etch the substrate 200 of floating boom conductive layer 202, tunneling medium layer 201 and segment thickness successively.
As a specific embodiment, described dry etch process is reactive ion etching, and the technological parameter of reactive ion etching process is: etching gas is HBr, He and O
2, wherein, HBr flow is 100sccm to 600sccm, He flow is 100sccm to 600sccm, O
2flow is 2sccm to 20sccm, and reaction chamber pressure is that 5 holders to 50 are held in the palm, and bias voltage is 50V to 300V.
Please refer to Fig. 5, adopt mobility chemical vapor deposition method to form the precursor material layer 206 of filling full described groove 205 (please refer to Fig. 4), described precursor material layer 206 is also covered in patterned mask layer 203 surface.
Carrying out in mobility chemical deposition process process, substrate 200 is remained in predetermined temperature range, the filling that the pre-reaction material material of mobility chemical vapor deposition method flows is entered in groove 205, thus forms the precursor material layer 206 of filling full groove 205.Especially, lower substrate 200 temperature (lower than 150 DEG C) can keep the mobility of pre-reaction material material in substrate 200 and groove 205 and viscosity.
Because pre-reaction material material has certain mobility and viscosity, the pre-reaction material material with mobility is packed into after in groove 205, carry out bottom groove 205 filling without cavity, thus avoided generation cavity bottom groove 205; And, because the precursor material layer 206 formed has certain flowable and viscosity, follow-up after the first annealing in process, employing oxygen atom displacement nitrogen-atoms, fracture and restructuring can be there is in the chemical bond of precursor material layer 206 material, form new chemical bond or functional group, thus precursor material layer 206 is converted into the second dielectric layer of isolation structure.
In the present embodiment, carrying out in mobility chemical vapor deposition method process, the temperature of substrate 200 is less than 150 DEG C, and such as, the temperature of substrate 200 is 20 DEG C, 50 DEG C, 70 DEG C or 110 DEG C etc.
The pre-reaction material material that described mobility chemical vapor deposition method adopts comprises: one or more of three silica-based nitrogen (TSA), silane, disilane, methyl-monosilane, dimethylsilane, trimethyl silane, tetramethylsilane, tetraethoxysilane, triethoxysilane, octamethylcy-clotetrasiloxane, tetramethyl disiloxane, tetramethyl-ring tetrasiloxane, trimethylsilyl amine, dimethyl silanyl amine.Other pre-reaction material such as silanamines and derivative thereof materials can also be used.
Described mobility chemical vapor deposition method is carried out under nitrogenous atmosphere, and described nitrogenous atmosphere is H
2and N
2mist, N
2, NH
3, NH
4oH, N
2h
4, NO, N
2o, NO
2, O
3, O
2, H
2o
2in one or more atmospheres, and at least comprise a kind of nitrogenous atmosphere.
In the present embodiment, adopt three base silicon nitrogen as the pre-reaction material material of mobility chemical vapor deposition method, at NH
3described mobility chemical vapor deposition method is carried out under atmosphere.
Concrete, be placed in reaction chamber by the substrate 200 of concrete groove 205, mobility chemical vapor deposition method parameter is: pre-reaction material material enters in reaction chamber with the flow velocity of 100sccm to 3000sccm, NH
3enter in reaction chamber with the flow velocity of 20sccm to 1000sccm, reaction chamber pressure is 0.1T to 10T, reaction chamber temperature is 20 DEG C to 150 DEG C, and can also pass into the inert gases such as Ar, He or Xe in reaction chamber, inert gas flow velocity is 1000sccm to 10000sccm.
In an embodiment of the present invention, containing Si in described pre-reaction material, and mobility chemical vapor deposition method is carried out under nitrogenous atmosphere, therefore at least comprise silicon atom and nitrogen-atoms in described precursor material layer 206 material, in described precursor material layer 206 material, also comprise hydrogen atom.Concrete, containing chemical bonds such as Si-H, Si-N or Si-N-H in the precursor material layer 206 of formation, these chemical bonds are in follow-up processing procedure, and nitrogen-atoms can by O atomic substitutions, make afore mentioned chemical key replace by O-Si-O or Si-O, formation material is SiO
2second dielectric layer.
In other embodiments, when substrate comprises graphics intensive district (dense) and figure rarefaction (ISO), the first groove is formed in the substrate in graphics intensive district, in the substrate of figure rarefaction, form the second groove, and the size of the first groove is less than the second groove simultaneously; So, after adopting mobility chemical vapor deposition method to form the precursor material layer of filling completely the first groove, size due to the first groove is less than the second groove, and the second groove is not filled full yet, then adopts high vertical wide dielectric material of filling full second groove than chemical vapor deposition method formation.
Please refer to Fig. 6, first annealing in process is carried out to described precursor material layer 206 (please refer to Fig. 5), precursor material layer 206 is converted into first medium layer 207, and containing nitrogen-atoms in described first medium layer 207 material, and described nitrogen-atoms has the first atomic quantity.
Containing silicon atom, nitrogen-atoms and oxygen atom in described first medium layer 207 material.Described first annealing in process, carrying out containing under oxygen atmosphere, such as, passes into O in the first annealing in process chamber
3, O
2or H
2one or more gases in O steam.
Under the first annealing in process effect, Si-H key in precursor material layer 206, Si-N key, Si-N-H key rupture, and enter in precursor material layer 206 containing the O atom in oxygen atmosphere, the Si key ruptured, N key and H key are combined with the O atom of surrounding and form new chemical bond, as Si-O-H key and N-O-H key, thus make the materials from oxidizing of precursor material layer 206, change precursor material layer 206 into first medium layer 207, in the material of described first medium layer 207, comprise Si-O key, O-Si-O key, Si-O-H key, Si-H key and N-O-H key.
Due to precursor material layer 206 surface be at first with the region of O atomic contacts, if too high in the starting stage annealing temperature of the first annealing in process, so the material of precursor material layer 206 surf zone can transform fast under the condition of high temperature, cause the compactness of precursor material layer 206 surf zone material good, the difficulty that O atom arrives precursor material layer 206 bottom section increases.
For this reason, in the present embodiment, the anneal duration of the first annealing in process comprises continuous print first duration, the second duration and the 3rd duration, wherein, annealing temperature in first duration is the first temperature, annealing temperature in second duration is by the first temperature increment to the second temperature, and the annealing temperature in the 3rd duration is the second temperature, and the first temperature is less than the second temperature.Wherein, the first duration and the 3rd duration are zero or non-zero duration.
Because the starting stage (namely in the first duration) in the first annealing in process has lower annealing temperature, avoid and that cause harmful effect too high due to precursor material layer 206 surface soundness, O atom is contacted with precursor material layer 206 bottom section comparatively fully, improves the quality of the first medium layer 207 formed.
Concrete, described first temperature is 200 degree to 450 degree, and described second temperature is 550 degree to 650 degree, and described incremental manner is: linear formula increases progressively, parabolic increases progressively or exponential function formula increases progressively.
Please refer to Fig. 7, remove the first medium layer 207 higher than patterned mask layer 203 (please refer to Fig. 6) surface; Remove described patterned mask layer 203.
Adopt CMP (Chemical Mechanical Polishing) process removal higher than the first medium layer 207 on patterned mask layer 203 surface, remaining first medium layer 207 top surface is flushed with patterned mask layer 203 top surface.
Wet-etching technology etching is adopted to remove described patterned mask layer 203, as a specific embodiment, the etch liquids of described wet-etching technology is hot phosphoric acid solution, wherein, the mass percent of phosphoric acid is 65% to 85%, and solution temperature is 120 degree to 200 degree.
Please refer to Fig. 8, employing oxygen atom replaces the nitrogen-atoms in described first medium layer 207 (please refer to Fig. 7) material, first medium layer 207 is converted into second dielectric layer 208, in described second dielectric layer 208 material, nitrogen-atoms has the second atomic quantity, and the second atomic quantity is less than the first atomic quantity.
Although when experience the first annealing in process, the Si-N key of precursor material layer by layer in 206 (please refer to Fig. 5), fracture to a certain degree can be there is in Si-N-H key, reconfigure and form Si-O key, Si-O-H key, Si-H key and N-O-H key, but owing to being subject to the impact of the factors such as the first annealing in process annealing temperature, the ability of oxygen atom displacement nitrogen-atoms is still limited, nitrogen atom content in first medium layer 207 material formed is still higher, namely, the content of Si-N key and Si-N-H key is still higher, the existence of described Si-N key and Si-H-N key, the material property of first medium layer 207 can be caused poor, such as, the density of first medium layer 207 is poor, quality is softer, directly etching processing is carried out back to first medium layer 207 if follow-up, etching processing then can be caused back different to the etch rate in each region of first medium layer 207, cause back first medium layer 207 surface irregularity after etching, thickness of dielectric layers uniformity between the grid affecting follow-up formation.
For this reason, the present embodiment is after formation first medium layer 207, also comprise step, adopt the nitrogen-atoms in oxygen atom displacement first medium layer 207 material, first medium layer 207 is converted into second dielectric layer 208, in described second dielectric layer 208 material, nitrogen-atoms has the second atomic quantity, and the second atomic quantity is less than the first atomic quantity.That is, the Si-N key in second dielectric layer 208 material and the quantity of Si-N-H key decrease, thus improve the material property of second dielectric layer 208, improve second dielectric layer 208 density and hardness.
In the present embodiment, the method adopting oxygen atom to replace nitrogen-atoms in first medium layer 207 material is: adopt oxygen containing deionized water to carry out immersion treatment 209 to described first medium layer 207, can diffuse in first medium layer 207 containing the oxonium ion in oxygen deionized water, binding ability between oxonium ion and silicon ion is stronger than the binding ability between Nitrogen ion and silicon ion, therefore when oxonium ion diffuses into after in first medium layer 207, Si-N key and Si-N-H bond fission, and oxonium ion and post-rift Si bond are closed and are formed Si-O key or O-Si-O key, be second dielectric layer 208 material by first medium layer 207 material converting, thus make nitrogen atom content in second dielectric layer 208 material fewer than nitrogen atom content in first medium layer 207 material, the quantity of the Si-N key in second dielectric layer 208 material or Si-N-H key is reduced greatly, improve the performance of second dielectric layer 208 material.
In immersion treatment 209 process, first medium layer 207 is completely coated by oxygen containing deionized water, and oxygen containing deionized water diffuses into first medium layer 207 everywhere from first medium layer 207 surface, thus realizes oxygen atom displacement nitrogen-atoms faster.
Because ozone ion activity is in deionized water higher, therefore in oxygen containing deionized water described in the present embodiment, oxygen element is ozone ion.
If the mass percent of ozone ion is too low, then the activity containing oxygen deionized water is lower, and the energy of oxygen atom displacement nitrogen-atoms is low; And the mass percent of ozone ion also can be subject to the restriction of ozone ion solid solubility in deionized water, when Quality Mgmt Dept's percentage of ozone ion reaches a certain amount of, ozone ion is difficult to continue to be dissolved in deionized water; Meanwhile, if the mass percent of ozone ion is too high, oxidation may be caused to the active area in substrate 200, affect the performance of active area.
Therefore, in the present embodiment, in oxygen containing deionized water, the mass percent of ozone ion is 5% to 25%.
If the duration of immersion treatment 209 is too short, then ozone ion diffuses into the limitation in first medium layer 207, and number of nitrogen atoms in second dielectric layer 208 material of formation can be caused still higher; If the duration of immersion treatment 209 is long, then first medium layer 207 produces deformation due to the effect of deionized water; If the temperature of immersion treatment 209 is too low, too low containing the ozone ion activity in oxygen deionized water, the difficulty diffused in first medium layer 207 is larger; If the temperature of immersion treatment 209 is too high, described high temperature can cause other harmful effects to first medium layer 207.
In the present embodiment, the duration of described immersion treatment 209 is 30min to 60min, and temperature during immersion treatment 209 is 50 degree to 80 degree.
The present embodiment carries out immersion treatment 209 again after carrying out chemical mechanical polish process to first medium layer 207, owing to eliminating the first medium layer 207 higher than patterned mask layer surface, the lower thickness of first medium layer 207, therefore the evolving path of ozone ion shortens, more ozone ions can arrive faster in first medium layer 207, improve effect and the efficiency of oxygen atom displacement nitrogen-atoms.
Please refer to Fig. 9, the second annealing in process 210 is carried out to described second dielectric layer 208.
Hydrogen atom in second dielectric layer 208, for dry second dielectric layer 208, is discharged by described second annealing in process 210, improves density and the hardness of second dielectric layer 208 further.
As a specific embodiment, the technological parameter of described second annealing in process 210 is: annealing temperature is 800 degree to 950 degree, and anneal duration is 20min to 40min.
In other embodiments, when adopt in the groove in figure rarefaction high vertical wide be formed with dielectric material than chemical vapor deposition method time, described second annealing in process is also for improving the performance of described dielectric material; And, employing high vertical wide form dielectric material than chemical vapor deposition method before, also precursor material layer is formed with in the groove of figure rarefaction, so aforesaid first annealing in process and plasma bombardment are also applicable to the precursor material layer in the groove of figure rarefaction, make the precursor material layer in the groove of figure rarefaction be converted into the high second dielectric layer of compactness high rigidity.
Please refer to Figure 10, plasma bombardment 211 is carried out to described second dielectric layer 208 surface.
Employing has high-octane Ions Bombardment second dielectric layer 208 surface, the compactness of second dielectric layer 208 surf zone is further enhanced, when follow-up when returning etching second dielectric layer 208, within the starting stage (namely etching second dielectric layer 208 surfacing) of returning etching technics, described etching technics improves the etch rate consistency in the surperficial each region of second dielectric layer 208.
As a specific embodiment, the technological parameter of described plasma bombardment 211 is: described plasma is formed by He, Ne, Xe, Kr or Ar gaseous plasmaization, He, Ne, Xe, Kr or Ar gas flow is 50sccm to 500sccm, low frequency RF power is 100 watts to 1500 watts, and HFRF power is 100 watts to 1500 watts.
After experience immersion treatment 209 and plasma bombardment 211, the performance of second dielectric layer 208 is significantly improved, and compactness and the hardness of second dielectric layer 208 are all improved.
Please refer to Figure 11, return the second dielectric layer 208 that etching removes segment thickness, make remaining second dielectric layer 208 top lower than floating boom conductive layer 202 top surface.
In the present embodiment, return the second dielectric layer 208 that etching removes segment thickness, expose the partial sidewall surface of floating boom conductive layer 202, with the overlapping area between the control gate conductive layer increasing floating boom conductive layer 202 and follow-up formation, improve the coupling efficiency of semiconductor structure, reduce the operating voltage of semiconductor structure, optimize the electric property of semiconductor structure.
The technique of described time etching is wet etching, and as a specific embodiment, the etch liquids of described wet etching is hydrofluoric acid solution, and wherein, the volume ratio of hydrofluoric acid and deionized water is 1:300 to 1:700.
In the present embodiment, owing to have employed oxygen atom displacement nitrogen-atoms, compared with first medium layer 207, Si-N key in second dielectric layer 208 material and Si-N-H key considerably reduce, and the quantity of Si-O key and O-Si-O key significantly increases, therefore, compared with first medium layer 207, density and the hardness of second dielectric layer 208 material are all significantly improved.When carrying out back etching processing to second dielectric layer 208, due to second dielectric layer 208 material density and hardness higher, return the etch rate of etching technics to each region of second dielectric layer 208 consistent, therefore after time etching technics completes, remaining second dielectric layer 208 surface has higher flatness, avoids the generation of uneven defect.
Please refer to Figure 12, form dielectric layer 212 between grid, the surperficial formation control grid conductive layer 213 of dielectric layer 212 between described grid at described floating boom conductive layer 202 top surface and sidewall surfaces, second dielectric layer 208 surface.
Between described grid, dielectric layer 212 is the insulating barrier between floating boom conductive layer 202 and control gate conductive layer 213.Between described grid, the material of dielectric layer 212 is one or more in silica or silicon nitride, and between described grid, dielectric layer 212 can be single layer structure also can be sandwich construction.
Between described grid, the formation process of dielectric layer 212 is chemical vapour deposition (CVD), thermal oxidation method or physical vapour deposition (PVD).
In the present embodiment, between described grid, dielectric layer 212 is sandwich construction, between described grid, dielectric layer 212 is the laminated construction (ONO:oxide-nitride-oxide) of oxide skin(coating), nitride layer and oxide skin(coating), between described grid, the thickness of dielectric layer 212 is 50 dust to 200 dusts, adopts chemical vapor deposition method to form dielectric layer 212 between described grid.
The material of described control gate conductive layer 213 is the polysilicon of polysilicon or doping, and the thickness of described control gate conductive layer 213 is 500 dust to 2000 dusts, adopts chemical vapour deposition (CVD) to form described control gate conductive layer 213.
In the present embodiment, after returning etching second dielectric layer 208, remaining second dielectric layer 208 surface flatness is high, and between the grid being therefore positioned at second dielectric layer 208 surface, the thickness evenness of dielectric layer 212 is good, thus improves the electric property of semiconductor structure.
Follow-up processing step comprises: dielectric layer 212, floating boom conductive layer 202 and tunneling medium layer 201 between graphical described control gate conductive layer 213, grid, forms grid structure.
To sum up, the technical scheme of the formation method of semiconductor structure provided by the invention has the following advantages:
First, adopt mobility chemical vapor deposition method to form the precursor material layer of filling full groove, annealing in process is carried out to described precursor material layer, precursor material layer is converted into first medium layer, containing nitrogen-atoms in first medium layer material, and nitrogen-atoms has the first atomic quantity; Adopt the nitrogen-atoms in atomic substitutions first medium layer material, first medium layer is converted into second dielectric layer, and in described second medium layer material, nitrogen-atoms has the second atomic quantity, and the second atomic quantity is less than the first atomic quantity.In first medium layer Si-N key and Si-N-H bond number amount more, and after adopting the nitrogen-atoms after oxygen atom in first medium layer, in the second dielectric layer formed, Si-N key and Si-N-H bond number amount significantly decrease, and the quantity of Si-O key and O-Si-O key obviously increases in second dielectric layer, compactness and the hardness of second dielectric layer are improved, improve the performance of the second dielectric layer formed, and then optimize the electric property of semiconductor structure.
Secondly, the method of oxygen atom displacement nitrogen-atoms is adopted to carry out immersion treatment for adopting oxygen containing deionized water to first medium layer, because when immersion treatment, first medium layer is enveloped by oxygen containing deionized water completely, oxonium ion can diffuse in first medium layer everywhere from first medium layer surface, thus improves effect and the efficiency of oxygen atom displacement nitrogen-atoms.
Further, the duration of described immersion treatment is 30min to 60min, ensures the regional diffused into containing the oxonium ion in oxygen deionized water in first medium layer; And temperature during immersion treatment is 50 degree to 80 degree, under described temperature conditions, in oxygen containing deionized water, the activity of oxonium ion is higher, to diffuse in first medium layer and the ability of displacement nitrogen-atoms is comparatively strong, makes oxygen atom replace the better effects if of nitrogen-atoms.
Again, substrate comprises substrate, is positioned at the tunneling medium layer of substrate surface and is positioned at the floating boom conductive layer on tunneling medium layer surface, after the second dielectric layer of returning etching removal segment thickness, the partial sidewall surface of floating boom conductive layer is exposed, overlapping area between floating boom conductive layer and control gate conductive layer is increased, improve the coupling efficiency of semiconductor structure, reduce the operating voltage of semiconductor structure.
Simultaneously, due to the compactness of second dielectric layer that formed after oxygen atom displacement nitrogen-atoms and hardness higher, when returning etching second dielectric layer, the etch rate of described time etching technics to each region of second dielectric layer is even, therefore return etching processing complete after remaining second dielectric layer surface flatness high, between the grid being positioned at remaining second dielectric layer surface, the thickness evenness of dielectric layer is good, thus improves reliability and the electric property of semiconductor structure.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Substrate is provided, in described substrate, is formed with groove;
Mobility chemical vapor deposition method is adopted to form the precursor material layer of filling full described groove;
Carry out annealing in process to described precursor material, precursor material layer is converted into first medium layer, containing nitrogen-atoms in described first medium layer material, and described nitrogen-atoms has the first atomic quantity;
Employing oxygen atom replaces the nitrogen-atoms in described first medium layer material, and first medium layer is converted into second dielectric layer, and in described second medium layer material, nitrogen-atoms has the second atomic quantity, and the second atomic quantity is less than the first atomic quantity.
2. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, at least comprise silicon atom and nitrogen-atoms in described precursor material layer material.
3. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the precursor material that described mobility chemical vapor deposition method adopts comprises one or more in three silica-based nitrogen, silane, disilane, methyl-monosilane, dimethylsilane, trimethyl silane, tetramethylsilane, tetraethoxysilane, triethoxysilane, octamethylcy-clotetrasiloxane, tetramethyl disiloxane, tetramethyl-ring tetrasiloxane, trimethylsilyl amine, dimethyl silanyl amine.
4. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, described mobility chemical vapor deposition method is carried out under nitrogenous atmosphere.
5. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the method adopting oxygen atom to replace the nitrogen-atoms of described first medium layer material is: adopt oxygen containing deionized water to carry out immersion treatment to described first medium layer.
6. the formation method of semiconductor structure as claimed in claim 5, it is characterized in that, the oxygen element in described oxygen containing deionized water is ozone ion.
7. the formation method of semiconductor structure as claimed in claim 6, it is characterized in that, in described oxygen containing deionized water, the mass percent of ozone ion is 5% to 25%.
8. the formation method of semiconductor structure as claimed in claim 7, it is characterized in that, the duration of described immersion treatment is 30min to 60min, and temperature during immersion treatment is 50 degree to 80 degree.
9. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, also comprise step: carry out plasma bombardment to described second dielectric layer surface.
10. the formation method of semiconductor structure as claimed in claim 9, it is characterized in that, the technological parameter of described plasma bombardment is: described plasma is formed by He, Ne, Xe, Kr or Ar gaseous plasmaization, He, Ne, Xe, Kr or Ar gas flow is 50sccm to 500sccm, low frequency RF power is 100 watts to 1500 watts, and HFRF power is 100 watts to 1500 watts.
The formation method of 11. semiconductor structures as claimed in claim 1, is characterized in that, described annealing in process is being carried out containing under oxygen atmosphere.
The formation method of 12. semiconductor structures as claimed in claim 1, it is characterized in that, the anneal duration of described annealing in process comprises continuous print first duration, the second duration and the 3rd duration, wherein, annealing temperature in first duration is the first temperature, annealing temperature in second duration is by the first temperature increment to the second temperature, and the annealing temperature in the 3rd duration is the second temperature.
The formation method of 13. semiconductor structures as claimed in claim 12, it is characterized in that, described first temperature is 200 degree to 450 degree, and described second temperature is 550 degree to 650 degree.
The formation method of 14. semiconductor structures as claimed in claim 1, is characterized in that, also comprise step: carry out the second annealing in process to described second dielectric layer; Return the second dielectric layer that etching removes segment thickness.
The formation method of 15. semiconductor structures as claimed in claim 14, it is characterized in that, the technological parameter of described second annealing in process is: annealing temperature is 800 degree to 950 degree, and anneal duration is 20min to 40min.
The formation method of 16. semiconductor structures as claimed in claim 14, it is characterized in that, described substrate comprises substrate, is positioned at the tunneling medium layer of substrate surface and is positioned at the floating boom conductive layer on tunneling medium layer surface.
The formation method of 17. semiconductor structures as claimed in claim 16, is characterized in that, returns the second dielectric layer that etching removes segment thickness, makes remaining second dielectric layer top lower than floating boom conductive layer top surface.
The formation method of 18. semiconductor structures as claimed in claim 17, is characterized in that, also comprise step: form dielectric layer between grid at described floating boom conductive layer top surface and sidewall surfaces, remaining second dielectric layer surface; Dielectric layer surface formation control grid conductive layer between described grid.
The formation method of 19. semiconductor structures as claimed in claim 16, it is characterized in that, the processing step forming described groove comprises: form patterned mask layer at described floating boom conductive layer surface; With described patterned mask layer for mask, etch the substrate of described floating boom conductive layer, tunneling medium layer and segment thickness, form groove.
The formation method of 20. semiconductor structures as claimed in claim 19, is characterized in that, after formation first medium layer, also comprises step: remove the first medium layer higher than patterned mask layer surface; Remove described patterned mask layer.
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| CN101521174A (en) * | 2008-02-25 | 2009-09-02 | 株式会社东芝 | Manufacturing method for semiconductor devices |
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| US20080064212A1 (en) * | 2006-08-25 | 2008-03-13 | Yoshihiro Ogawa | Method of manufacturing semiconductor device |
| CN101521174A (en) * | 2008-02-25 | 2009-09-02 | 株式会社东芝 | Manufacturing method for semiconductor devices |
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