CN106206448A - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN106206448A CN106206448A CN201510225547.6A CN201510225547A CN106206448A CN 106206448 A CN106206448 A CN 106206448A CN 201510225547 A CN201510225547 A CN 201510225547A CN 106206448 A CN106206448 A CN 106206448A
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Abstract
A kind of forming method of semiconductor structure, including: providing substrate, described substrate surface has fin and sealing coat, and the surface of described sealing coat is less than the top surface of described fin, and described sealing coat covers the partial sidewall surface of described fin；The first nitration case is formed at described insulation surface and the sidewall of described fin and top surface；Oxidation processing technique is used to form oxide layer on described first nitration case surface；The second nitration case is formed on described oxide layer surface；Grid structure is formed on described second nitration case surface.The performance of the semiconductor structure formed improves, and formation process simplifies.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the forming method of a kind of semiconductor structure.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type: analog circuit,
Digital circuit and D/A hybrid circuit, an important kind during wherein memory device is digital circuit.Closely
Nian Lai, in memory device, the development of flash memories (flash memory) is the rapidest.
The information being mainly characterized by the case of not powered keeping storing for a long time of flash memories, because of
This is widely used in various urgent need data to be stored and will not disappear because of power interruptions, there is a need to repeat
The memorizer of read-write data.And, flash memory has integrated level height, access speed is fast, be prone to erasing and weight
The advantage such as write, thus be widely used in the multinomial field such as MEMS, Automated condtrol.
Therefore, how to promote the performance of flash memory and reduce cost and become an important topic.
Flash memories, according to the difference of array structure, mainly divides NAND gate flash memories (NAND
And nor gate flash memories (NOR Flash) Flash).Along with the development of high density flash memory technology, respectively
The performance of class accompanied electronic equipment is improved, such as using flash memory as digital camera, notebook computer
Or the memory device in the electronic equipment such as panel computer.Therefore, reduce the size of flash cell, and with this
The cost of reduction flash memories is one of direction of technology development.
But, along with size reduction, the density of semiconductor device improve, the technique forming flash memories
Difficulty increases, and the hydraulic performance decline of the flash memories formed, reliability reduce.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor structure, improves half formed
The performance of conductor structure, Simplified flowsheet, improves the work efficiency of semiconductor structure.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including: provide
Substrate, described substrate surface has fin and sealing coat, and the surface of described sealing coat is less than described fin
Top surface, and the partial sidewall surface of the described sealing coat described fin of covering；Described insulation surface,
And the sidewall of described fin and top surface form the first nitration case；Use oxidation processing technique described
First nitration case surface forms oxide layer；The second nitration case is formed on described oxide layer surface；At the second nitrogen
The part surface changing layer forms grid structure, and described grid structure is covered in sidewall and the top of fin, and
Described grid structure is across described fin.
Optionally, the material of described first nitration case is silicon nitride.
Optionally, the formation process of described first nitration case is atom layer deposition process.
Optionally, the thickness of described first nitration case is 20 angstroms～200 angstroms.
Optionally, described oxidation processing technique is that steam generates technique, decoupled plasma oxidation work in situ
Skill or free-radical oxidation technique.
Optionally, described oxidation processing technique makes part the first nitration case being positioned at surface be converted into oxide layer.
Optionally, before described oxidation processing technique, the thickness of described first nitration case is the first thickness,
Part the first nitride thickness being converted into oxide layer is the second thickness, and described second thickness is described first
The 60%～98% of thickness.
Optionally, the material of described oxide layer is silicon oxide.
Optionally, the material of described second nitration case is silicon nitride.
Optionally, the technique forming described second nitration case includes nitrogenation treatment technology.
Optionally, described nitrogenation treatment technology is decoupled plasma nitridation process.
Optionally, described nitrogenation treatment technology makes the portion of oxide layer being positioned at surface be converted into the second nitration case.
Optionally, before described plasma nitridation processes, the thickness of described oxide layer is the 3rd
Thickness, the partial oxidation layer thickness being converted into the second nitration case is the 4th thickness, and described 4th thickness is institute
State the 5%～30% of the 3rd thickness.
Optionally, the technique forming described second nitration case also includes: after described nitrogenation treatment technology,
Carry out annealing process.
Optionally, described grid structure includes the first grid layer being positioned at part the second nitration case surface.
Optionally, the material of described first grid layer is polysilicon.
Optionally, described grid structure also includes: be positioned at the interlayer dielectric layer on first grid layer surface；Position
Second grid layer in interlayer dielectric layer surface.
Optionally, the one during the material of described interlayer dielectric layer is silicon oxide, silicon nitride, silicon oxynitride
Or multiple combination；The material of described second grid layer is polysilicon.
Optionally, also include: after formation of the gate structure, with described grid structure as mask, etching
Described second nitration case, oxide layer and the first nitration case, until exposing described sealing coat and fin
Sidewall and top surface till.
Compared with prior art, technical scheme has the advantage that
In the forming method of the present invention, before forming oxide layer, at insulation surface and described fin
The sidewall in portion and top surface form the first nitration case, owing to passing through formation process, it is possible to make described first
Nitration case has good step covering power, and the first nitration case formed can closely be covered in fin
Sidewall and top surface so that the stable performance of the semiconductor structure formed, leakage current reduce.And
And, by regulation formation process, it is possible to make the thickness of the first nitration case and the concentration of Nitrogen ion be distributed more
For uniformly, the most described first nitration case is subsequently formed for stopping that dopant ion in fin diffuses into
Ability in grid structure is higher and stable.After forming described oxide layer, on described oxide layer surface
Forming the second nitration case, the second nitration case formed is less than phase with the electrical thickness of described first nitration case
Oxidated layer thickness with physical thickness such that it is able to make the first nitration case, oxide layer and the second nitration case
Total electrical thickness reduces, and is conducive to reducing tunneling voltage, improves operating current, and what raising was formed partly leads
The performance of body structure.Additionally, due to formed described first nitration case before forming oxide layer, thus keep away
Exempt from after oxide layer surface forms the second nitration case, used extra rapid thermal anneal process to form oxygen
Change the nitration case step between layer and fin, it is possible to avoid because the hot environment of rapid thermal anneal process is to fin
Portion causes damage.
Further, the material of described first nitration case is silicon nitride, the formation process of described first nitration case
For atom layer deposition process.The density of described silicon nitride material is more than the density of silica material, therefore institute
State the first nitration case and can be used in stopping the dopant ion tunnelling in fin, thus the doping in avoiding fin
Ion is through oxide layer and enters in the grid structure being subsequently formed, thus ensure that formed quasiconductor
The stable performance of structure.And the first nitride thickness that described atom layer deposition process is formed is relatively thin, and
Stepcoverage power is higher, it is possible to make described first nitration case closely be covered in sidewall and the top table of fin
Face, the electrical thickness of described first nitration case is uniform, and described first nitration case is to the dopant ion in fin
Blocking capability uniform.
Further, the thickness of described first nitration case is 20 angstroms～200 angstroms.The thickness of described first nitration case
Should not be the thinnest, otherwise not enough to the blocking capability of dopant ion.The thickness of described first nitration case is the most unsuitable
Blocked up, the electrical thickness of the most described first nitration case is blocked up, easy first nitration case, oxide layer and
The tunneling voltage of nitride layer, causes the power consumption of semiconductor structure to increase, and operating current reduces.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the formation of the storage grid structure of the NAND gate flash memories of the embodiment of the present invention
The cross-sectional view of process；
Fig. 6 to Figure 11 is the cross-section structure signal of the forming process of the semiconductor structure of the embodiment of the present invention
Figure.
Detailed description of the invention
As stated in the Background Art, along with size reduction, the density of semiconductor device improve, form flash memory and deposit
The technology difficulty of reservoir increases, the hydraulic performance decline of the flash memories formed.
In order to improve the device density of NAND gate flash memory, the storage grid of described NAND gate flash memories
Electrode structure is formed at fin portion surface, it is possible to while reducing device size, improving device density, it is ensured that
Channel region tool bottom grid structure is wide enough, to ensure sufficiently large operating current.Fig. 1 to Fig. 5
It it is the cross-section structure of the forming process of the storage grid structure of the NAND gate flash memories of the embodiment of the present invention
Schematic diagram.
Refer to Fig. 1, it is provided that substrate 100, described substrate 100 surface has fin 101 and sealing coat 102,
The surface of described sealing coat 102 is less than the top surface of described fin 101, and described sealing coat 102 covers
Cover the partial sidewall surface of described fin 101.
Refer to Fig. 2, use oxidation technology at the sidewall of described fin 101 and top surface and sealing coat
102 surfaces form oxide layer 103.
Refer to Fig. 3, use nitrogenation treatment technology the surface of described oxide layer 103 to be processed, in institute
State oxide layer 103 surface and form the first nitration case 104.
Refer to Fig. 4, after described nitrogenation treatment technology, use Rapid Thermal nitrogen oxidation annealing process at fin
The second nitration case 105 is formed between portion 101 and oxide layer 103.
Refer to Fig. 5, form grid structure 106 on described first nitration case 104 surface；With grid structure
106 is mask, etches described first nitration case 104 and oxide layer 103, until exposing sealing coat 102
Till surface.
Wherein, described oxide layer 103 as the tunnel oxide between grid structure 106 and fin 101,
For regulating storage or the erasing voltage of grid memory element.But, along with the size reduction of flash memories,
The thickness of described oxide layer 103 reduces the most accordingly, and the dopant ion in fin 101 easily propagates through described oxygen
Change layer 103 and enter grid structure 106, cause the reliability of flash memory size device to reduce.
Find through research, by forming the second nitration case between described oxide layer 103 and fin 101
105, form the second nitration case 105 on described oxide layer 103 surface, it is possible to improve described flash memories
Performance.Described second nitration case 105 is the finest and close, it is possible to before oxide layer 103 and fin 101
Dopant ion within stopping fin 101 enters grid structure 106 through described oxide layer 103, thus
The reliability making flash memories improves.On the other hand, by nitrogenation treatment technology, make described oxide layer
Surface portion be converted into the first nitration case 104, the most described first nitration case 104 is compared to same thickness
Oxide layer 103 has less electrical thickness so that described oxide layer the 103, first nitration case 104 and
The tunneling voltage of dioxide layer 105 reduces, and advantageously reduces the power consumption of flash memories, improves flash memory and deposits
The performance of reservoir.
Owing to described grid structure 106 is formed at fin 101 surface, and described second nitration case 105, oxygen
Change layer 103 and the first nitration case 104 are also respectively formed in sidewall and the top surface of described fin 101,
It is therefore desirable to described second nitration case 105, oxide layer 103 and the first nitration case 104 have good rank
Ladder covering power.But, owing to described second nitration case 105 is existed by Rapid Thermal nitrogen oxidation annealing process
Formed between oxide layer 103 and fin 101, i.e. promote oxygen and nitrogen to penetrate into the first nitrogen by thermal drivers
Change layer 104 and oxide layer 103, and react with the material on fin 101 surface and form the second nitration case
105, the thickness evenness of the second nitration case 105 formed is difficult to control to, and described Rapid Thermal nitrogen oxygen
Fin or substrate are easily caused damage by the hot environment of annealing technique.
In order to solve the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure.Wherein, exist
Formed before oxide layer, form first at insulation surface and the sidewall of described fin and top surface
Nitration case, owing to passing through formation process, it is possible to makes described first nitration case have good step covering power,
The first nitration case formed can closely be covered in sidewall and the top surface of fin so that is formed
The stable performance of semiconductor structure, leakage current reduces.And, by regulation formation process, it is possible to make
The thickness of the first nitration case and the concentration of Nitrogen ion more uniformly spread, the most described first nitration case for
Stop that the dopant ion in fin diffuses into the ability in the grid structure being subsequently formed higher and stable.
Being formed after described oxide layer, it is that described oxide layer surface forms the second nitration case, the formed
The electrical thickness of nitride layer and described first nitration case is less than the oxidated layer thickness of same physical thickness, from
And total electrical thickness of the first nitration case, oxide layer and the second nitration case can be made to reduce, be conducive to reducing
Tunneling voltage, improves operating current, improves the performance of the semiconductor structure formed.Additionally, due to
Form described first nitration case before forming oxide layer, thus avoid and form the second nitrogen on oxide layer surface
After changing layer, extra rapid thermal anneal process is used to form the nitration case step between oxide layer and fin,
It can be avoided that because fin is caused damage by the hot environment of rapid thermal anneal process.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Fig. 6 to Figure 11 is the cross-section structure signal of the forming process of the semiconductor structure of the embodiment of the present invention
Figure.
Refer to Fig. 6, it is provided that substrate 200, described substrate 200 surface has fin 201 and sealing coat 202,
The surface of described sealing coat 202 is less than the top surface of described fin 201, and described sealing coat 202 covers
Cover the partial sidewall surface of described fin 201.
In the present embodiment, the semiconductor structure formed is the grid structure of flash memory cell.And,
In order to make device density raising, device dimensions shrink, described grid structure is formed at fin 201 surface,
Ensureing in the case of the size reduction of grid structure with this, the channel region formed in fin 201 has foot
Enough width, make the size reduction of grid structure.
In one embodiment, described substrate 200 and fin 201 are formed by etching semiconductor substrate.Institute
The formation process stating fin 201 includes: provide semiconductor base；Part table at described semiconductor base
Face forms patterned first mask layer, and described first mask layer covers the correspondence needing to form fin 201
Region；With described first mask layer as mask, etch described semiconductor base, at described semiconductor base
The some grooves of interior formation, the semiconductor base between adjacent trenches forms fin 201, is positioned at described fin
Semiconductor base bottom 201 forms substrate 200；After etching described substrate, remove described first and cover
Film layer.
Described semiconductor base is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI)
Substrate, germanium on insulator (GOI) substrate.
The material of described first mask layer is in silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon
Plant or multiple；The formation process of described mask layer includes: form mask material film at semiconductor substrate surface；
Photoetching process is used to form patterned photoresist layer on described mask material film surface；With described graphically
Photoresist layer be mask, etch described mask material film till exposing semiconductor substrate surface,
Form the first mask layer.After forming fin 201, the technique removing mask layer is wet-etching technology
Or cineration technics.
In order to reduce the size of described fin 201, described first mask layer can also use multiple graphical
Masking process is formed, and described multiple graphical masking process includes: self-alignment duplex pattern (Self-aligned
Double Patterned, SaDP) technique, autoregistration triple graphical (Self-aligned Triple Patterned)
Technique or autoregistration quadruple are graphical (Self-aligned Double Double Patterned, SaDDP)
Technique.
The technique of described etching substrate is anisotropic dry etch process, fin 201 side formed
Wall energy is enough perpendicular to substrate 200 surface or tilts relative to substrate 200 surface.In the present embodiment,
The sidewall of described fin 201 tilts relative to substrate 200 surface, the top chi of the fin 201 formed
Very little less than bottom size.The sloped sidewall of described fin 201 is conducive to when being subsequently formed grid structure,
The gate layer material of fin 201 sidewall surfaces is performed etching, it is possible to the grid structure that guarantee is formed
Pattern is good, size is accurate, makes the stable performance of formed fin formula field effect transistor.
In another embodiment, described semiconductor base can also be semiconductor-on-insulator substrate, described
Semiconductor-on-insulator substrate includes: substrate, is positioned at the insulating barrier of substrate surface, is positioned at surface of insulating layer
Semiconductor layer.The formation process of described fin 201 includes: form the first mask in semiconductor layer surface
Layer；With described first mask layer as mask, etching semiconductor layer till exposing surface of insulating layer,
Forming the fin 201 being positioned on insulating barrier, described substrate forms substrate 200, and described insulating barrier is isolation
The sealing coat of described fin 201.
In other embodiments, described fin 201 is formed at partly leading of semiconductor substrate surface by etching
Body layer is formed, and described semiconductor layer uses selective epitaxial depositing operation to be formed at described semiconductor base table
Face.Described semiconductor base be silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate,
Germanium substrate on insulator, glass substrate or III-V substrate, such as gallium nitride substrate or GaAs
Substrate etc.；The selection of described semiconductor base is unrestricted, it is possible to chooses and is suitable to process requirements or is prone to collection
The semiconductor base become.The material of described semiconductor layer is silicon, germanium, carborundum or SiGe, is formed
The material of the first fin 210 and the second fin 220 is unrestricted, it is possible to meet specific process requirements,
And the thickness of described semiconductor layer can be controlled by epitaxy technique, thus control formed first
Fin 210 and the height of the second fin 220.
Described sealing coat 202, for isolating adjacent fin 201, makes the active area being formed in fin 201
Mutually isolated.The material of described fin 201 is silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric material
One or more combinations in material, ultralow K dielectric material；In the present embodiment, the material of described fin 201
Material is silicon oxide.The formation process of described fin 201 includes: at described substrate 200 and fin 201
Surface forms isolating membrane；Planarize described isolating membrane, until exposing the top surface of described fin 201
Till；After planarizing described isolating membrane, it is etched back to described isolating membrane, and exposes described fin 201
Partial sidewall surface, form described sealing coat 202.
Wherein, the formation process of described isolating membrane is chemical vapor deposition method or physical gas-phase deposition,
Such as fluid chemistry vapour deposition (FCVD, Flowable Chemical Vapor Deposition) technique,
Plasma enhanced chemical vapor deposition technique.Described flatening process is CMP process.This
In embodiment, the formation process of described isolating membrane is fluid chemistry gas-phase deposition, uses described fluid
The isolating membrane that chemical vapor deposition method is formed is prone to be packed in the groove between fin 201, it is possible to make
The isolating membrane even compact formed, sealing coat 202 isolation performance formed is good.
In one embodiment, in order to avoid damage is caused in fin 201 top by described chemically mechanical polishing,
Polishing stop layer, institute can also be formed at substrate 200 and fin 201 surface before forming isolating membrane
The material stating polishing stop layer is different from the material of isolating membrane, when described CMP process exposes
After described polishing stop layer, described polishing stop layer was carried out polishing or wet-etching technology, with cruelly
Expose the top surface of fin 201.
The described technique that is etched back to is anisotropic dry etch process, due to described flatening process make every
Smooth from the surface of film, after being therefore etched back to described in process, the surface of described sealing coat 202 is smooth.
After forming described sealing coat 202, before grid structure continuous after its formation, to fin 201
Carry out ion implantation technology.In one embodiment, described ion implantation technology is for described fin 201
Carry out well region injection, in order in fin 201, form well region；In another embodiment, additionally it is possible in institute
After stating well region injection, described fin 201 is carried out threshold value regulation and injects, with to the grid knot formed
The threshold voltage of structure is adjusted.
Refer to Fig. 7, at described sealing coat 202 surface and the sidewall of described fin 201 and top table
Face forms the first nitration case 203.
In the present embodiment, the grid structure formed as the grid structure of flash memory cell, and
Between described grid structure and fin 201, need to form oxide layer as tunnel oxide.But, with
The size reduction of grid structure, the thickness of described oxide layer also scaled-back, in causing fin 201
Dopant ion easily propagates through described oxide layer and enters grid structure, causes the property of formed semiconductor structure
Can be unstable.
Therefore, formed before described oxide layer, needing at the sidewall of described fin 201 and top surface
Form the first nitration case 203, owing to the density of described first nitration case 203 is bigger such that it is able to stop fin
Dopant ion in portion 201 diffuses in the oxide layer being subsequently formed, it is to avoid described dopant ion enters
The grid structure being subsequently formed, makes the stable performance of formed semiconductor structure.
In the present embodiment, the material of described first nitration case 203 is silicon nitride.Described silicon nitride close
Degree is more than silicon oxide, it is possible to prevent the dopant ion in fin 201 from spreading；And, in same thickness
In the case of, the electrical thickness of nitration case is less than the electrical thickness of silicon oxide, therefore, described first nitration case
203 can also have less electrical thickness, then tunnelling electricity while having sufficiently large blocking capability
Stream is relatively big, is conducive to improving the work efficiency of flash memory cell.
The formation process of described first nitration case 203 is atom layer deposition process.Described ald work
Skill has good gradient coating performance, it is possible to make the first formed nitration case 203 closely be covered in
The sidewall of fin 201 and top surface, be not likely to produce between described first nitration case 203 and fin 201
Defect or gap, it is possible to avoid producing leakage current.And, use the first of atom layer deposition process formation
Nitration case 203 thickness is the most easily-controllable, beneficially the tunnel between fin 201 and the grid structure being subsequently formed
Wear electric current more stable, improve the reliability and stability of formed semiconductor structure.At the present embodiment
In, the parameter of the atom layer deposition process forming described first nitration case 203 includes: temperature is 300 DEG C
～600 DEG C, pressure is 0.1 torr～30 torr, and gas includes silicon source gas and nitrogen source gas, and silicon source gas includes
SiH4、Si2H6、Si2H4Cl2In one or more, nitrogen source gas includes NH3。
The thickness of described first nitration case 203 is the first thickness.Owing to follow-up needs uses oxidation technology pair
Described first nitration case 203 aoxidizes, and makes part the first nitration case 203 be converted into oxide layer, therefore
Described first thickness is unsuitable too small, otherwise will be unable to make the oxide layer being subsequently formed reach adequate thickness；So
And, described first thickness is also unsuitable blocked up, otherwise not only results in the size of formed semiconductor structure
Becoming big, also resulting in the electrical thickness between fin 201 and the grid structure being subsequently formed increases, institute's shape
The performance of the semiconductor structure become is the best.In the present embodiment, described first thickness is 20 angstroms～200 angstroms.
Refer to Fig. 8, use oxidation processing technique to form oxide layer on described first nitration case 203 surface
204。
Described oxide layer 204 as the tunnel oxide between fin 201 and the grid structure being subsequently formed,
Electric charge migrates between described grid structure and fin 201, with realize the erasing of data, storage or
Programming.In the present embodiment, the material of described oxide layer 204 is silicon oxide.
Described oxide layer 204 is by carrying out oxidation processes formation to part the first nitration case 203；By right
Described first nitration case 203 carries out oxidation processes, makes described first nitration case 203 be positioned at the part on surface
It is oxidized into oxide layer 204；In described oxidation technology, oxonium ion is the most excellent with the silicon ion in silicon nitride
First react to form oxide layer 204；And Nitrogen ion separates out to the direction on fin 201 surface so that position
In the first nitration case 203 between oxide layer 204 and fin 201, Nitrogen ion concentration improves, and described the
The density of one nitration case 203 increases, and is more beneficial in described first nitration case 203 stops fin 201
Dopant ion spreads.
And, oxide layer 204 density using oxidation processing technique to be formed is relatively big, is not easily formed electric charge and falls into
Trap, during using described oxide layer 204 as tunnel oxide, it is possible to make formed semiconductor structure performance
More stable.Additionally, employing oxidation technology is when the first nitration case 203 surface forms oxide layer 204, institute
State oxide layer to combine closely with the first nitration case 203, be difficult in the first nitration case 203 and oxide layer
Defect is formed between 204.
Described oxidation processing technique is that steam generates (In-Situ Steam Generation is called for short ISSG) in situ
Technique, decoupled plasma oxidation (Decoupled Plasma Oxidation, be called for short DPO) technique or
Free-radical oxidation (Radical Oxidation) technique.
In the present embodiment, described oxidation processing technique is that steam generates technique in situ；Described original position steam
The parameter generating technique includes: temperature is 700 DEG C～1200 DEG C, and gas includes hydrogen and oxygen, oxygen stream
Amount is 1slm～50slm, and hydrogen flowing quantity is 1slm～10slm, and the time is 20 seconds～10 minutes.Use institute
State steam in situ and generate oxide layer 204 dense uniform that technique is formed, and thickness is the most easily-controllable, is conducive to
The tunnelling current making formed flash memory cell is stable, the semiconductor structure stable performance formed.
In the present embodiment, before described oxidation processing technique, the thickness of described first nitration case 203
Being the first thickness, part the first nitration case 203 thickness being converted into oxide layer 204 is the second thickness, institute
Stating the second thickness is the 60%～98% of described first thickness；It is not converted into the first nitration case of oxide layer 204
203 for stopping that the dopant ion in fin 201 spreads.
The thickness of described oxide layer 204 is the 3rd thickness.Owing to follow-up needs uses nitriding process to described
Oxide layer 204 aoxidizes, and makes portion of oxide layer 204 be converted into the second nitration case, and the most described 3rd
Thickness is unsuitable too small, otherwise will be unable to make the second nitration case being subsequently formed reach adequate thickness；But,
Described 3rd thickness is also unsuitable blocked up, the most not only makes the physical thickness of oxide layer 204 increase, also can lead
Cause electrical thickness increases, and the performance easily causing formed semiconductor structure is the best.In the present embodiment,
The thickness of institute's oxide layer 204 is 1 nanometer～20 nanometers.
Refer to Fig. 9, at described oxide layer 204 surface the second nitration case 205.
In the present embodiment, the material of described second nitration case 205 is silicon nitride.Described second nitration case
For regulating the electrical thickness between described fin 201 and the grid structure being subsequently formed.Same thickness
Silicon nitride electrical thickness is less than the electrical thickness of silicon oxide, therefore, by carrying out described oxide layer 204
Nitrogen treatment also forms described second nitration case 205, it is possible to described fin 201 and the grid knot being subsequently formed
Electrical thickness between structure reduces, and is conducive to improving tunnelling current, thus improves formed semiconductor junction
The work efficiency of structure.
The technique forming described second nitration case 205 includes nitrogenation treatment technology.By to described oxide layer
204 carry out nitrogen treatment, and the partial nitridation making described oxide layer 204 be positioned at surface becomes the second nitration case
205；Nitriding process is used to form the second nitration case 205 on oxide layer 204 surface, it is possible to make to be formed
Second nitration case 205 is combined closely with described oxide layer 204, is difficult in the first nitration case 203 and oxidation
Form defect between layer 204, thus be not easily formed charge trap, it is possible to make formed semiconductor structure
Reliability improve.
In the present embodiment, described nitrogenation treatment technology is decoupled plasma nitridation (Decoupled
Plasma Nitridation, is called for short DPO) technique.The second nitridation that described decoupled plasma nitridation is formed
Layer 205 thickness are uniform, and thickness is prone to pass through technology controlling and process, it is possible to make fin 201 and be subsequently formed
Tunnelling current between grid structure is more stable.Form the technological parameter bag of described second nitration case 205
Including: power is 1000 watts～4000 watts, pressure is 10 millitorrs～50 millitorrs, and gas includes nitrogen, nitrogen
Flow be 50sccm～500sccm.
Before described plasma nitridation processes, the thickness of described oxide layer 204 is the 3rd thickness,
Portion of oxide layer 204 thickness being converted into the second nitration case 205 is the 4th thickness, and described 4th thickness is
The 5%～30% of described 3rd thickness.In the present embodiment, described second nitration case 205 thickness is 0.5 to receive
Rice～5 nanometers.
Owing to described second nitration case 205 is used for regulating electrical thickness, therefore, described second nitration case 205
Thickness unsuitable blocked up, the thickness that otherwise will result in oxide layer 204 is the thinnest, easily causes control quasiconductor
The tunneling voltage of device is too small；The thickness of described second nitration case 205 also should not be the thinnest, otherwise reduces electricity
The degree learning thickness is not enough.
In one embodiment, the technique forming described second nitration case 205 also includes: at described nitridation
After science and engineering skill, carry out annealing process.Described annealing process is used for making Nitrogen ion at described second nitration case
Being more evenly distributed in 205.The parameter of the annealing process forming described second nitration case 205 includes: temperature
Being 1000 DEG C～1100 DEG C, pressure is 0.5 torr～5 torr；Time is 10 seconds～120 seconds, and gas includes nitrogen,
The flow of nitrogen is 5slm～50slm.
Refer to Figure 10, the part surface at the second nitration case 205 forms grid structure, and described grid is tied
Structure is covered in sidewall and the top of fin 201, and described grid structure is across described fin 201.
In the present embodiment, described grid structure is the grid structure of flash memory cell.Described grid structure
Including the first grid layer 206 being positioned at part the second nitration case 205 surface；Described first grid layer 206
Material is polysilicon；Described first grid layer 206 can be as the selection grid of flash memory cell or control
Grid.
The forming step of described first grid layer 206 includes: formed on described second nitration case 205 surface
First grid film；Described first grid film surface is planarized；After described flatening process,
Part surface at described first grid film forms the second mask layer of patterned layer；With described second mask
Layer is mask, etches described first grid film, until exposing described second nitration case 205 surface, shape
Become first grid layer 206.
Wherein, the formation process of described first grid film is chemical vapor deposition method, physical vapour deposition (PVD)
Technique or atom layer deposition process；The flatening process carrying out described first grid film is that chemical machinery is thrown
Light technique；The material of described second mask layer is photoresist layer material or amorphous carbon；Forming the first grid
After the layer of pole, it is possible to retain described second mask layer；The technique etching described first grid film is each to different
The dry etch process of property, the sidewall of the first grid layer 206 formed is perpendicular to substrate 200 surface.
In one embodiment, described grid structure also includes: be positioned at the inter-level dielectric on first grid layer surface
Layer；It is positioned at the second grid layer on interlayer dielectric layer surface.Wherein, the material of described interlayer dielectric layer is oxygen
One or more combinations in SiClx, silicon nitride, silicon oxynitride；In one embodiment, described interlayer is situated between
Matter layer is the combinative structure of oxide-nitride-oxide (ONO)；Described interlayer dielectric layer is used for conduct
Electricity isolated layer between first grid layer and second grid layer.The material of described second grid layer is polysilicon；
Described second grid layer as the selection grid of flash memory cell or control gate, and described second grid layer with
The function of first grid layer is different.
Refer to Figure 11, after formation of the gate structure, with described grid structure as mask, etching is described
Second nitration case 205, oxide layer 204 and the first nitration case 203, until expose described sealing coat 202,
And till the sidewall of fin 201 and top surface.
In the present embodiment, described second nitration case 205, oxide layer 204 and the first nitration case 203 are etched
Technique with formed first grid layer 206 time the second mask layer as mask, described second mask layer can
Described first grid layer 206 top surface is protected.Described etching the second nitration case 205, oxide layer
204 and first the technique of nitration case 203 be anisotropic dry etch process, the second nitridation after etching
The sidewall of layer 205, oxide layer 204 and the first nitration case 203 is perpendicular to substrate 200 surface.
In one embodiment, described second nitration case 205, oxide layer 204 and the first nitration case are being etched
After 203, at described first grid layer the 206, second nitration case 205, oxide layer 204 and the first nitrogen
The sidewall surfaces changing layer 203 forms side wall.The forming step of described side wall includes: described sealing coat 202,
And the sidewall of fin 201 and top surface form side wall film；It is etched back to described side wall film until exposing
Described sealing coat 202 and the sidewall of fin 201 and top surface, form side wall.
To sum up, in the present embodiment, before forming oxide layer, at insulation surface and described fin
Sidewall and top surface form the first nitration case, owing to passing through formation process, it is possible to make described first nitrogen
Changing layer and have good step covering power, the first nitration case formed can closely be covered in fin
Sidewall and top surface so that the stable performance of the semiconductor structure formed, leakage current reduces.And,
By regulation formation process, it is possible to make the thickness of the first nitration case and the concentration of Nitrogen ion be distributed the most equal
Even, the most described first nitration case is for stopping that the dopant ion in fin diffuses into the grid being subsequently formed
Ability in structure is higher and stable.After forming described oxide layer, it is described oxide layer surface shape
Becoming the second nitration case, the second nitration case formed and the electrical thickness of described first nitration case are less than identical
The oxidated layer thickness of physical thickness such that it is able to make the total of the first nitration case, oxide layer and the second nitration case
Electrical thickness reduces, and is conducive to reducing tunneling voltage, improves operating current, improves the quasiconductor formed
The performance of structure.Additionally, due to formed described first nitration case before forming oxide layer, thus avoid
After oxide layer surface forms the second nitration case, extra rapid thermal anneal process is used to form oxidation
Nitration case step between layer and fin, it is possible to avoid because the hot environment of rapid thermal anneal process is to fin
Cause damage.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (19)
1. the forming method of a semiconductor structure, it is characterised in that including:
Thering is provided substrate, described substrate surface has fin and sealing coat, and the surface of described sealing coat is less than institute
State the top surface of fin, and described sealing coat covers the partial sidewall surface of described fin；
The first nitration case is formed at described insulation surface and the sidewall of described fin and top surface；
Oxidation processing technique is used to form oxide layer on described first nitration case surface；
The second nitration case is formed on described oxide layer surface；
Part surface at the second nitration case forms grid structure, and described grid structure is covered in the side of fin
Wall and top, and described grid structure is across described fin.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described first nitridation
The material of layer is silicon nitride.
3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described first nitridation
The formation process of layer is atom layer deposition process.
4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described first nitridation
The thickness of layer is 20 angstroms～200 angstroms.
5. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described oxidation processes
Technique is that steam generates technique, decoupled plasma oxidation technology or free-radical oxidation technique in situ.
6. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described oxidation processes
Technique makes part the first nitration case being positioned at surface be converted into oxide layer.
7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that at described oxidation
Before science and engineering skill, the thickness of described first nitration case is the first thickness, is converted into the part of oxide layer
One nitride thickness is the second thickness, and described second thickness is the 60%～98% of described first thickness.
8. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described oxide layer
Material is silicon oxide.
9. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described second nitridation
The material of layer is silicon nitride.
10. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that form described second
The technique of nitration case includes nitrogenation treatment technology.
The forming method of 11. semiconductor structures as claimed in claim 10, it is characterised in that described nitrogen treatment
Technique is decoupled plasma nitridation process.
The forming method of 12. semiconductor structures as claimed in claim 10, it is characterised in that described nitrogen treatment
Technique makes the portion of oxide layer being positioned at surface be converted into the second nitration case.
The forming method of 13. semiconductor structures as claimed in claim 12, it is characterised in that at described plasma
Before body nitrogenation treatment technology, the thickness of described oxide layer is the 3rd thickness, is converted into the second nitration case
Partial oxidation layer thickness be the 4th thickness, described 4th thickness is the 5%～30% of described 3rd thickness.
The forming method of 14. semiconductor structures as claimed in claim 10, it is characterised in that form described second
The technique of nitration case also includes: after described nitrogenation treatment technology, carries out annealing process.
The forming method of 15. semiconductor structures as claimed in claim 1, it is characterised in that described grid structure
Including the first grid layer being positioned at part the second nitration case surface.
The forming method of 16. semiconductor structures as claimed in claim 15, it is characterised in that described first grid
The material of layer is polysilicon.
The forming method of 17. semiconductor structures as claimed in claim 1, it is characterised in that described grid structure
Also include: be positioned at the interlayer dielectric layer on first grid layer surface；It is positioned at the second of interlayer dielectric layer surface
Grid layer.
The forming method of 18. semiconductor structures as claimed in claim 17, it is characterised in that described inter-level dielectric
The material of layer is one or more combinations in silicon oxide, silicon nitride, silicon oxynitride；Described second gate
The material of pole layer is polysilicon.
The forming method of 19. semiconductor structures as claimed in claim 1, it is characterised in that also include: in shape
After becoming grid structure, with described grid structure as mask, etch described second nitration case, oxide layer
With the first nitration case, till the sidewall exposing described sealing coat and fin and top surface.
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| CN110890279A (en) * | 2018-09-11 | 2020-03-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN117376796A (en) * | 2023-12-08 | 2024-01-09 | 瑞声光电科技(常州)有限公司 | Method for preparing micro electromechanical microphone |
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| CN117376796A (en) * | 2023-12-08 | 2024-01-09 | 瑞声光电科技(常州)有限公司 | Method for preparing micro electromechanical microphone |
| CN117376796B (en) * | 2023-12-08 | 2024-02-06 | 瑞声光电科技(常州)有限公司 | Method for preparing micro electromechanical microphone |
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Application publication date: 20161207 |