CN106952815A - The forming method of fin transistor - Google Patents
The forming method of fin transistor Download PDFInfo
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- CN106952815A CN106952815A CN201610006643.6A CN201610006643A CN106952815A CN 106952815 A CN106952815 A CN 106952815A CN 201610006643 A CN201610006643 A CN 201610006643A CN 106952815 A CN106952815 A CN 106952815A
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- 238000000034 method Methods 0.000 title claims abstract description 145
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- 238000007747 plating Methods 0.000 description 1
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- -1 such as He Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
Abstract
A kind of forming method of fin transistor, including：There is provided includes the substrate of core space and external zones, and the substrate surface of core space and external zones has fin respectively；In substrate surface formation separation layer, separation layer covers the partial sidewall of fin, and insulation surface is less than the top surface of fin；In fin side wall and top surface the first grid oxide layer of formation of external zones and the protective layer positioned at the first grid oxide layer surface, the dielectric coefficient of protective layer is more than the dielectric coefficient of the first grid oxide layer；In the formation of separation layer, fin and protective layer respectively across the pseudo- gate layer of core space and external zones fin；In separation layer and fin portion surface formation dielectric layer, dielectric layer is exposed at the top of pseudo- gate layer；Pseudo- gate layer is removed, first groove is formed in the dielectric layer of external zones, second groove is formed in the dielectric layer of core space；Fin side wall and top surface the second grid oxide layer of formation gone out in second groove bottom-exposed.The leakage current of the fin transistor formed is controlled, and reliability is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of fin transistor.
Background technology
With developing rapidly for semiconductor fabrication, semiconductor devices towards higher component density, with
And the direction of higher integrated level is developed.Transistor is just extensive at present as most basic semiconductor devices
Using, therefore the raising of the component density and integrated level with semiconductor devices, the grid of planar transistor
Size is also shorter and shorter, and traditional planar transistor dies down to the control ability of channel current, produces short ditch
Channel effect, produces leakage current, the electric property of final influence semiconductor devices.
In order to overcome the short-channel effect of transistor, suppress leakage current, prior art proposes fin effect
Transistor (Fin FET) is answered, fin formula field effect transistor is a kind of common multi-gate device.Fin effect
Answering the structure of transistor includes：Positioned at the fin and dielectric layer of semiconductor substrate surface, the dielectric layer covers
The side wall of fin described in cover, and dielectric layer surface is less than at the top of fin；Positioned at dielectric layer surface, with
And top and the grid structure of sidewall surfaces of fin；Source in the fin of the grid structure both sides
Area and drain region.
However, density raising, size reduction, the system of fin formula field effect transistor with semiconductor devices
Technology difficulty is made to improve, and degradation, the reliability decrease of the fin formula field effect transistor formed.
The content of the invention
The problem of present invention is solved is to provide a kind of forming method of fin transistor, and the fin formed is brilliant
The leakage current of body pipe is controlled, and driving current is improved, and power consumption reduces, improved stability.
To solve the above problems, the present invention provides a kind of forming method of fin transistor, including：There is provided
Substrate, the substrate includes core space and external zones, and the substrate surface of the core space and external zones is distinguished
With fin；In substrate surface formation separation layer, the separation layer covers the part side of the fin
Wall, and the insulation surface is less than the top surface of the fin；On the fin side wall of external zones and top
Portion surface forms the first grid oxide layer and the protective layer positioned at the first grid oxide layer surface, the protective layer
Dielectric coefficient be more than first grid oxide layer dielectric coefficient；In the separation layer, fin and protective layer
Surface forms pseudo- gate layer respectively across the core space and external zones fin, and the pseudo- gate layer is covered in portion
On the side wall and top for dividing the fin；In the separation layer and fin portion surface formation dielectric layer, given an account of
The side wall of the matter layer covering pseudo- gate layer, and the dielectric layer exposes the pseudo- gate layer top；Remove institute
Pseudo- gate layer is stated, first groove is formed in the dielectric layer of the external zones, in the dielectric layer of the core space
Interior formation second groove；Fin side wall and the top surface formation the gone out in the second groove bottom-exposed
Two grid oxide layers；In the first grid structure of the full first groove of protective layer formation filling；
The second grid oxide layer surface forms the second grid structure of the full second groove of filling.
Optionally, the forming step of first grid oxide layer and protective layer includes：In the fin exposed
Side wall and the top surface first grid oxygen film of formation in portion；Formed in the first grid oxygen film and insulation surface
Diaphragm；The first patterned layer is formed on the diaphragm surface of external zones；Using first patterned layer as
Mask, etches the diaphragm and the first grid oxygen film of the core space, expose core space fin side wall and
Top surface, forms the first grid oxide layer and protective layer；In the diaphragm and the first grid oxygen film of etching core space
Afterwards, first patterned layer is removed.
Optionally, the formation process of the diaphragm is atom layer deposition process.
Optionally, also include：Before pseudo- gate layer is formed, in the separation layer, fin and protective layer table
Face forms pseudo- gate dielectric layer；After the pseudo- gate layer is removed, first groove and second groove bottom are removed
Pseudo- gate dielectric layer.
Optionally, the formation process of the pseudo- gate dielectric layer is atom layer deposition process.
Optionally, the material of the protective layer includes high K dielectric material.
Optionally, the material of the protective layer includes：Al2O3、ZrO2, HfO2；The Al2O3 of nitrating,
ZrO2Or HfO2；Or, mix the silica of aluminium, yttrium, hafnium or nitrogen.
Optionally, the dielectric coefficient of the protective layer is 6~20.
Optionally, the thickness of the protective layer is 5 angstroms~25 angstroms.
Optionally, the formation process of first grid oxide layer is situ steam generation technique.
Optionally, the thickness of first grid oxide layer is 10 angstroms~35 angstroms.
Optionally, the formation process of second grid oxide layer is thermal oxidation technology or wet process oxidation technology.
Optionally, the technique for removing the pseudo- gate layer is one in wet-etching technology and dry etch process
Plant or two kinds of combinations.
Optionally, the first grid structure includes the first gate dielectric layer and positioned at the first gate dielectric layer
On first grid layer, the full first groove of first grid layer filling；The second grid structure
Second grid layer including the second gate dielectric layer and on the second gate dielectric layer, the second grid
The full second groove of layer filling.
Optionally, the forming step of the first grid structure and second grid structure includes：Given an account of
The inner wall surface formation gate dielectric film of matter layer surface, the inner wall surface of first groove and second groove；In shape
Into after gate dielectric film, the gate electrode film of the filling full first groove and second groove is formed；Planarization institute
Gate electrode film and gate dielectric film are stated untill the dielectric layer surface is exposed, is formed in first groove
One gate dielectric layer and first grid layer, form the second gate dielectric layer and second grid layer in second groove.
Optionally, the top surface of the fin also has mask layer.
Optionally, the forming step of the substrate and fin includes：Semiconductor base is provided；Described half
The part surface formation mask layer of conductor substrate, the mask layer covering needs to form the correspondence position of fin
And shape；Using the mask layer as mask, the semiconductor base is etched, the substrate and fin is formed.
Optionally, the forming step of the separation layer includes：In the substrate and fin portion surface formation isolation
Film；Planarize the barrier film；After the barrier film is planarized, be etched back to the barrier film until
Untill exposing part fin side wall.
Optionally, while the barrier film is etched back to or afterwards, the mask layer is removed.
Optionally, before the separation layer is formed, in the substrate and fin portion surface formation liner oxidation
Layer；After the separation layer is formed, the cushion oxide layer exposed is removed.
Compared with prior art, technical scheme has advantages below：
In the forming method of the present invention, in fin side wall and top surface the first grid oxide layer of formation of external zones,
And protective layer is formed on the first grid oxide layer surface, and the pseudo- gate layer is formed at the protective layer table
Face.When being subsequently formed dielectric layer and removing the pseudo- gate layer, the protective layer can be used in protection first
Grid oxide layer is from damage, it is to avoid first grid oxide layer produces time breakdown effect, so as to improve to be formed
Fin transistor for short-channel effect rejection ability, improve driving current, reduce transistor work(
Consumption, suppresses the influence of the unstable effect of Bias Temperature.The dielectric coefficient for being additionally, since the protective layer is big
In the dielectric coefficient of the first grid oxide layer, so as to avoid increasing the situation of fin transistor threshold voltage
Under, reduce the carrier Tunneling Phenomenon between the first grid structure being subsequently formed and fin.Therefore, institute
The performance improvement of the fin formula field effect transistor of formation, reliability are improved.
Brief description of the drawings
Fig. 1 to Fig. 4 is a kind of cross-sectional view of the forming process of fin formula field effect transistor；
Fig. 5 to Figure 15 is the cross-section structure signal of the forming process of the fin transistor of the embodiment of the present invention
Figure.
Embodiment
As stated in the Background Art, with semiconductor devices density raising, size reduction, the fin formed
The degradation of formula field-effect transistor, reliability decrease.
In order to further reduce device size, device density be improved, on the basis of fin formula field effect transistor
On, high-K metal gate transistor is introduced, i.e., using high K dielectric material as gate dielectric layer, with metal material
Material is used as grid.Moreover, the combination shape between gate dielectric layer and fin in order to improve high K dielectric material
State, also needs to form grid oxide layer between the gate dielectric layer and fin of the high K dielectric material and is bonded.
The high-K metal gate transistor is formed using rear grid (Gate Last) technique, grid technique after one of which
In be after removing the pseudo- gate layer of polysilicon and forming gate trench, then at the inner wall surface of gate trench
Form the gate dielectric layer of high K dielectric material.
However, for the fin formula field effect transistor of external zones, because grid oxide layer is forming pseudo- gate layer
Formed before, then the grid oxide layer can be damaged by removing the technique of the pseudo- gate layer.As fin field effect is brilliant
The size of body pipe is smaller, and the influence of the damage of the grid oxide layer to device performance becomes apparent from.Below with reference to
Accompanying drawing is illustrated.
Fig. 1 to Fig. 4 is a kind of cross-sectional view of the forming process of fin formula field effect transistor.
Fig. 1 be refer to there is provided substrate 100, the substrate 100 includes core space 110 and external zones 120,
The surface of substrate 100 of the core space 110 and external zones 120 has fin 101, the substrate respectively
100 surfaces form separation layer 102, and the separation layer 102 covers the partial sidewall surface of the fin 101,
And the surface of separation layer 102 is less than the top surface of the fin 101.
Fig. 2 is refer to, in side wall and top surface the first grid oxide layer of formation of the fin 101 exposed
103；Formed on the surface of the first grid oxide layer 103 respectively across the core space 110 and external zones 120
The pseudo- gate layer 104 of fin 101, the pseudo- gate layer 104 covers partial sidewall and the top of the fin 101.
Fig. 3 is refer to, dielectric layer 105, the dielectric layer 105 are formed on the surface of the first grid oxide layer 103
The side wall of the pseudo- gate layer 104 is covered, and the dielectric layer 105 exposes the top of pseudo- gate layer 104.
Fig. 4 is refer to, the pseudo- gate layer 104, the shape in the dielectric layer 105 of the external zones 120 is removed
Into first groove 121, second groove 111 is formed in the dielectric layer 105 of the core space 110.
Wherein, the formation process of first grid oxide layer 103 is atom layer deposition process, and material is oxidation
Silicon.First grid oxide layer 103 is used for when removing pseudo- gate layer 104, protection core space 110 and periphery
The side wall of fin 101 and top surface in area 120.Due to the silica using atom layer deposition process formation
Density is relatively low, and internal easily to form defect, therefore, first grid oxide layer 103 is not suitable as core
The grid oxide layer of the fin formula field effect transistor of area 110, then subsequently need to remove the first grid oxygen of core space 110
Layer 103.
Secondly as density and internal flaw of the fin formula field effect transistor of external zones 120 to grid oxide layer
Quantitative requirement is relatively low, therefore, it is possible to retain the first oxide layer 103 of external zones 120, is used as external zones 120
Grid oxide layer in the fin formula field effect transistor of formation.After the pseudo- gate layer 104 is removed, subsequently need
The first grid oxide layer 103 of core space 110 is removed, and exposed with thermal oxidation technology in core space 110
Fin 101 and lower surface the second grid oxide layer of formation.
Although however, first grid oxide layer 103 can protect core space when removing pseudo- gate layer 104
110 and the side wall of fin 101 and top surface of external zones 120, but the etching for removing pseudo- gate layer 104
Technique also easily causes damage to first grid oxide layer 103, and the first impaired grid oxide layer 103 is not
Only easily cause time breakdown (Time Dependent Dielectric Breakdown, abbreviation TDDB),
Cause short-channel effect, reduce driving current, improve power consumption, be also easy to cause the unstable effect of Bias Temperature
Answer (Bias Temperature Instability, abbreviation BTI), the transistor performance formed is deteriorated.
In order to solve the above problems, the present invention provides a kind of forming method of fin transistor, including：Carry
For substrate, the substrate includes core space and external zones, the substrate surface point of the core space and external zones
Ju You not fin；In substrate surface formation separation layer, the separation layer covers the part of the fin
Side wall, and the insulation surface is less than the top surface of the fin；External zones fin side wall and
Top surface the first grid oxide layer of formation and the protective layer positioned at the first grid oxide layer surface, the protection
The dielectric coefficient of layer is more than the dielectric coefficient of first grid oxide layer；In the separation layer, fin and protection
Layer surface formation is respectively across the pseudo- gate layer of the core space and external zones fin, and the pseudo- gate layer is covered in
On the side wall and top of the part fin；Dielectric layer is formed in the separation layer and fin portion surface, it is described
Dielectric layer covers the side wall of the pseudo- gate layer, and the dielectric layer is exposed at the top of the pseudo- gate layer；Remove
The pseudo- gate layer, first groove is formed in the dielectric layer of the external zones, in the medium of the core space
Second groove is formed in layer；The fin side wall and top surface gone out in the second groove bottom-exposed is formed
Second grid oxide layer；In the first grid structure of the full first groove of protective layer formation filling；
The second grid structure of the full second groove of filling is formed on the second grid oxide layer surface.
Wherein, in fin side wall and top surface the first grid oxide layer of formation of external zones, and described the
One grid oxygen layer surface formation protective layer, and the pseudo- gate layer is formed at the protective layer.When follow-up shape
Into dielectric layer and when removing the pseudo- gate layer, the protective layer can be used in protecting the first grid oxide layer from damage
Wound, it is to avoid first grid oxide layer produces time breakdown effect, so as to improve formed fin transistor
For the rejection ability of short-channel effect, driving current is improved, the power consumption of transistor is reduced, suppresses bias
The influence of the unstable effect of temperature.The dielectric coefficient for being additionally, since the protective layer is more than the first grid oxide layer
Dielectric coefficient, so as in the case where avoiding increase fin transistor threshold voltage, reduce follow-up
Carrier Tunneling Phenomenon between the first grid structure and fin of formation.Therefore, the fin formed
The performance improvement of effect transistor, reliability are improved.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 5 to Figure 15 is the cross-section structure signal of the forming process of the fin transistor of the embodiment of the present invention
Figure.
Fig. 5 be refer to there is provided substrate 200, the substrate 200 includes core space 220 and external zones 210,
The surface of substrate 200 of the core space 220 and external zones 210 has fin 201 respectively.
The core space 220 is used to form core devices, and the external zones 210 is used to form peripheral components,
Such as input and output (I/O) device.The core devices density of the core space 220 is more than external zones 210
Peripheral components density, and the characteristic size (Critical Dimention, abbreviation CD) of the core devices
Less than the characteristic size of the peripheral components.The operating current or operating voltage of the core devices are less than institute
State the operating current or operating voltage of peripheral components.In the present embodiment, the core space 220 and periphery
The surface of substrate 200 in area 210 has fin 201 respectively, for respectively in core space 220 and external zones
210 form fin transistor.
In the present embodiment, the top surface of the fin 201 also has mask layer 202.The mask layer
202 form the mask of the fin 201 as etching, and the mask layer 202 can also be in follow-up work
During skill, the top surface for protecting fin 201.
In the present embodiment, the forming step of the substrate 200 and fin 201 includes：Semiconductor is provided
Substrate；In the part surface formation mask layer 202 of the semiconductor base, the covering of mask layer 202 is needed
Form the correspondence position and shape of fin 200；It is mask with the mask layer 202, etches described half
Conductor substrate, forms the substrate 200 and fin 201.
The semiconductor base is silicon substrate, germanium substrate and silicon-Germanium substrate.In the present embodiment, described half
Conductor substrate is monocrystalline substrate, i.e., the material of described fin 201 and substrate 200 is monocrystalline silicon.
The forming step of the mask layer 202 includes：In semiconductor substrate surface formation mask material
Film；Second graphical layer is formed on the mask material film surface；With second graphical layer for mask etching
The mask material film forms the mask layer 202 untill semiconductor substrate surface is exposed.
In one embodiment, the second graphical layer is patterned photoresist layer, the second graph
Change layer to be formed using coating process and photoetching process.In another embodiment, in order to reduce the fin 201
Characteristic size and the distance between adjacent fin 201, the second graphical layer uses multigraph
Shape masking process is formed.The multiple graphical masking process includes：Self-alignment duplex pattern
(Self-aligned Double Patterned, SaDP) technique, the triple graphical (Self-aligned of autoregistration
Triple Patterned) graphical (the Self-aligned Double Double of technique or autoregistration quadruple
Patterned, SaDDP) technique.
The technique for etching the semiconductor base is anisotropic dry etch process.The fin 201
Side wall it is vertical relative to the surface of substrate 200 or tilt, and when the fin 201 side wall relative to
When the surface of substrate 200 is tilted, the bottom size of the fin 201 is more than top dimension.In the present embodiment
In, the side wall of the fin 201 is tilted relative to the surface of substrate 200.
Also there is the first well region, the core space in the substrate 200 and fin 201 of the external zones 210
Also there is the second well region in 220 substrate 200 and fin 201.First well region and the second well region are used
Ion implantation technology is formed；First well region and the second well region can be formed in etching semiconductor substrate
Formed before fin 201；Or, first well region and the second well region can formed fin 201 it
After formed.
In another embodiment, the semiconductor layer that the fin is formed at substrate surface by etching is formed；
The semiconductor layer is formed at the substrate surface using selective epitaxial depositing operation.The substrate is silicon
Substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium substrate on insulator, glass lined
Bottom or III-V substrate, such as gallium nitride substrate or gallium arsenide substrate.The semiconductor layer
Material is silicon, germanium, carborundum or SiGe.
In the present embodiment, before the separation layer is subsequently formed, it is additionally included in the He of substrate 200
The surface of fin 201 forms cushion oxide layer 203.The formation process of the cushion oxide layer 203 is steamed to be in situ
Vapour generates (In-Situ Steam Generation, abbreviation ISSG) technique.The situ steam generation technique
Parameter include：Temperature is 700 DEG C~1200 DEG C, and gas includes hydrogen and oxygen, and oxygen flow is
1slm~50slm, hydrogen flowing quantity is 1slm~10slm, and the time is 20 seconds~10 minutes.The steaming in situ
The cushion oxide layer 203 of vapour generation technique formation has good gradient coating performance, can make to be formed
Cushion oxide layer 203 be closely covered in the sidewall surfaces of fin 201, and the pad oxygen formed
The thickness for changing layer 203 is uniform.
By forming the cushion oxide layer 203, the substrate 200 can be repaired and the surface of fin 201 exists
The damage being subject to during preamble etching technics and ion implantation technology.Moreover, the cushion oxide layer 203
The surface of fin 201 and substrate 200 can also be protected in successive process.
Fig. 6 is refer to, separation layer 204 is formed on the surface of substrate 200, the separation layer 204 is covered
The partial sidewall of the fin 201, and the surface of the separation layer 204 is less than the top of the fin 201
Surface.
The forming step of the separation layer 204 includes：Formed in the substrate 200 and the surface of fin 201
Barrier film；Planarize the barrier film；After the barrier film is planarized, the barrier film is etched back to
Untill the side wall of part fin 201 is exposed.
In the present embodiment, the material of the separation layer 204 is silica；The thickness of the separation layer 204
Degree is the 1/4~1/2 of the height of fin 201.The formation process of the barrier film is heavy for fluid chemistry gas phase
Product technique (FCVD, Flowable Chemical Vapor Deposition).In other embodiments, institute
Stating barrier film can also be formed using other chemical vapor deposition methods or physical gas-phase deposition；It is described
Other chemical vapor deposition methods include plasma enhanced chemical vapor deposition technique (PECVD) or height
Depth-to-width ratio chemical vapor deposition method (HARP).
In the present embodiment, the step of fluid chemistry gas-phase deposition includes：The substrate 200,
Fin 201 and the surface of mask layer 202 form forerunner's deielectric-coating；Annealing process is carried out, makes forerunner's deielectric-coating
Solidification, forms the barrier film.
The material of forerunner's deielectric-coating is siliceous flowable materials；The flowable materials can be containing
The condensate of one or more polymerizations in Si -- H bond, Si-N keys and Si-O keys.Forerunner's deielectric-coating
Formation process parameter includes：Technological temperature is 60 DEG C~70 DEG C, is 65 DEG C in the present embodiment.
Annealing process in the fluid chemistry gas-phase deposition can be that wet method annealing process or dry method are moved back
Ignition technique；The parameter of the annealing process includes：Temperature is less than or equal to 600 DEG C, and anneal gas include
H2、O2、N2, one or more combinations in Ar and He, annealing time is 5 seconds~1 minute.Wherein,
When anneal gas include H2And O2When, the annealing process is wet method annealing process.
The flatening process is CMP process (CMP)；In the present embodiment, describedization
Learn mechanical polishing process and stop-layer is used as using the mask layer 202.The technique for being etched back to the barrier film is
Isotropic dry etch process, anisotropic dry etch process or wet-etching technology.
In the present embodiment, while the barrier film is etched back to or afterwards, the mask layer 202 is removed
(as shown in Figure 5).After the separation layer 204 is formed, the cushion oxide layer 203 exposed is removed；
Because the cushion oxide layer 203 exposed can sustain damage in the technique for being etched back to barrier film, therefore
The cushion oxide layer 203 is not suitable as follow-up gate oxide, it is therefore desirable to remove the pad oxygen
Change layer 203.
In fin side wall and top surface the first grid oxide layer of formation of external zones and positioned at first grid oxygen
The protective layer of layer surface, the dielectric coefficient of the protective layer is more than the dielectric coefficient of first grid oxide layer.
The forming step of first grid oxide layer and protective layer is as shown in Fig. 7 to Fig. 8.
Fig. 7 is refer to, in side wall and top surface the first grid oxygen film of formation of the fin 201 exposed
211。
The first grid oxygen film 211 is used for the grid oxide layer formed in the fin transistor of external zones 210, uses
In the bond strength between the first gate dielectric layer that external zones 210 strengthens fin 201 and is subsequently formed,
The material of first gate dielectric layer is high K dielectric material (dielectric coefficient is more than 3.9), the first grid
Dielectric layer as the fin formula field effect transistor of external zones 210 gate dielectric layer.
The material of the first grid oxygen film 211 is silica, and the thickness of the first grid oxygen film 211 is 10
Angstrom~35 angstroms；In the present embodiment, the thickness of the first grid oxygen film is 15 angstroms.In the present embodiment,
The formation process of the first grid oxygen film 211 is situ steam generation technique；The situ steam generates work
The parameter of skill includes：Temperature is 700 DEG C~1200 DEG C, and gas includes hydrogen and oxygen, and oxygen flow is
1slm~50slm, hydrogen flowing quantity is 1slm~10slm, and the time is 10 seconds~5 minutes.
In another embodiment, the formation process of the first grid oxygen film 211 is chemical oxidation process；Institute
The step of stating chemical oxidation process includes：The fin 201 is exposed using the aqueous solution for being passed through ozone
Side wall and top surface aoxidized, the fin 201 side wall and top surface formation the first oxygen
Change layer.Wherein, it is passed through described in the aqueous solution of ozone, concentration of the ozone in water is 1%~15%.
Fig. 8 is refer to, diaphragm 212 is formed in the first grid oxygen film 211 and the surface of separation layer 204.
The diaphragm 212 is used to protect the first grid oxide layer, the first grid in the pseudo- gate layer of follow-up removal
Oxygen layer is formed by the first grid oxygen film 211 of external zones 210.Because first grid oxide layer is used to form outer
Enclose the grid oxide layer in the fin formula field effect transistor in area 210, therefore the first grid oxygen of the external zones 210
Film 211 needs to be exposed and retain in successive process.And the protective layer formed by the diaphragm 212
The damage that first grid oxide layer is subject to then can be reduced in the follow-up etching technics for removing pseudo- gate layer.
In the present embodiment, the material of the diaphragm 212 includes high K dielectric material, the guarantor formed
The density of material and hardness of sheath are higher, and with the etching selection ratio between the pseudo- grid layer material that is subsequently formed
It is larger, therefore, it is sufficient to the first formed grid oxide layer is protected in successive process.
The dielectric coefficient for being additionally, since the material of diaphragm 212 is higher, and the protective layer formed is located at
Between first grid oxide layer and the first gate dielectric layer being subsequently formed, the protective layer can not improved
In the case of fin transistor threshold voltage, suppress the load between fin 201 and first gate dielectric layer
Sub- Tunneling Phenomenon is flowed, leakage current is reduced.
In the present embodiment, the dielectric coefficient of the diaphragm 212 is 6~20.The diaphragm 212
Material includes：Al2O3、ZrO2, HfO2；The Al of nitrating2O3、ZrO2Or HfO2；Or, mix aluminium,
The silica of yttrium, hafnium or nitrogen.In other embodiments, the material of the diaphragm 212 can also be it
Its high K dielectric material (dielectric coefficient is more than 3.9).
In the present embodiment, the formation process of the diaphragm 212 is atom layer deposition process.Using original
The diaphragm 212 of sublayer depositing operation formation has good gradient coating performance, can closely fit
In the surface of 204 and first grid oxide layer of separation layer 211；Moreover, the thickness of diaphragm 212 formed is uniform,
Be conducive to making the threshold voltage stabilization of the fin formula field effect transistor of the formation of external zones 210.
The thickness of the diaphragm 212 is 5 angstroms~25 angstroms；In the present embodiment, the diaphragm 212
Thickness be 20 angstroms.The thickness of the diaphragm 212 is unsuitable blocked up, otherwise easily improves external zones 210
The threshold voltage of the fin transistor of formation, is unfavorable for the lower power consumption of semiconductor devices.The diaphragm
212 thickness is also unsuitable excessively thin, and the protective layer being otherwise subsequently formed is not enough to protection first grid oxide layer,
Still easily cause the damage of the first grid oxide layer.
Fig. 9 is refer to, the first patterned layer 222 is formed on the surface of diaphragm 212 of external zones 210；With
First patterned layer 222 is mask, etches the diaphragm 212 of the core space 220 (such as Fig. 8 institutes
Show) and the first grid oxygen film 211 (as shown in Figure 8) expose side wall and the top of the fin 201 of core space 220
Portion surface, forms the first grid oxide layer 211a and protective layer 212a.
First patterned layer 222 is patterned photoresist layer, and first patterned layer 222 is adopted
Formed with coating process and photoetching process.The technique for etching the grid oxygen film 211 of diaphragm 212 and first
For wet-etching technology or isotropic dry etch process.
In the present embodiment, the material of the diaphragm 212 includes high K dielectric material, the first grid
The material of oxygen film 211 is silica；The technique for etching the grid oxygen film 211 of diaphragm 212 and first is equal
For isotropic dry etch process.
In the present embodiment, the isotropic dry etch technique for etching the first grid oxygen film 211 can
For SICONI techniques.Etch rate of the SICONI techniques on each different directions is uniform, can
The first grid oxide layer 211 positioned at the side wall of fin 201 and top surface is equably removed, and to the fin
The damage of 201 side walls and top surface is smaller.
The parameter of the SICONI techniques includes：Power 10W~100W, frequency is less than 100kHz, carves
It is 40 degrees Celsius~80 degrees Celsius to lose temperature, and pressure is the support of 0.5 support~50, and etching gas include NH3、
NF3, He, wherein, NH3Flow be 0sccm~500sccm, NF3Flow be 20sccm~200sccm,
He flow is 400sccm~1200sccm, NF3With NH3Flow-rate ratio be 1:20~5:1.
Figure 10 is refer to, is formed and distinguished on the separation layer 204, fin 201 and protective layer 212a surfaces
Across the pseudo- gate layer 205 of the core space 220 and the fin 201 of external zones 210, the pseudo- gate layer 205 is covered
Cover on the side wall and top of the part fin 201.
In the present embodiment, in the diaphragm 212 (as shown in Figure 8) and the first grid of etching core space 210
After oxygen film 211 (as shown in Figure 8), first patterned layer 222 is removed.
The material of the pseudo- gate layer 205 is polysilicon.The forming step of the pseudo- gate layer 205 includes：
The protective layer 212a surfaces on the surface of separation layer 204, the surface of fin 201 and external zones 210 are formed
Dummy grid film；The dummy grid film is planarized；After the flatening process, in the puppet
Gate electrode film surface forms the 3rd patterned layer, and the 3rd patterned layer covering needs to form pseudo- gate layer 205
Location and shape；Using the 3rd patterned layer as mask, the dummy grid film is etched, until exposure
Untill going out separation layer 204, fin 201 and protective layer 212a surfaces, pseudo- gate layer 205 is formed.
In the present embodiment, it is additionally included in before forming the dummy grid film, in the table of separation layer 204
Face, the surface of fin 201 and protective layer 212a surfaces form pseudo- gate dielectric layer 213；In the pseudo- gate medium
213 surface of layer form the dummy grid film.
In one embodiment, after the dummy grid film is etched, the pseudo- gate dielectric layer 213 is etched, directly
Untill separation layer 204, fin 201 and protective layer 212a surfaces is exposed.In another embodiment,
After the dummy grid film is etched, the pseudo- gate dielectric layer 213 is not etched.
The material of the pseudo- gate dielectric layer 213 is silica；The formation process of the pseudo- gate dielectric layer 213
For atom layer deposition process；The thickness of the pseudo- gate dielectric layer 213 is 5 angstroms~15 angstroms.In the present embodiment,
The thickness of the pseudo- gate dielectric layer 213 is 10 angstroms.The pseudo- gate dielectric layer 213 is used to remove puppet follow-up
During gate layer, the surface of fin 201 of core space 220 is protected.
In the present embodiment, it is additionally included in the sidewall surfaces formation side wall of the pseudo- gate layer 205；Described
Source region and drain region are formed in the fin 201 of pseudo- gate layer 205 and side wall both sides.
The material of the side wall includes one or more combinations in silica, silicon nitride and silicon oxynitride.
The forming step of the side wall includes：Using depositing operation in the protective layer and the pseudo- surface shape of gate layer 205
Into side wall film；The side wall film is etched back to until exposing the protective layer position on the surface of fin 201, is formed
Side wall.
In one embodiment, the source region and drain region are formed with ion implantation technology.In another embodiment,
The source region and the forming step in drain region also include：Fin 201 in the pseudo- gate layer 205 and side wall both sides
Interior formation groove；Stressor layers are formed in the groove using selective epitaxial depositing operation；Answered described
Doped ions in power layer, form source region and drain region.The doping process is ion implantation technology, original position is mixed
One or two kinds of combinations in general labourer's skill.
When the fin transistor formed is PMOS transistor, the material of the stressor layers is SiGe,
The ion of doping is p-type ion in the stressor layers, and the stressor layers are Σ type stressor layers.When institute's shape
Into fin transistor be nmos pass transistor when, the materials of the stressor layers is carborundum, the stress
The ion of doping is N-type ion in layer.
Figure 11 is refer to, dielectric layer 206 is formed in the separation layer 204 and the surface of fin 201, it is described
Dielectric layer 206 covers the side wall of the pseudo- gate layer 205, and the dielectric layer 206 exposes the pseudo- grid
The top of layer 205.
The forming step of the dielectric layer 206 includes：In the separation layer 204, fin 201, protective layer
The surface of 212a and pseudo- gate layer 205 forms deielectric-coating；The deielectric-coating is planarized until exposing the puppet
Untill the top surface of gate layer 205, the dielectric layer 206 is formed.
The formation process of the deielectric-coating is chemical vapor deposition method, physical gas-phase deposition or atom
Layer depositing operation.The material of the dielectric layer 206 is silica, silicon nitride, silicon oxynitride, low k Jie
(dielectric coefficient is such as porous silica or porous nitrogen more than or equal to 2.5, less than 3.9 to material
SiClx) or ultra-low k dielectric material (dielectric coefficient is less than 2.5, such as porous SiC OH).
In the present embodiment, the material of the dielectric layer 206 is silica；The formation work of the deielectric-coating
Skill is fluid chemistry vapour deposition (Flowable Chemical Vapor Deposition, abbreviation FCVD)
Technique, high-density plasma deposition (High Density Plasma, abbreviation HDP) technique, plasma
One or more in enhanced deposition technique.
Figure 12 is refer to, the pseudo- gate layer 205 (as shown in figure 11) is removed, in the external zones 210
Dielectric layer 206 in form first groove 214, the is formed in the dielectric layer 206 of the core space 220
Two grooves 221.
Remove the pseudo- gate layer 205 technique be dry etch process and wet-etching technology in one kind or
Two kinds of combinations；Wherein, the dry etch process is isotropic dry etch process.
In the present embodiment, the material of the pseudo- gate layer 205 is polysilicon, removes the pseudo- gate layer 205
Technique be plasma dry etch process；The parameter of the plasma dry etch process includes：
Gas includes carbon fluorine gas, HBr and Cl2In one or two and carrier gas, the carbon fluorine gas bag
Include CF4、CHF3、CH2F2Or CH3F, the carrier gas is inert gas, such as He, and gas flow is
50sccm~400sccm, pressure is the millitorr of 3 millitorrs~8.
In the plasma dry etch process, due to the protective layer 212a density and hardness compared with
Height, so as to avoid the first grid oxide layer 211a by plasma damage.The protective layer 212a and
One grid oxide layer 211a is remained in the fin transistor of the formation of external zones 210, due to the protective layer 212a
It is less with damage suffered by the first grid oxide layer 211a, advantageously ensure that the fin that external zones 210 is formed is brilliant
The performance of body pipe is more stable.
In another embodiment, the technique for removing the pseudo- gate layer is wet-etching technology, and the wet method is carved
The etching liquid of etching technique is hydrofluoric acid solution.
Figure 13 is refer to, the pseudo- gate dielectric layer 213 of first groove 214 and the bottom of second groove 221 is removed
(as shown in figure 12).
In the present embodiment, the material of the pseudo- gate dielectric layer 213 is silica, removes the pseudo- grid and is situated between
The technique of matter layer 213 is wet-etching technology or isotropic dry etch process.Carved when using wet method
When etching technique removes the pseudo- gate dielectric layer 213, the etching liquid of the wet-etching technology is molten for hydrofluoric acid
Liquid.When removing the pseudo- gate dielectric layer 213 using isotropic dry etch process, it is described it is each to
The dry etch process of the same sex can be SICONI techniques.
In the present embodiment, because the material of the protective layer 212a is high K dielectric material, the protection
Etching selection ratio between layer 212a and pseudo- gate dielectric layer 213 is larger, and the pseudo- gate layer 205 is removed in etching
When, the damage that the protective layer 212a is subject to is less.
Figure 14 is refer to, the side wall of fin 201 and top table gone out in the bottom-exposed of second groove 221
Face forms the second grid oxide layer 223.
Second grid oxide layer 223 is used for the grid oxide layer of the fin transistor as the formation of core space 210.
The material of second grid oxide layer 223 is silica；The formation process of second grid oxide layer 223 is heat
Oxidation technology or wet process oxidation technology.
The thickness of second grid oxide layer 223 is 3 nanometers~10 nanometers.In the present embodiment, described second
The formation process of grid oxide layer 223 is chemical oxidation process；The step of chemical oxidation process, includes：Adopt
The side wall and top surface exposed with the aqueous solution for being passed through ozone to the fin 201 is aoxidized,
Side wall and top surface the second grid oxide layer 223 of formation of the fin 201.Wherein, it is passed through ozone described
The aqueous solution in, concentration of the ozone in water be 1%~15%.
Figure 15 is refer to, the full first groove 214 of filling is formed on the protective layer 212a surfaces (such as
Shown in Figure 14) first grid structure；Filling full described the is formed on the surface of the second grid oxide layer 223
The second grid structure of two grooves 221 (as shown in figure 14).
The first grid structure includes the first gate dielectric layer 215 and on the first gate dielectric layer 215
First grid layer 216, the full first groove 214 of the filling of first grid layer 216；Described second
Grid structure includes the second gate dielectric layer 224 and the second grid layer on the second gate dielectric layer 224
225, the full second groove 221 of the filling of second grid layer 225.
The forming step of the first grid structure and second grid structure includes：In the dielectric layer 206
The inner wall surface formation gate dielectric film on surface, the inner wall surface of first groove 214 and second groove 221；
After gate dielectric film is formed, the grid of the filling full first groove 214 and second groove 221 is formed
Film；The gate electrode film and gate dielectric film are planarized untill the surface of dielectric layer 206 is exposed,
The first gate dielectric layer 215 and first grid layer 216 are formed in first groove 214, in second groove 221
Form the second gate dielectric layer 224 and second grid layer 225.
The material of the gate dielectric layer 224 of first gate dielectric layer 215 and second is that high K medium material (is situated between
3.9) electrostrictive coefficient is more than；The high K medium material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, oxidation
Lanthanum, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or oxidation
Aluminium.The formation process of the gate dielectric film is atom layer deposition process.
The material of the first grid layer 216 and second grid layer 225 includes copper, tungsten, aluminium or silver；Institute
Stating the formation process of gate electrode film includes chemical vapor deposition method, physical gas-phase deposition, atomic layer deposition
Product technique, electroplating technology or chemical plating process.It is chemistry to planarize the gate electrode film and gate dielectric film technique
Mechanical polishing process (CMP).
In one embodiment, before the gate electrode film is formed, it is additionally included in gate dielectric film surface shape
Success function film；Gate electrode film is formed on the work function film surface；After the gate electrode film is planarized,
The work function film is planarized untill the surface of dielectric layer 206 is exposed, work-function layer is formed.
The material of the work-function layer formed in first groove 214 and second groove 221 can be identical or different.
In the present embodiment, after the gate dielectric film is formed, formed before the gate electrode film, also wrapped
Include carry out annealing process.The annealing process is used to eliminate the defect in the inside of fin 201 and surface
Or impurity and the first grid oxide layer 211, the second grid oxide layer 223, the first gate dielectric layer 215 and second gate
Defect or impurity in dielectric layer 224.Moreover, the annealing process, which can also be used to activation, is located at fin
The foreign ion in source region and drain region in 201.
To sum up, in the present embodiment, in fin side wall and top surface the first grid oxide layer of formation of external zones,
And protective layer is formed on the first grid oxide layer surface, and the pseudo- gate layer is formed at the protective layer table
Face.When being subsequently formed dielectric layer and removing the pseudo- gate layer, the protective layer can be used in protection first
Grid oxide layer is from damage, it is to avoid first grid oxide layer produces time breakdown effect, so as to improve to be formed
Fin transistor for short-channel effect rejection ability, improve driving current, reduce transistor work(
Consumption, suppresses the influence of the unstable effect of Bias Temperature.The dielectric coefficient for being additionally, since the protective layer is big
In the dielectric coefficient of the first grid oxide layer, so as to avoid increasing the situation of fin transistor threshold voltage
Under, reduce the carrier Tunneling Phenomenon between the first grid structure being subsequently formed and fin.Therefore, institute
The performance improvement of the fin formula field effect transistor of formation, reliability are improved.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of fin transistor, it is characterised in that including：
Substrate is provided, the substrate includes core space and external zones, the substrate of the core space and external zones
Surface has fin respectively；
In substrate surface formation separation layer, the separation layer covers the partial sidewall of the fin, and
The insulation surface is less than the top surface of the fin；
In fin side wall and top surface the first grid oxide layer of formation of external zones and positioned at first grid oxygen
The protective layer of layer surface, the dielectric coefficient of the protective layer is more than the dielectric coefficient of first grid oxide layer；
In the formation of the separation layer, fin and protective layer respectively across the core space and external zones fin
The pseudo- gate layer in portion, the pseudo- gate layer is covered on the side wall and top of the part fin；
In the separation layer and fin portion surface formation dielectric layer, the dielectric layer covers the side of the pseudo- gate layer
Wall, and the dielectric layer exposes the pseudo- gate layer top；
The pseudo- gate layer is removed, first groove is formed in the dielectric layer of the external zones, in the core
Second groove is formed in the dielectric layer in area；
Fin side wall and top surface the second grid oxide layer of formation gone out in the second groove bottom-exposed；
In the first grid structure of the full first groove of protective layer formation filling；
The second grid structure of the full second groove of filling is formed on the second grid oxide layer surface.
2. the forming method of fin transistor as claimed in claim 1, it is characterised in that first grid oxygen
The forming step of layer and protective layer includes：Formed in the side wall and top surface of the fin exposed
First grid oxygen film；In the first grid oxygen film and insulation surface formation diaphragm；In the guarantor of external zones
Cuticula surface forms the first patterned layer；Using first patterned layer as mask, the core is etched
The diaphragm in area and the first grid oxygen film, expose the side wall and top surface of core space fin, form the
One grid oxide layer and protective layer；After the diaphragm and the first grid oxygen film of etching core space, remove described
First patterned layer.
3. the forming method of fin transistor as claimed in claim 2, it is characterised in that the diaphragm
Formation process is atom layer deposition process.
4. the forming method of fin transistor as claimed in claim 1, it is characterised in that also include：In shape
Into before pseudo- gate layer, pseudo- gate dielectric layer is formed in the separation layer, fin and protective layer；Going
After the pseudo- gate layer, the pseudo- gate dielectric layer of first groove and second groove bottom is removed.
5. the forming method of fin transistor as claimed in claim 4, it is characterised in that the pseudo- gate medium
The formation process of layer is atom layer deposition process.
6. the forming method of fin transistor as claimed in claim 1, it is characterised in that the protective layer
Material includes high K dielectric material.
7. the forming method of fin transistor as claimed in claim 6, it is characterised in that the protective layer
Material includes：Al2O3、ZrO2, HfO2；The Al of nitrating2O3、ZrO2Or HfO2；Or, mix aluminium,
The silica of yttrium, hafnium or nitrogen.
8. the forming method of fin transistor as claimed in claim 6, it is characterised in that the protective layer
Dielectric coefficient is 6~20.
9. the forming method of fin transistor as claimed in claim 6, it is characterised in that the protective layer
Thickness is 5 angstroms~25 angstroms.
10. the forming method of fin transistor as claimed in claim 1, it is characterised in that first grid oxygen
The formation process of layer is situ steam generation technique.
11. the forming method of fin transistor as claimed in claim 1, it is characterised in that first grid oxygen
The thickness of layer is 10 angstroms~35 angstroms.
12. the forming method of fin transistor as claimed in claim 1, it is characterised in that second grid oxygen
The formation process of layer is thermal oxidation technology or wet process oxidation technology.
13. the forming method of fin transistor as claimed in claim 1, it is characterised in that remove the pseudo- grid
The technique of layer is one or two kinds of combinations in wet-etching technology and dry etch process.
14. the forming method of fin transistor as claimed in claim 1, it is characterised in that the first grid
Structure includes the first gate dielectric layer and the first grid layer on the first gate dielectric layer, described the
The full first groove of one grid layer filling；The second grid structure include the second gate dielectric layer, with
And the second grid layer on the second gate dielectric layer, full second ditch of second grid layer filling
Groove.
15. the forming method of fin transistor as claimed in claim 14, it is characterised in that the first grid
The forming step of structure and second grid structure includes：In the dielectric layer surface, first groove
The inner wall surface formation gate dielectric film of wall surface and second groove；After gate dielectric film is formed, formed
The gate electrode film of the filling full first groove and second groove；Planarize the gate electrode film and gate dielectric film
Untill the dielectric layer surface is exposed, the first gate dielectric layer and first are formed in first groove
Grid layer, forms the second gate dielectric layer and second grid layer in second groove.
16. the forming method of fin transistor as claimed in claim 1, it is characterised in that the top of the fin
Portion surface also has mask layer.
17. the forming method of fin transistor as claimed in claim 16, it is characterised in that the substrate and fin
The forming step in portion includes：Semiconductor base is provided；Formed in the part surface of the semiconductor base
Mask layer, the mask layer covering needs to form the correspondence position of fin and shape；With the mask layer
For mask, the semiconductor base is etched, the substrate and fin is formed.
18. the forming method of fin transistor as claimed in claim 16, it is characterised in that the separation layer
Forming step includes：In the substrate and fin portion surface formation barrier film；Planarize the barrier film；
After the barrier film is planarized, be etched back to the barrier film is up to exposing part fin side wall
Only.
19. the forming method of fin transistor as claimed in claim 18, it is characterised in that described in being etched back to
While barrier film or afterwards, the mask layer is removed.
20. the forming method of fin transistor as claimed in claim 1, it is characterised in that formed it is described every
Before absciss layer, in the substrate and fin portion surface formation cushion oxide layer；Formed the separation layer it
Afterwards, the cushion oxide layer exposed is removed.
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| CN201610006643.6A CN106952815A (en) | 2016-01-06 | 2016-01-06 | The forming method of fin transistor |
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| CN201610006643.6A CN106952815A (en) | 2016-01-06 | 2016-01-06 | The forming method of fin transistor |
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Application publication date: 20170714 |