CN106328694A - Formation method of semiconductor structure - Google Patents
Formation method of semiconductor structure Download PDFInfo
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- CN106328694A CN106328694A CN201510373552.1A CN201510373552A CN106328694A CN 106328694 A CN106328694 A CN 106328694A CN 201510373552 A CN201510373552 A CN 201510373552A CN 106328694 A CN106328694 A CN 106328694A
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- fin
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- grid
- forming method
- sidewall
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- 238000000034 method Methods 0.000 title claims abstract description 157
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 230000015572 biosynthetic process Effects 0.000 title abstract description 14
- 230000008569 process Effects 0.000 claims abstract description 90
- 239000007789 gas Substances 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 238000005516 engineering process Methods 0.000 claims abstract description 52
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 15
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract 2
- 229910052731 fluorine Inorganic materials 0.000 claims abstract 2
- 239000011737 fluorine Substances 0.000 claims abstract 2
- 239000010410 layer Substances 0.000 claims description 246
- 238000005530 etching Methods 0.000 claims description 41
- 238000007789 sealing Methods 0.000 claims description 40
- 150000002500 ions Chemical class 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 25
- 238000002347 injection Methods 0.000 claims description 21
- 239000007924 injection Substances 0.000 claims description 21
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical group F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 20
- 238000004381 surface treatment Methods 0.000 claims description 20
- 239000012528 membrane Substances 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 16
- 229910052760 oxygen Inorganic materials 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 239000000243 solution Substances 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 230000036961 partial effect Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 230000005669 field effect Effects 0.000 abstract description 14
- 239000012535 impurity Substances 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract description 4
- -1 Nitrogen ion Chemical class 0.000 description 19
- 229940090044 injection Drugs 0.000 description 19
- 239000006227 byproduct Substances 0.000 description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 13
- 229910052757 nitrogen Inorganic materials 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000000151 deposition Methods 0.000 description 9
- 239000012212 insulator Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
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- 230000000694 effects Effects 0.000 description 2
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- 230000000873 masking effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
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- 230000009286 beneficial effect Effects 0.000 description 1
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- 239000011248 coating agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
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- 229920000642 polymer Polymers 0.000 description 1
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- 230000009467 reduction Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A formation method of a semiconductor structure comprises the steps of providing a substrate, wherein a fin part and an isolation layer are arranged on a surface of the substrate, the isolation layer is arranged on a surface of a part of a side wall of the fin part, the surface of the isolation layer is lower than the surface of the top of the fin part, and interface layers are arranged on surfaces of the side wall and the top of the fin part; removing the interface layers by a dry etching process, wherein a gas of the dry etching process comprises a fluorine-containing gas; and performing a surface processing technology on the surfaces of the side wall and the top of the fin part, wherein a gas of surface processing comprises a nitrogen-containing gas. By the formation method of the semiconductor structure, impurities resided on the surface of the fin part can be removed, and the performance of the formed fin field-effect transistor is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the forming method of a kind of semiconductor structure.
Background technology
Along with developing rapidly of semiconductor fabrication, semiconductor device towards higher component density, with
And the direction of higher integrated level develops.Transistor as most basic semiconductor device currently by extensively
Application, therefore along with component density and the raising of integrated level of semiconductor device, the grid of planar transistor
Size is the most shorter and shorter, and the control ability of channel current is died down by traditional planar transistor, produces short ditch
Channel effect, produces leakage current, finally affects the electric property of semiconductor device.
In order to overcome the short-channel effect of transistor, suppressing leakage current, prior art proposes fin field effect
Answering transistor (Fin FET), fin formula field effect transistor is a kind of common multi-gate device.Fin field is imitated
The structure answering transistor includes: be positioned at fin and the dielectric layer of semiconductor substrate surface, and described dielectric layer covers
The sidewall of fin described in cover, and dielectric layer surface is less than fin top；Be positioned at dielectric layer surface, with
And the top of fin and the grid structure of sidewall surfaces；It is positioned at the source of the fin of described grid structure both sides
District and drain region.
But, the performance of the formed fin formula field effect transistor of prior art is bad, reliability is poor.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor structure, removes fin portion surface residual
The impurity stayed, makes the performance improvement of formed fin field effect pipe.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including: provide
Substrate, described substrate surface has fin and sealing coat, and described sealing coat is positioned at the part side of described fin
Wall surface, the surface of described sealing coat is less than the top surface of described fin, the sidewall of described fin and top
Surface, portion has boundary layer；Dry etch process is used to remove described boundary layer, described dry etch process
Gas include fluoro-gas；After removing described boundary layer, sidewall and the top table to described fin
Face carries out process of surface treatment, and the gas that described surface processes includes nitrogenous gas.
Optionally, the material of described boundary layer is silicon oxide；The thickness of described boundary layer is 10 angstroms～30 angstroms.
Optionally, the dry etch process removing described boundary layer is SiCoNi etching technics.
Optionally, the parameter of described SiCoNi etching technics includes: power 10W～100W, and frequency is less than
100kHz, etching temperature is 40 degrees Celsius～80 degrees Celsius, and pressure is 0.5 torr～50 torr, etching gas
Including NH3、NF3, He, wherein, NH3Flow be 0sccm～500sccm, NF3Flow be
The flow of 20sccm～200sccm, He is 400sccm～1200sccm, NF3With NH3Flow-rate ratio be
1:20～5:1.
Optionally, the step of described process of surface treatment includes: sidewall and the top surface to described fin
Carry out plasma-treating technology.
Optionally, the parameter of described plasma-treating technology includes: gas includes N2O、N2, in NO
One or more, power is 300 watts～1500 watts, and pressure is 10 millitorrs～100 millitorrs, and flow is
20sccm～～300sccm.
Optionally, N is included when the gas of described plasma-treating technology2During O or NO, described grade from
Daughter processes sidewall that technique exposes at described fin and top surface forms oxide layer.
Optionally, the step of described process of surface treatment also includes: at described plasma-treating technology
Afterwards, wet processing process is used to remove described oxide layer.
Optionally, the liquid of described wet processing process is hydrofluoric acid solution；Water in described hydrofluoric acid solution
It is 20:1～～200:1 with the volume ratio of Fluohydric acid..
Optionally, the thickness of described oxide layer is less than the thickness of described boundary layer；The thickness of described oxide layer
It it is 5 angstroms～10 angstroms.
Optionally, also include: after described process of surface treatment, to described sealing coat and fin portion surface
Carry out pre-cleaning processes.
Optionally, after forming described boundary layer, before removing described boundary layer, in described fin
Carry out ion implantation technology；Use the ion that annealing process is injected in activating fin.
Optionally, the ion implantation technology carried out in described fin includes that channel region stops injection, threshold value
One or more in regulation injection, well region injection.
Optionally, the forming step of described substrate and fin includes: provide semiconductor base；Described half
Conductor substrate surface forms mask layer, and described mask layer covers the semiconductor substrate surface needing to form fin；
With described mask layer as mask, etch described semiconductor base, in described semiconductor base, form groove,
Form substrate and be positioned at the fin of substrate surface.
Optionally, the forming step of described sealing coat includes: form isolation at described substrate and fin portion surface
Film；Planarize described isolating membrane till exposing the top surface of described fin；Described in planarization
After isolating membrane, it is etched back to described isolating membrane, exposes part fin sidewall surfaces, form sealing coat.
Optionally, after described process of surface treatment, in described insulation surface and the side of fin
Wall and top surface are developed across the grid structure of described fin；In the fin of described grid structure both sides
Form source region and drain region.
Optionally, described grid structure includes being positioned at insulation surface and the sidewall of fin and top surface
Grid oxide layer, it is positioned at the grid layer on grid oxide layer surface and is positioned at grid oxide layer and the side of grid layer sidewall surfaces
Wall.
Optionally, the forming step of described grid oxide layer and grid layer includes: in described insulation surface and
The sidewall of fin and top surface form grid oxygen film；Gate electrode film is formed on described grid oxygen film surface；Described
Gate electrode film surface forms patterned layer, and described patterned layer covers the corresponding region needing to form grid layer；
With described patterned layer as mask, etch described gate electrode film and grid oxygen film, until exposing described sealing coat
Till fin portion surface, form grid oxide layer and grid layer.
Optionally, the material of described grid oxide layer is silicon oxide；The material of described grid layer is polysilicon.
Optionally, after forming source region and drain region, also include: at described insulation surface and fin
The sidewall in portion and top surface form dielectric layer, and described dielectric layer flushes with the top surface of grid structure；
Remove described grid layer, in described dielectric layer, form opening；High-k gate dielectric is formed in described opening
Layer；The metal gate filling full described opening is formed on described high-k gate dielectric layer surface.
Compared with prior art, technical scheme has the advantage that
In the method for the present invention, described boundary layer for protecting fin when described fin carries out ion implanting
Sidewall that portion exposes and top surface.Described boundary layer can be removed by described dry etch process,
Etching gas yet with described dry etch process includes that fluoro-gas, described fluoro-gas easily exist
After described etching technics, easily remain fluorion in described fin portion surface, and described fluorion easily draws
Play the reunion of other etch by-products, cause the rough surface of fin.Therefore, described boundary layer is being removed
Afterwards, need to remove fin sidewall and the fluorion of top surface by process of surface treatment；Described surface
Process the gas of technique include nitrogenous gas, described nitrogenous gas can interrupt fluorion and fin portion surface it
Between chemical bond, and fluorion and etch by-products are taken away by the gas of described process of surface treatment.
Thus, surface treated fin portion surface is smooth, the fluorion of described fin portion surface attachment and etching pair
Product reduces, beneficially the carrying out of subsequent technique, and the transistor performance formed with described fin strengthens,
Reliability improves.
Further, sidewall and top surface to described fin carry out plasma-treating technology, described etc.
Gas ions processes the gas of technique and includes N2O、N2, one or more in NO.Wherein, described grade from
After the gas of daughter process technique is in plasma, it is possible to produce Nitrogen ion, by described Nitrogen ion
Sidewall and top surface to described fin bombard, it is possible to the chemistry between fluorion and fin portion surface
Key such that it is able to make fluorion and etch by-products and the fin portion surface reunited occurs around fluorion
Depart from, and make described fluorion be taken away by the gas of described plasma-treating technology with etch by-products.
Further, N is included when the gas of described plasma-treating technology2During O or NO, described grade from
Daughter processes sidewall that technique exposes at described fin and top surface forms oxide layer, described oxide layer
The etch by-products oxidation that the gas of technique is taken away can be plasma treated by failing.Described grade from
After daughter processes technique, then wet processing process is used to remove described oxide layer, it is possible to remove further
It is attached to the etch by-products of fin portion surface.It is additionally, since in described plasma-treating technology formation
Oxidated layer thickness less than described boundary layer, described oxide layer is easily removed by wet processing process, and not
Easily fin portion surface is caused damage.
Further, after described process of surface treatment, in described insulation surface and the side of fin
Wall and top surface are developed across the grid structure of described fin；Described grid structure includes being positioned at sealing coat
Surface and the sidewall of fin and the grid oxide layer of top surface and be positioned at the grid layer on grid oxide layer surface；By
The gas processed in described surface includes nitrogenous gas, is carrying out sidewall and the top surface of described fin
After process of surface treatment, it is possible at sidewall and top surface residual nitrogen ion, the described Nitrogen ion of fin
To improve the dielectric constant of described grid oxide layer, described grid oxide layer can be reduced to described grid oxide layer internal diffusion
Equivalent oxide (EOT) thickness.It is thus possible to make the fin field effect crystal formed with described fin
The performance improvement of pipe.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of a kind of fin formula field effect transistor of the embodiment of the present invention；
Fig. 2 to Fig. 8 is the cross-sectional view of the forming process of the semiconductor structure of the embodiment of the present invention.
Detailed description of the invention
As stated in the Background Art, the performance of the formed fin formula field effect transistor of prior art is bad, reliable
Property is poor.
Refer to the cross-section structure of a kind of fin formula field effect transistor that Fig. 1, Fig. 1 are the embodiment of the present invention show
It is intended to, including: Semiconductor substrate 100；It is positioned at the fin 101 on Semiconductor substrate 100 surface；It is positioned at half
The dielectric layer 102 on conductor substrate 100 surface, the side of fin 101 described in described dielectric layer 102 covering part
Wall, and dielectric layer 102 surface is less than fin 101 top；It is positioned at dielectric layer 102 surface and fin
The top of 101 and the grid structure 103 of sidewall surfaces；It is positioned at the fin 101 of described grid structure 103 both sides
Interior source region 104a and drain region 104b.
Wherein, described before fin 101 surface forms grid structure 103, in addition it is also necessary to described fin
101 carry out well region injection technology, to form well region in described fin 101.Secondly, in order to regulate fin
The threshold voltage size that channel region in 101 is opened, additionally it is possible to before forming described grid structure 103,
Threshold voltage adjustments ion is injected in described fin 101.Additionally, the contracting of the size along with fin 101
Little, the dopant ion concentration in described source region 104a and drain region 104b is higher so that described source region 104a
It is more easy to contact with each other because of the diffusion of dopant ion with drain region 104b, thus causes source region 104a and drain region
Short circuit between 104b；Therefore, before forming described grid structure 103, in addition it is also necessary at fin 101
Interior injection channel region non-proliferation ion, mutually expands hindering the dopant ion in source region 104a and drain region 104b
Dissipate.
Due to above-mentioned well region injection technology, the injection of threshold voltage adjustments ion or channel region non-proliferation from
The injection of son was all carried out before forming grid structure 103, therefore easily fin portion surface was caused damage.
In order to solve the problems referred to above, it is possible to carry out well region injection technology, the injection of threshold voltage adjustments ion or
Before the injection of person's channel region non-proliferation ion, the sidewall exposed at fin 101 and top surface are formed
Oxide layer, the surface of fin can be protected by described oxide layer, to reduce the damage to fin 101.
Further, after completing ion implantation technology, it is possible to remove described oxygen by isotropic etching technics
Change layer, to carry out being subsequently formed the processing step of grid structure 103.
The described isotropic etching technics removing removing oxide layer includes wet-etching technology and dry etching work
Skill；Described isotropic dry etch process is SiCoNi etching technics.Described SiCoNi etches work
Skill is compared to wet-etching technology, and sidewall and top surface for fin 101 have more accurate and homogeneous
Etch rate, and the damage for fin 101 is less.
But, owing to the etching gas of SiCoNi etching technics is fluoro-gas, remove fin 101 in etching
After the oxide layer on surface, easily at the remained on surface fluorion of fin 101；When described fin 101
When material is monocrystal silicon, described fluorion is easily bonded formation F-Si key with the silicon ion on fin 101 surface；
And, when fluorion and silicon ion occur bonding, it is also easy to attract described SiCoNi etching technics produces
Raw impurity is reunited, thus causes the surface attachment of fin 101 to have impurity, makes described fin 101
Rough surface.When the follow-up sidewall in described fin 101 and top surface formed grid structure 103 it
After, second-rate at grid structure 103 and the contact interface of fin 101, make formed fin field imitate
The performance answering transistor is the best.
In order to solve the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including: carry
For substrate, described substrate surface has fin and sealing coat, and described sealing coat is positioned at the part of described fin
Sidewall surfaces, the surface of described sealing coat less than the top surface of described fin, the sidewall of described fin and
Top surface has boundary layer；Dry etch process is used to remove described boundary layer, described dry etching work
The gas of skill includes fluoro-gas；After removing described boundary layer, sidewall and the top to described fin
Surface carries out process of surface treatment, and the gas that described surface processes includes nitrogenous gas.
Wherein, described boundary layer for protecting fin to expose when described fin is carried out ion implanting
Sidewall and top surface.Described boundary layer can be removed, yet with institute by described dry etch process
The etching gas stating dry etch process includes fluoro-gas, and described fluoro-gas is easily in described etching work
After skill, easily remain fluorion in described fin portion surface, and described fluorion easily causes other to etch
The reunion of by-product, causes the rough surface of fin.Therefore, after removing described boundary layer, need
Fin sidewall and the fluorion of top surface is removed by process of surface treatment；Described process of surface treatment
Gas includes that nitrogenous gas, described nitrogenous gas can interrupt the chemical bond between fluorion and fin portion surface,
And fluorion and etch by-products are taken away by the gas of described process of surface treatment.Thus, Jing Guobiao
The fin portion surface that face processes is smooth, and fluorion and the etch by-products of the attachment of described fin portion surface reduce, and have
It is beneficial to the carrying out of subsequent technique, and the transistor performance formed with described fin strengthens, reliability improves.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Fig. 2 to Fig. 8 is the cross-sectional view of the forming process of the semiconductor structure of the embodiment of the present invention.
Refer to Fig. 2, it is provided that substrate 200, described substrate 200 surface has fin 201 and sealing coat 202,
Described sealing coat 202 is positioned at the partial sidewall surface of described fin 201, the surface of described sealing coat 202
Top surface less than described fin 201.
In the present embodiment, described substrate 200 includes first area 210 and second area 220；Described
One region 210 is used for being formed PMOS transistor, and described second area 220 is used for forming NMOS crystal
Pipe.
In the present embodiment, described fin 201 and substrate 200 are formed by etching semiconductor substrate.Institute
The forming step stating substrate 200 and fin 201 includes: provide semiconductor base；Described semiconductor-based
Basal surface forms mask layer, and described mask layer covers the semiconductor substrate surface needing to form fin 201；
With described mask layer as mask, etch described semiconductor base, in described semiconductor base, form groove,
Form substrate 200 and be positioned at the fin 201 on substrate 200 surface；After forming described fin 201,
Remove described mask layer.In other embodiments, additionally it is possible to after being subsequently formed described sealing coat 202,
Remove described mask layer.
Described semiconductor base is body substrate or semiconductor-on-insulator (SOI) substrate；Described body substrate is
Silicon substrate, germanium substrate and silicon-Germanium substrate；Described semiconductor-on-insulator substrate be silicon-on-insulator substrate or
Germanium substrate on insulator.In the present embodiment, described semiconductor base is monocrystalline substrate, the most described fin
The material of portion 201 and substrate 200 is monocrystal silicon.
In order to reduce the distance between size and the adjacent fin of described fin 201, described mask layer
Multiple graphical masking process can be used to be formed.Described multiple graphical masking process includes: autoregistration
Dual graphing (Self-aligned Double Patterned, SaDP) technique, autoregistration are triple graphically
(Self-aligned Triple Patterned) technique or graphical (the Self-aligned Double of autoregistration quadruple
Double Patterned, SaDDP) technique.
In one embodiment, the formation process of described mask layer is self-alignment duplex pattern metallization processes, including:
At semiconductor substrate surface deposited sacrificial film；Patterned photoresist layer is formed on described expendable film surface；
With described photoresist layer as mask, etch described expendable film till exposing semiconductor substrate surface,
Form sacrifice layer, and remove photoresist layer；At semiconductor base and sacrificial layer surface deposition of mask material film；
It is etched back to described mask material film till exposing sacrifice layer and semiconductor substrate surface, at sacrifice layer
The semiconductor substrate surface of both sides forms mask layer；Described be etched back to technique after, remove described sacrifice
Layer.
In another embodiment, described semiconductor base can also be semiconductor-on-insulator substrate；Described
Semiconductor-on-insulator substrate includes: substrate, is positioned at the insulating barrier of substrate surface, is positioned at surface of insulating layer
Semiconductor layer.The formation process of described fin 201 includes: form mask layer in semiconductor layer surface；
With described mask layer for mask etching semiconductor layer till exposing surface of insulating layer, formed and be positioned at absolutely
Fin 201 in edge layer, described substrate forms substrate 200.
In other embodiments, described fin 201 is formed at the quasiconductor on substrate 200 surface by etching
Layer is formed, and described semiconductor layer uses selective epitaxial depositing operation to be formed at described substrate 200 surface.
Described substrate 200 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, insulator
Upper germanium substrate, glass substrate or III-V substrate, such as gallium nitride substrate or gallium arsenide substrate etc.,
The selection of described semiconductor base is unrestricted, it is possible to chooses and is suitable to process requirements or partly leading of being easily integrated
Body substrate.The material of described semiconductor layer is silicon, germanium, carborundum or SiGe, therefore, and the fin formed
Portion 201 material is unrestricted, it is possible to meet multiple process requirements, and the thickness energy of described semiconductor layer
Enough it is controlled by epitaxy technique, thus accurately controls the height of the fin 201 formed.
Described sealing coat 202 is for isolating adjacent fin 201, so that the active area in fin 201
Mutually isolated.The material of described sealing coat 202 is silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric
Material (dielectric constant more than or equal to 2.5, less than 3.9), (dielectric constant is little for ultralow K dielectric material
In 2.5) in one or more combination.In the present embodiment, the material of described sealing coat 202 is silicon oxide.
The forming step of described sealing coat 202 includes: formed at described substrate 200 and fin 201 surface
Isolating membrane；Planarize described isolating membrane till exposing the top surface of described fin 201；Flat
After the described isolating membrane of smoothization, it is etched back to described isolating membrane, exposes part fin 201 sidewall surfaces,
Form sealing coat 202.
The formation process of described isolating membrane is chemical vapor deposition method or physical gas-phase deposition, such as
Fluid chemistry vapour deposition (FCVD, Flowable Chemical Vapor Deposition) technique, etc. from
Daughter strengthens chemical vapor deposition method or high-aspect-ratio chemical vapor deposition method (HARP)；Described flat
Smooth metallization processes is CMP process；The described technique that is etched back to is anisotropic dry etch process.
In the present embodiment, the formation process of described isolating membrane is fluid chemistry gas-phase deposition, uses described stream
The isolating membrane that body chemical vapor phase growing technique is formed is prone to be packed in the groove between adjacent fin 201,
Can make formed isolating membrane even compact, then sealing coat 202 isolation performance formed is good.
In one embodiment, in order to avoid planarizing the chemically mechanical polishing of described isolating membrane to fin 201
Top surface cause damage, additionally it is possible to formed before isolating membrane, at substrate 200 and fin 201 table
Face forms polishing stop layer, and the material of described polishing stop layer is different from the material of isolating membrane, when describedization
After mechanical polishing process exposes described polishing stop layer, described polishing stop layer was carried out polishing
Or wet-etching technology, to expose the top surface of described fin 201.
Refer to Fig. 3, sidewall and top surface at described fin 201 form boundary layer 203.
Described boundary layer 203 for follow-up described fin 201 is carried out ion implantation technology time, protection
The sidewall of described fin 201 and top surface, reduce described fin 201 sidewall and top surface is subject to
Damage.Owing to described boundary layer 203 is used for protecting described fin 201, the most described boundary layer 203 is rear
Can sustain damage in continuous ion implantation technology, described boundary layer 203 is unfavorable for being subsequently formed grid structure,
Therefore, before being subsequently formed grid structure, need to remove described boundary layer 203.
In the present embodiment, the material of described boundary layer 203 is silicon oxide.The thickness of described boundary layer 203
Degree is 10 angstroms～30 angstroms；The thickness of described boundary layer 203 is unsuitable blocked up, and follow-up being difficult to thoroughly is removed
Described boundary layer 203, easily at sidewall or the material of top surface residual boundary layer 203 of fin 203,
Then the degradation of formed fin formula field effect transistor is made；The thickness of described boundary layer 203 is the most not
Suitable or thin, the otherwise protective layer scarce capacity to fin 203 sidewall and top surface, described fin 203
Sidewall and top surface still be easily subject to damage.
The formation process of described boundary layer 203 is oxidation technology or depositing operation, and described oxidation technology can
For thermal oxidation technology or chemical oxidation process；Described depositing operation can be chemical vapor deposition method, thing
Physical vapor deposition technique or atom layer deposition process；The boundary layer 203 using depositing operation to be formed is also located at
Described sealing coat 202 surface.In the present embodiment, the formation process of described boundary layer 203 is atomic layer
Depositing operation；Boundary layer 203 thickness using atom layer deposition process to be formed uniformly and has good
Gradient coating performance, described boundary layer can be in close contact with the sidewall of fin 201 and top surface.
Refer to Fig. 4, after forming described boundary layer 203, in described fin 201, carry out ion note
Enter technique；Use the ion that annealing process is injected in activating fin 201.
The ion implantation technology carried out in described fin 201 includes that channel region stops injection, threshold value regulation
One or more in injection, well region injection.Described well region injects for forming well region in fin 201；
In the present embodiment, described first area 210 is used for forming PMOS transistor, in first area 210
Fin 201 in well region inject ion be N-type ion；Described second area 220 is used for forming NMOS
Transistor, the ion that well region injects in the fin 201 of described second area 220 is p-type ion.Institute
Stating threshold value regulation to inject for injecting threshold voltage adjustments ion in fin 201, described threshold voltage is adjusted
The cut-in voltage of the channel region being formed in fin 201 can be adjusted, to meet fin by joint ion
The technical need of field-effect transistor.Described channel region stop inject ion for stop be subsequently formed in
Source region in fin 201 and the ion in drain region spread towards channel region, thus avoid source region and drain region to occur
Short circuit；Described channel region stops that the ion injected is contrary with the ionic conduction type in described source region and drain region.
In the present embodiment, first area 210 is used for being formed PMOS transistor, and second area 220 is used
In forming nmos pass transistor, therefore, the fin 201 of first area 210 and second area 220 injects
Ion different.
The step carrying out ion implantation technology in described fin 201 includes: in described first area 210
Sealing coat 202 and fin 201 surface form the first patterned layer；With described first patterned layer for covering
Film, carries out the first ion implantation technology to second area 220；After described first ion implantation technology,
Remove described first patterned layer；After removing described first patterned layer, at described second area 220
Sealing coat 202 and fin 201 surface formed second graphical layer；With described second graphical layer mask,
First area 210 is carried out the second ion implantation technology.
Described first ion implantation technology and the second ion implantation technology include that channel region stops injection, threshold value
One or more in regulation injection, well region injection.Described first patterned layer and second graphical layer are
Patterned photoresist layer, the photoresist layer of described patterned layer uses coating process and exposure imaging work
Skill is formed.
Refer to Fig. 5, use dry etch process 240 to remove described boundary layer 203 (as shown in Figure 4),
The gas of described dry etch process includes fluoro-gas.
In the present embodiment, before removing boundary layer 203, described second graphical layer is removed；Due to
Described second graphical layer is patterned photoresist layer, and the technique removing second graphical layer is that wet method is gone
Adhesive process or cineration technics.
Owing to described boundary layer 203 is during carrying out ion implantation technology to fin 201, it is used for protecting
Protecting fin 201 sidewall higher than sealing coat 202 and top surface, the most described boundary layer 203 is described
Can be consumed during ion implantation technology, the poor surface quality of boundary layer 203, in uneven thickness,
Therefore, before being subsequently formed grid structure, need to remove described boundary layer 203.
The dry etch process removing described boundary layer 203 is isotropic etching technics, described respectively to
The etching technics of same sex etch rate in all directions is closer to such that it is able to removes simultaneously and is positioned at
The boundary layer 203 of fin 201 sidewall surfaces and top surface.
In the present embodiment, the material of described boundary layer 203 is silicon oxide, removes described boundary layer 203
Dry etch process be SiCoNi etching technics.The parameter of described SiCoNi etching technics includes: merit
Rate 10W～100W, frequency is less than 100kHz, and etching temperature is 40 degrees Celsius～80 degrees Celsius, and pressure is
0.5 torr～50 torr, etching gas includes NH3、NF3, He, wherein, NH3Flow be 0sccm～500sccm,
NF3Flow be 20sccm～200sccm, the flow of He is 400sccm～1200sccm, NF3With NH3
Flow-rate ratio be 1:20～5:1.
Described SiCoNi etching technics is in addition on each different directions, etch rate is homogeneous, described
The etch rate of SiCoNi etching technics is relatively slow, and the etch rate of the most relatively wet-etching technology is slow, because of
The etch thicknesses of this described dry etch process the most accurately controls；And, described SiCoNi etches work
Skill is little to the surface damage of fin 206a, is conducive to, after removing boundary layer 203, reducing fin
The sidewall of 201 and the damage of top surface, reduction roughness.
But, owing to the etching gas of described SiCoNi etching technics includes fluoro-gas, such as NF3,
Described fluoro-gas is after etching interface layer 203, easily at described fin 201 remained on surface fluorion,
And described fluorion is easily and the semi-conducting material ionic bonding on fin 201 surface, form stable chemistry
Key.In the present embodiment, the material of described fin 201 is monocrystal silicon, at described SiCoNi etching technics
Afterwards, the fluorion residuing in fin 201 surface can be bonded with the silicon ion on fin 210 surface, is formed
F-Si key.
It is additionally, since during described SiCoNi etching technics etching interface layer 203, also can produce
Other etch by-products, and during described fluorion is bonded with silicon ion, easily attract other to carve
Erosion by-product is reunited around F-Si key, thus easily causes after removing boundary layer 203,
The sidewall of fin 201 and top surface attachment impurity so that the surface of fin 201 is the most coarse.If
After using described SiCoNi etching technics, directly form grid structure in fin 201 surface, then described
Interfacial state at grid structure and the contact interface of fin 201 is poor, easily makes formed fin field imitate
Answer the degradation of transistor.Persistently reduce especially with dimensions of semiconductor devices, described fin 201
Size reduce the most accordingly, fin 201 width in the present embodiment is 14 nanometers～20 nanometers, the most attached
The impurity in fin 201 surface and the roughness on fin 201 surface is affected bigger, thus to being formed
Transistor performance impact bigger.
Therefore, the present embodiment removing after described boundary layer 203, to the sidewall of described fin 201 and
Top surface carries out process of surface treatment, to remove the fluorion of fin 201 surface attachment, reduces with this
The roughness on fin 201 surface.Described process of surface treatment includes plasma-treating technology, described etc.
Gas ions processes the gas of technique and includes nitrogenous gas.Hereinafter described process of surface treatment will be illustrated.
Refer to Fig. 6, sidewall and top surface to described fin 201 carry out plasma-treating technology.
The gas of described plasma-treating technology is nitrogenous gas, and described nitrogenous gas is in plasma
Afterwards, it is possible to produce Nitrogen ion, with described Nitrogen ion, the surface of fin 201 is bombarded, it is possible to will
Chemical bond between fluorion and fin 201 surfacing ion interrupts, and can make fluorion and
Other etch by-products reunited is plasma treated the gas of technique and takes away, thus reduces fin 201
The roughness on surface.
Secondly, use after fin 201 surface is bombarded by described Nitrogen ion, it is possible at described fin
Portion 201 remained on surface Nitrogen ion, when the follow-up sidewall at described fin 201 and top surface are developed across
After the grid structure of described fin 201, the Nitrogen ion residuing in fin 201 surface can be tied to grid
Grid oxide layer in structure or gate dielectric layer internal diffusion so that the dielectric constant (k) of grid oxide layer or gate dielectric layer carries
Height, the equivalent oxide thickness of described grid oxide layer or gate dielectric layer reduces, and the fin field effect formed is brilliant
The performance of body pipe improves.
The parameter of described plasma-treating technology includes: gas includes N2O、N2, one in NO or
Multiple, power is 300 watts～1500 watts, and pressure is 10 millitorrs～100 millitorrs, and flow is
20sccm～～300sccm.
In the present embodiment, the gas of described plasma-treating technology includes N2O or NO, by described
N2After O or NO is plasmarized, additionally it is possible to producing oxonium ion, described oxonium ion can be at fin 201
Surface form oxide layer 204, the fluorion that the gas failing to be plasma treated technique is taken away or its
Its etch by-products oxidation；Follow-up can remove described oxide layer 204 by wet-etching technology.
The thickness of described oxide layer 204 is 5 angstroms～10 angstroms.The thickness of described oxide layer 204 is less than described boundary
The thickness of surface layer 203, the very thin thickness of described oxide layer 204, the most described oxide layer 204 be prone to by
Remove, and damage will not be caused in fin 201 surface.
The energy entrained by produced Nitrogen ion of described plasma-treating technology is unsuitable excessive, otherwise
Easily damage is caused on fin 201 surface；And the produced Nitrogen ion of described plasma-treating technology
Entrained energy is also unsuitable too small, otherwise cannot interrupt F-Si key.
In other embodiments, the gas of described plasma-treating technology includes N2, then described grade from
After daughter processes technique, the surface of fin 201 will not form oxide layer, therefore, at described plasma
After body processes technique, it is not necessary to use wet-etching technology to remove described oxide layer.
Refer to Fig. 7, after described plasma-treating technology, use wet processing process to remove institute
State oxide layer 204.
In the present embodiment, the material of described oxide layer 204 is silicon oxide, the quarter of described wet processing process
Erosion liquid is hydrofluoric acid solution；In described hydrofluoric acid solution the volume ratio of water and Fluohydric acid. be 20:1～～200:1,
The concentration of described hydrofluoric acid solution is relatively low.Due to the very thin thickness of described oxide layer 204, therefore, it is possible to
Described oxide layer is removed with the hydrofluoric acid solution of low concentration.And, when the concentration of described hydrofluoric acid solution
Time relatively low, fin 201 surface is not resulted in damage.Additionally, due to the concentration of described hydrofluoric acid solution
Relatively low, less to the thinning of described sealing coat 202 and damage.Therefore, described oxide layer 204 is being removed
Afterwards, described fin 201 surface topography is good.
Refer to Fig. 8, after described process of surface treatment, at described sealing coat 202 surface and fin
The sidewall in portion 201 and top surface are developed across the grid structure (sign) of described fin 201；?
Source region and drain region (sign) is formed in the fin 201 of described grid structure both sides.
In the present embodiment, before forming described grid structure, to described sealing coat 202 and fin 201
Surface carries out pre-cleaning processes, and described pre-cleaning processes is used for removing sealing coat 202 and fin 201 surface
The by-products such as the polymer of attachment.
Described grid structure includes being positioned at sealing coat 202 surface and the sidewall of fin 201 and top surface
Grid oxide layer 205, it is positioned at the grid layer 206 on grid oxide layer 205 surface and is positioned at grid oxide layer 205 and grid
The side wall of layer 206 sidewall surfaces.
The forming step of described grid oxide layer 205 and grid layer 206 includes: on described sealing coat 202 surface
And the sidewall of fin 201 and top surface form grid oxygen film；Gate electrode film is formed on described grid oxygen film surface；
Form patterned layer on described gate electrode film surface, described patterned layer covers to be needed to form grid layer 206
Corresponding region；With described patterned layer as mask, etch described gate electrode film and grid oxygen film, until exposing
Till described sealing coat 202 and fin 201 surface, form grid oxide layer 205 and grid layer 206.
The material of described grid oxide layer 205 is silicon oxide；Described grid oxygen film can be formed with thermal oxidation technology,
Atom layer deposition process is formed or chemical vapor deposition method is formed.The material of described grid layer 206 is many
Crystal silicon.In the present embodiment, described grid structure is dummy gate structure, and follow-up needs removes described grid
Layer 206, and substitute with high-k gate dielectric layer and metal gate.In another embodiment, described grid structure
Being directly used in formation transistor, the most described grid oxide layer 205 is as gate dielectric layer.
In the present embodiment, after forming source region and drain region, also include: at described sealing coat 202 table
Face and the sidewall of fin 201 and top surface form dielectric layer, described dielectric layer and grid structure
Top surface flushes；Remove described grid layer 206, in described dielectric layer, form opening；At described opening
Interior formation high-k gate dielectric layer；The metal filling full described opening is formed on described high-k gate dielectric layer surface
Grid.
In the present embodiment, nitrogenous gas is included due to the gas of described plasma-treating technology, it is possible to
At the remained on surface Nitrogen ion of fin 201, described Nitrogen ion can be to described grid oxide layer 205 and high k grid
Dielectric layer internal diffusion so that the dielectric constant of grid oxide layer 205 and high-k gate dielectric layer improves, equivalent oxide
Layer thickness reduces so that the transistor performance of formation improves.
In the present embodiment, the fin formula field effect transistor formed is for forming input and output (IO) electricity
Lu Shi, therefore, the running voltage of the fin formula field effect transistor formed is higher, then grid oxide layer 205
Equivalent oxide thickness reduces the performance improvement to transistor and becomes apparent from.
Additionally, when the transistor formed is PMOS transistor, due to the material of described grid oxide layer 205
Material is changed into silicon oxynitride by silicon oxide, the dielectric constant of grid oxide layer 205 and high-k gate dielectric layer improves,
Equivalent oxide thickness reduces, it is possible to make the Negative Bias Temperature Instability (NBTI) of PMOS transistor
Problem is inhibited so that the performance of PMOS transistor is more preferably.
To sum up, in the present embodiment, described boundary layer is used for the protection when described fin carries out ion implanting
Sidewall that fin exposes and top surface.Described boundary layer can be removed by described dry etch process,
Etching gas yet with described dry etch process includes that fluoro-gas, described fluoro-gas easily exist
After described etching technics, easily remain fluorion in described fin portion surface, and described fluorion easily draws
Play the reunion of other etch by-products, cause the rough surface of fin.Therefore, described boundary layer is being removed
Afterwards, need to remove fin sidewall and the fluorion of top surface by process of surface treatment；Described surface
Process the gas of technique include nitrogenous gas, described nitrogenous gas can interrupt fluorion and fin portion surface it
Between chemical bond, and fluorion and etch by-products are taken away by the gas of described process of surface treatment.
Thus, surface treated fin portion surface is smooth, the fluorion of described fin portion surface attachment and etching pair
Product reduces, beneficially the carrying out of subsequent technique, and the transistor performance formed with described fin strengthens,
Reliability improves.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a semiconductor structure, it is characterised in that including:
Thering is provided substrate, described substrate surface has fin and sealing coat, and described sealing coat is positioned at described fin
Partial sidewall surface, the surface of described sealing coat less than the top surface of described fin, described fin
Sidewall and top surface have boundary layer；
Using dry etch process to remove described boundary layer, the gas of described dry etch process includes fluorine-containing
Gas；
After removing described boundary layer, sidewall and top surface to described fin carry out surface science and engineering
Skill, the gas that described surface processes includes nitrogenous gas.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described boundary layer
Material is silicon oxide；The thickness of described boundary layer is 10 angstroms～30 angstroms.
3. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that remove described interface
The dry etch process of layer is SiCoNi etching technics.
4. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that described SiCoNi
The parameter of etching technics includes: power 10W～100W, and frequency is less than 100kHz, and etching temperature is
40 degrees Celsius～80 degrees Celsius, pressure is 0.5 torr～50 torr, and etching gas includes NH3、NF3, He,
Wherein, NH3Flow be 0sccm～500sccm, NF3Flow be 20sccm～200sccm, He
Flow be 400sccm～1200sccm, NF3With NH3Flow-rate ratio be 1:20～5:1.
5. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described surface processes
The step of technique includes: sidewall and top surface to described fin carry out plasma-treating technology.
6. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that described plasma
The parameter processing technique includes: gas includes N2O、N2, one or more in NO, power is
300 watts～1500 watts, pressure is 10 millitorrs～100 millitorrs, and flow is 20sccm～～300sccm.
7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that when described plasma
Body processes the gas of technique and includes N2During O or NO, described plasma-treating technology is at described fin
The sidewall exposed and top surface form oxide layer.
8. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that described surface processes
The step of technique also includes: after described plasma-treating technology, uses wet processing process
Remove described oxide layer.
9. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that described wet treatment
The liquid of technique is hydrofluoric acid solution；In described hydrofluoric acid solution, the volume ratio of water and Fluohydric acid. is
20:1～～200:1.
10. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that described oxide layer
Thickness is less than the thickness of described boundary layer；The thickness of described oxide layer is 5 angstroms～10 angstroms.
The forming method of 11. semiconductor structures as claimed in claim 1, it is characterised in that also include: in institute
After stating process of surface treatment, described sealing coat and fin portion surface are carried out pre-cleaning processes.
The forming method of 12. semiconductor structures as claimed in claim 1, it is characterised in that forming described boundary
After surface layer, before removing described boundary layer, in described fin, carry out ion implantation technology；Use
The ion that annealing process is injected in activating fin.
The forming method of 13. semiconductor structures as claimed in claim 12, it is characterised in that in described fin
During the ion implantation technology carried out includes that channel region stops that injection, threshold value regulation injection, well region inject
One or more.
The forming method of 14. semiconductor structures as claimed in claim 1, it is characterised in that described substrate and fin
The forming step in portion includes: provide semiconductor base；Mask layer is formed at described semiconductor substrate surface,
Described mask layer covers the semiconductor substrate surface needing to form fin；With described mask layer as mask,
Etch described semiconductor base, in described semiconductor base, form groove, form substrate and be positioned at
The fin of substrate surface.
The forming method of 15. semiconductor structures as claimed in claim 1, it is characterised in that described sealing coat
Forming step includes: form isolating membrane at described substrate and fin portion surface；Planarize described isolating membrane straight
To the top surface exposing described fin；After planarizing described isolating membrane, it is etched back to institute
State isolating membrane, expose part fin sidewall surfaces, form sealing coat.
The forming method of 16. semiconductor structures as claimed in claim 1, it is characterised in that in described surface
After science and engineering skill, it is developed across institute at described insulation surface and the sidewall of fin and top surface
State the grid structure of fin；Source region and drain region is formed in the fin of described grid structure both sides.
The forming method of 17. semiconductor structures as claimed in claim 16, it is characterised in that described grid structure
Including the sidewall and top surface being positioned at insulation surface and fin grid oxide layer, be positioned at grid oxide layer surface
Grid layer and be positioned at grid oxide layer and the side wall of grid layer sidewall surfaces.
The forming method of 18. semiconductor structures as claimed in claim 17, it is characterised in that described grid oxide layer and
The forming step of grid layer includes: in described insulation surface and the sidewall of fin and top surface shape
Become grid oxygen film；Gate electrode film is formed on described grid oxygen film surface；Formed graphically on described gate electrode film surface
Layer, described patterned layer covers the corresponding region needing to form grid layer；With described patterned layer for covering
Film, etches described gate electrode film and grid oxygen film, till exposing described sealing coat and fin portion surface,
Form grid oxide layer and grid layer.
The forming method of 19. semiconductor structures as claimed in claim 17, it is characterised in that described grid oxide layer
Material is silicon oxide；The material of described grid layer is polysilicon.
The forming method of 20. semiconductor structures as claimed in claim 19, it is characterised in that formed source region and
After drain region, also include: formed at described insulation surface and the sidewall of fin and top surface
Dielectric layer, described dielectric layer flushes with the top surface of grid structure；Remove described grid layer, in institute
Opening is formed in stating dielectric layer；High-k gate dielectric layer is formed in described opening；It is situated between at described high k grid
Matter layer surface forms the metal gate filling full described opening.
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