CN106611709B - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN106611709B CN106611709B CN201510666124.8A CN201510666124A CN106611709B CN 106611709 B CN106611709 B CN 106611709B CN 201510666124 A CN201510666124 A CN 201510666124A CN 106611709 B CN106611709 B CN 106611709B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 118
- 125000006850 spacer group Chemical group 0.000 claims abstract description 71
- 238000005530 etching Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 32
- 230000008021 deposition Effects 0.000 claims abstract description 12
- 238000000926 separation method Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 189
- 239000011229 interlayer Substances 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000012212 insulator Substances 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 239000006117 anti-reflective coating Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 239000005049 silicon tetrachloride Substances 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- XSKXPHGJRMYISG-UHFFFAOYSA-N [Si](OCC)(OCC)(OCC)OCC.[P] Chemical compound [Si](OCC)(OCC)(OCC)OCC.[P] XSKXPHGJRMYISG-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 125000003963 dichloro group Chemical group Cl* 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, electronic device.The method includes the steps S1: providing semiconductor substrate, is formed with several gate stacks on the semiconductor substrate, the gate stack includes the floating gate stacked gradually, separation layer, control gate and mask layer；Step S2: sequentially forming the first spacer material layer and the second spacer material layer in the semiconductor substrate and the gate stack, to cover the gate stack, wherein the first spacer material layer choosing oxide；Step S3: etching the second spacer material layer, to expose the first spacer material layer in the semiconductor substrate the and described mask layer upper portion side wall；Step S4: the first spacer material layer that etching removal is exposed, to form clearance wall on the side wall of the gate stack；Step S5: deposition stop-layer, to cover the clearance wall and the mask layer.The method further improves the yield and performance of NOR flash memory.
Description
Technical field
The present invention relates to semiconductor devices, in particular it relates to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technique
With high speed development (such as mobile phone, digital camera, MP3 player and the PDA of portable electronic device
Deng), the requirement for data storage is higher and higher.Nonvolatile flash memory is due to the spy for remaining to save data under power blackout situation
Point becomes most important storage unit in these equipment, wherein since flash memory (flash memory) can achieve very high core
Piece storage density, and without introducing new material, manufacturing process is compatible, therefore, can be easier more reliable being integrated into and gather around
Have in digital and analog circuit.
NOR and NAND is that two kinds of main nonvolatile flash memory technologies, NOR flash memory (Flash) device belong to currently on the market
One kind of nonvolatile flash memory, its main feature is that executing in chip, such application program can directly be run in Flash flash memory, no
Code must be read in system RAM (random access memory) again, to make it have higher efficiency of transmission.
For NOR flash memory, wherein threshold voltage should be kept stable, and threshold voltage depends on the electricity in floating gate
Son is found by grid disturbed test, with the continuous reduction of dimensions of semiconductor devices, the threshold voltage stability of NOR flash memory
It being deteriorated, reason may be to damage when being formed between grid and forming contact hole opening to the clearance wall on the grid,
The performance of device is influenced, or even clearance wall is made to fail.
Therefore, it is necessary to be improved further to current described device and preparation method thereof, to eliminate the above problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to solve the problems in the existing technology, a kind of preparation method of semiconductor devices is provided, comprising:
Step S1: providing semiconductor substrate, is formed with several gate stacks on the semiconductor substrate, and the grid is folded
Layer includes floating gate, separation layer, control gate and the mask layer stacked gradually；
Step S2: the first spacer material layer and second are sequentially formed in the semiconductor substrate and the gate stack
Spacer material layer, to cover the gate stack, wherein the first spacer material layer choosing oxide；
Step S3: etching the second spacer material layer, to expose in the semiconductor substrate the and described exposure mask
The first spacer material layer in layer upper portion side wall；
Step S4: the first spacer material layer that etching removal is exposed, with the shape on the side wall of the gate stack
At clearance wall；
Step S5: deposition stop-layer, to cover the clearance wall and the mask layer.
Optionally, the etching selectivity of the first spacer material layer and the second spacer material layer is greater than 3.
Optionally, in the step S3, after etching the second spacer material layer, on the mask layer of exposing
The height of the first spacer material layer on portion's side wall is 800~1500 angstroms.
Optionally, the method may further comprise:
Step S6: interlevel dielectric deposition, to cover the gate stack；
Step S7: patterning the interlayer dielectric layer and using the stop-layer as etching stopping layer, with folded in the grid
Contact hole opening is formed between layer.
Optionally, in the step S1, it is also formed with gate dielectric on the semiconductor substrate, the grid is folded
Layer is located at the top of the gate dielectric.
Optionally, in the step S4, removal dew while removing the first spacer material layer of the exposing
The gate dielectric out.
Optionally, in the step S4, first gap of dry etching or wet etching removal exposing is selected
The wall material bed of material.
Optionally, the second spacer material layer choosing nitride；
The stop-layer selects nitride.
The present invention provides a kind of semiconductor devices being prepared based on above-mentioned method.
The present invention provides a kind of electronic devices, including above-mentioned semiconductor devices.
In order to solve the problems in the existing technology the present invention, provides a kind of preparation method of semiconductor devices,
Then the material layer for forming oxide (O) and nitride (N) in the method on the gate stack is etched to be formed
The clearance wall of ON clearance wall or ONON, and form stop-layer on the outside of the clearance wall, etching when using as etching contact hole
Stop-layer, is protected to be formed to the clearance wall, its cycle performance of the semiconductor devices being prepared by the method obtains
To being greatly improved, the threshold voltage stability of the device is higher, further improves the yield and performance of NOR flash memory.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 a-1e is the preparation process schematic diagram of semiconductor devices described in an embodiment of the present invention；
Fig. 2 is the preparation technology flow chart of semiconductor devices described in an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
Embodiment one
A kind of specific embodiment of the invention is illustrated with reference to the accompanying drawing, wherein Fig. 1 a-1e is the present invention one
The preparation process schematic diagram of semiconductor devices described in embodiment；Fig. 2 is semiconductor device described in an embodiment of the present invention
The preparation technology flow chart of part.
Firstly, executing step 101, semiconductor substrate 101 is provided, forms gate dielectric in the semiconductor substrate 101
Layer.
Firstly, a referring to Fig.1, wherein the semiconductor substrate 101 can be at least one in the following material being previously mentioned
Kind: silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator for silicon, silicon-on-insulator (SOI)
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.
In addition, active area can be defined in semiconductor substrate 101.It on the active region can also include that others have
Source device, for convenience, there is no indicate in shown figure.
Gate dielectric 102 is formed in the semiconductor substrate 101, wherein the gate dielectric 102 can be selected
Dielectric material commonly used in the art, such as oxide can be selected.
When selecting oxide as the gate dielectric 102, the forming method of the gate dielectric 102 can be
High-temperature oxydation or deposition method, it is not limited to which a certain method can according to need and be selected.
SiO is selected in the present invention2Layer is used as gate dielectric 102, and the thickness of the gate dielectric 102 can be 1-
20nm, but it is not limited solely to the thickness, those skilled in the art, which can according to need, to be adjusted, to obtain more preferable effect.
It is used as a kind of specific embodiment, the SiO in this step2The deposition method of layer can select thermal oxide, original
Sublayer deposition, chemical vapor deposition, electron beam evaporation or magnetically controlled sputter method.
Step 102 is executed, sequentially forms floating gate material layer, spacer material layer, control gate on the gate dielectric 102
Material layer and mask layer, and pattern the floating gate material layer, the spacer material layer, the control gate material layer and exposure mask
Layer, to form gate stack.
Specifically, as shown in Figure 1a, floating gate material layer is then formed on the gate dielectric 102, wherein described floating
Gate material layer selects semiconductor material, such as silicon, polysilicon or Ge etc., it is not limited to a certain material, the floating gate material
The deposition method of the bed of material can choose molecular beam epitaxy (MBE), Metallo-Organic Chemical Vapor deposition (MOCVD), low pressure chemical gas
Mutually one of deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG).
In this embodiment, the floating gate material layer of polysilicon is formed, the polysilicon selects epitaxy method to be formed, specifically
Ground is described further by taking silicon as an example in a particular embodiment, and reaction gas may include hydrogen (H2) carry silicon tetrachloride
(SiCl4) or trichlorosilane (SiHCl3), silane (SiH4) and dichloro hydrogen silicon (SiH2Cl2) etc. at least one of enter be placed with
The reaction chamber of silicon substrate carries out high-temperature chemical reaction in reaction chamber, siliceous reaction gas is made to restore or thermally decompose, generated silicon
Atom epitaxial growth in gate dielectric layer surface.
Further, spacer material layer is formed on the floating gate material layer, the spacer material layer can select this field
Common insulating materials, such as ONO (the structural insulation separation layer of oxidenitride oxide), but be not limited to that institute
State material.
Then control gate material layer is formed in the top of the spacer material layer, wherein the control gate material layer can be selected
With material identical with the floating gate material layer, different materials can also be selected, such as metal gates conduct can formed
Control gate.
Wherein, the mask layer can select hard mask layer, such as SiN or metal hard mask layer can be selected etc., and
It is not limited to a certain kind.
Pattern the patterning floating gate material layer, the spacer material layer, the control gate material layer and described
Mask layer, to form floating gate 103, separation layer 104, control gate 105 and mask layer 106, to form the gate stack.
Specifically patterning method includes but is not limited to following methods: forming organic distribution on the mask layer 106
Layer (Organic distribution layer, ODL), siliceous bottom antireflective coating (Si-BARC), described siliceous
The photoresist layer of deposit patterned on bottom antireflective coating (Si-BARC), or only formed in the control gate material layer
The photoresist layer patterned, pattern definition on the photoresist figure for the gate structure of being formed, then with described
Photoresist layer is mask layer or the lamination formed with the etching organic distribution layer, bottom antireflective coating, photoresist layer
For floating gate material layer, the spacer material layer described in mask etch, the control gate material layer and mask layer 106.
Then organic distribution layer (Organic distribution layer, ODL), siliceous bottom anti-reflective are removed
Penetrate coating (Si-BARC), photoresist layer.
In this step, dry etching, reactive ion etching (RIE), ion beam milling, plasma etching are selected.
Step 103 is executed, the first spacer material layer is sequentially formed in the semiconductor substrate and the gate stack
107 and the second spacer material layer 108, to cover the gate stack, wherein the first spacer material layer choosing aoxidizes
Object.
Specifically, as shown in Figure 1a, in this step, the first spacer material layer choosing oxide, described second
Spacer material layer 108 selects nitride, to form the clearance wall of oxide-nitride (ON) in subsequent steps.
Wherein, the etching selectivity of the first spacer material layer and the second spacer material layer is greater than 3.
It optionally, in this step can be with duplicate deposition the first spacer material layer 107 and the second clearance wall
Material layer 108, to form the clearance wall of oxidenitride oxide-nitride (ONON) in subsequent steps.
Multiple first spacer material layers 107 and the second spacer material layer 108 can be wherein formed in this step
Lamination, so that the performance of the NOR flash memory is more stable.
Execute step 104, etch the second spacer material layer 108, with expose it is in the semiconductor substrate and
The first spacer material layer 107 in mask layer upper portion side wall described in the gate stack.
Specifically, as shown in Figure 1 b, the second spacer material layer 108 is etched in this step, between described first
The gap wall material bed of material 107 is stop-layer, removes the second spacer material layer 108 in the horizontal direction, and etching
It is inevitably removed at the top of the mask layer in the process and the second spacer material layer 108 on top, but
The control gate will be at least completely covered in the second spacer material layer 108 on gate stack sidewall described in the step, i.e.,
The height of the second spacer material layer 108 cannot be below the top of the control gate.
Optionally, described in the mask layer upper portion side wall of exposing after etching the second spacer material layer
The height of first spacer material layer is 800~1500 angstroms, the control gate is at least completely covered.
Wherein, dry etching or wet etching are selected in this step, preferred C-F etchant loses in the present invention
It carves, the C-F etchant is CF4、CHF3、C4F8And C5F8One of or it is a variety of.In this embodiment, the dry etching
CF can be selected4、CHF3, in addition add N2、CO2One of as etching atmosphere, wherein gas flow be CF410-
200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure is 30-150mTorr, when etching
Between be 5-120s.
Execute step 105, the first spacer material layer that etching removal is exposed, to be formed on the gate stack
Clearance wall.
Specifically, as illustrated in figure 1 c, first gap wall material that etching removal is exposed at step 104 in this step
The bed of material, while removing the gate dielectric of exposing, for example, remove at the top of the mask layer and on side wall described first
Spacer material layer, to expose the mask layer, since second clearance wall is located at the top at the top of the control gate,
The the first spacer material layer and the second spacer material layer on control gate side wall will not be destroyed in this step.
Optionally, the institute outside gate stack described in the semiconductor substrate can also be removed in this step
Gate dielectric is stated, to expose the semiconductor substrate.
In this step, the first spacer material layer for selecting dry etching or wet etching removal to expose.
In one embodiment, N can choose2In conduct etch atmosphere, other a small amount of gas examples can also be added simultaneously
Such as CF4、CO2、O2, the etching pressure can be 50-200mTorr, it is chosen as 100-150mTorr, power 200-600W,
The etching period is 5-80s in the present invention, is chosen as 10-60s, while selecting biggish gas flow in the present invention,
It is 30-300sccm in the flow of N2 of the present invention, is chosen as 50-100sccm.
Step 106 is executed, stop-layer 109 is deposited, the clearance wall and the mask layer is completely covered.
Specifically, as shown in Figure 1 d, stop-layer 109 is deposited in this step, using as etching contact hole in subsequent step
The stop-layer of opening, while the protective layer as the clearance wall, it is right during etching forms contact hole opening to prevent
The clearance wall damages.
In this application since the clearance wall includes the oxide and nitride being sequentially depositing, while in the clearance wall
Outside be also formed with stop-layer as protective layer, avoid etching formed contact hole opening during to the clearance wall
It damages, its cycle performance of the semiconductor devices being prepared by the method is greatly improved, threshold voltage stabilization
Property is higher, further improves the yield and performance of NOR flash memory.
Execute step 107, interlevel dielectric deposition 110, to cover the gate stack；
Specifically, as shown in fig. le, the interlayer dielectric layer 110 can be silicon oxide layer, heavy including the use of thermal chemical vapor
What product (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process were formed has doped or undoped oxygen
The material layer of SiClx, such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).
In addition, the interlayer dielectric layer 110 is also possible to adulterate boron or adulterates the spin cloth of coating-type glass (spin-on- of phosphorus
Glass, SOG), doping phosphorus tetraethoxysilane (PTEOS) or boron-doped tetraethoxysilane (BTEOS).
Step 108 is executed, patterns the interlayer dielectric layer and using the stop-layer as etching stopping layer, in the grid
Contact hole opening is formed between the lamination of pole.
Specifically, the interlayer dielectric layer 110 is patterned, to form contact hole opening, dew between the gate structure
The semiconductor substrate out, and conductive material is filled in contact hole opening, to form the contact hole.
Specifically, the mask layer with contact hole pattern is formed on the interlayer dielectric layer 110, is with the mask layer
Interlayer dielectric layer 110 described in mask etch, to form contact hole between the gate structure in the interlayer dielectric layer 110
Opening.
Then conductive material is deposited, is open to fill the contact hole and executes planarization, to form contact hole and described
Semiconductor substrate forms connection.
Specifically, the conductive material can pass through low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD
Deposit (PECVD), Metallo-Organic Chemical Vapor deposition (MOCVD) and atomic layer deposition (ALD) or other advanced deposition techniques
It is formed.
Preferably, conductive material is tungsten material.In of the invention one specifically embodiment, conductive material can be cobalt
(Co), molybdenum (Mo), titanium nitride (TiN) and conductive material containing tungsten or combinations thereof.
So far, the introduction of the preparation process of the semiconductor devices of the embodiment of the present invention is completed.After the above step, also
It may include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the preparation method of the present embodiment is also
It can include other steps among above-mentioned each step or between different steps, these steps can pass through the prior art
In various techniques realize that details are not described herein again.
In order to solve the problems in the existing technology the present invention, provides a kind of preparation method of semiconductor devices,
Then the material layer for forming oxide (O) and nitride (N) in the method on the gate stack is etched to be formed
The clearance wall of ON clearance wall or ONON, and form stop-layer on the outside of the clearance wall, etching when using as etching contact hole
Stop-layer, is protected to be formed to the clearance wall, its cycle performance of the semiconductor devices being prepared by the method obtains
To being greatly improved, the threshold voltage stability of the device is higher, further improves the yield and performance of NOR flash memory.
Wherein, Fig. 2 is the process flow chart of semiconductor devices in the embodiment of the invention, specifically includes following
Step:
Step S1: providing semiconductor substrate, is formed with several gate stacks on the semiconductor substrate, and the grid is folded
Layer includes floating gate, separation layer, control gate and the mask layer stacked gradually；
Step S2: the first spacer material layer and second are sequentially formed in the semiconductor substrate and the gate stack
Spacer material layer, to cover the gate stack, wherein the first spacer material layer choosing oxide；
Step S3: etching the second spacer material layer, to expose in the semiconductor substrate the and described exposure mask
The first spacer material layer in layer upper portion side wall；
Step S4: the first spacer material layer that etching removal is exposed, with the shape on the side wall of the gate stack
At clearance wall；
Step S5: deposition stop-layer, to cover the clearance wall and the mask layer.
Embodiment two
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes semiconductor substrate, the semiconductor
Substrate 101 can be following at least one of the material being previously mentioned: silicon is laminated on insulator in silicon, silicon-on-insulator (SOI)
(SSOI), SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator are laminated on insulator
(GeOI) etc..
In addition, active area can be defined in semiconductor substrate 101.It on the active region can also include that others have
Source device, for convenience, there is no indicate in shown figure.
Gate dielectric 102 is formed in the semiconductor substrate 101, wherein the gate dielectric 102 can select
With dielectric material commonly used in the art, such as oxide can be selected.
When selecting oxide as the gate dielectric 102, the forming method of the gate dielectric 102 can be
High-temperature oxydation or deposition method, it is not limited to which a certain method can according to need and be selected.
SiO is selected in the present invention2Layer is used as gate dielectric 102, and the thickness of the gate dielectric 102 can be 1-
20nm, but it is not limited solely to the thickness, those skilled in the art, which can according to need, to be adjusted, to obtain more preferable effect.
Floating gate 103, separation layer 104, control gate 105 and mask layer 106 are sequentially formed on the gate dielectric 102,
To form the gate stack.
Wherein the floating gate layer selects semiconductor material, such as silicon, polysilicon or Ge etc., it is not limited to a certain material
Material, the deposition method of the floating gate layer can choose molecular beam epitaxy (MBE), Metallo-Organic Chemical Vapor deposition (MOCVD), low
One of pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG).
The control gate can select identical material with the floating gate, can also select different materials, such as can be with
Metal gates are being formed as control gate.
Wherein, the mask layer can select hard mask layer, such as SiN or metal hard mask layer can be selected etc., and
It is not limited to a certain kind.
Clearance wall is formed on the side wall of the gate stack, the clearance wall includes the first spacer material layer 107
With the second spacer material layer 108.
Wherein, the first spacer material layer choosing oxide, the second spacer material layer 108 select nitridation
Object, to form the clearance wall of oxide-nitride (ON).
Wherein, the etching selectivity of the first spacer material layer and the second spacer material layer is greater than 3.
It is also formed with stop-layer 109, on the outside of the clearance wall the clearance wall and the exposure mask is completely covered
Layer.
The stop-layer 109, as the stop-layer for etching contact hole opening in subsequent step, while as the clearance wall
Protective layer, with prevent etching formed contact hole opening during the clearance wall is damaged.
In this application since the clearance wall includes the oxide and nitride being sequentially depositing, while in the clearance wall
Outside be also formed with stop-layer as protective layer, avoid etching formed contact hole opening during to the clearance wall
It damages, its cycle performance of the semiconductor devices being prepared by the method is greatly improved, threshold voltage stabilization
Property is higher, further improves the yield and performance of NOR flash memory.
Embodiment three
The present invention also provides a kind of electronic devices, including semiconductor devices described in embodiment two.Wherein, semiconductor device
Part is semiconductor devices described in embodiment two, or the semiconductor devices that the preparation method according to embodiment one obtains.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.The electronic device of the embodiment of the present invention above-mentioned is partly led due to having used
Body device, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of preparation method of semiconductor devices, comprising:
Step S1: semiconductor substrate is provided, is formed with several gate stacks, the gate stack packet on the semiconductor substrate
Include the floating gate stacked gradually, separation layer, control gate and mask layer；
Step S2: the first spacer material layer and the second gap are sequentially formed in the semiconductor substrate and the gate stack
The wall material bed of material, to cover the gate stack, wherein the first spacer material layer choosing oxide；
Step S3: etching the second spacer material layer, to expose in the semiconductor substrate the and described mask layer
The first spacer material layer on portion's side wall；
Step S4: the first spacer material layer that etching removal is exposed, between being formed on the side wall of the gate stack
Gap wall；
Step S5: deposition stop-layer, to cover the clearance wall and the mask layer.
2. the method according to claim 1, wherein the first spacer material layer and second clearance wall
The etching selectivity of material layer is greater than 3.
3. the method according to claim 1, wherein in the step S3, etching second gap wall material
After the bed of material, the height of the mask layer of the first spacer material layer covering in the mask layer upper portion side wall of exposing
Degree is 800~1500 angstroms.
4. the method according to claim 1, wherein the method may further comprise:
Step S6: interlevel dielectric deposition, to cover the gate stack；
Step S7: patterning the interlayer dielectric layer and using the stop-layer as etching stopping layer, with the gate stack it
Between formed contact hole opening.
5. the method according to claim 1, wherein in the step S1, going back on the semiconductor substrate
It is formed with gate dielectric, the gate stack is located at the top of the gate dielectric.
6. according to the method described in claim 5, it is characterized in that, removing described the of the exposing in the step S4
The gate dielectric that removal is exposed while one spacer material layer.
7. the method according to claim 1, wherein selecting dry etching or wet process in the step S4
The first spacer material layer that etching removal is exposed.
8. the method according to claim 1, wherein the second spacer material layer choosing nitride；
The stop-layer selects nitride.
9. a kind of semiconductor devices being prepared based on method described in one of claim 1 to 8.
10. a kind of electronic device, including semiconductor devices as claimed in claim 9.
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|---|---|---|---|---|
| US6232179B1 (en) * | 1997-06-27 | 2001-05-15 | Matsushita Electronics Corporation | Semiconductor device and method of manufacturing the same |
| KR20030006893A (en) * | 2001-07-10 | 2003-01-23 | 삼성전자 주식회사 | Nonvolatile semiconductor device with improved sidewall spacer structure |
| KR20050095429A (en) * | 2004-03-26 | 2005-09-29 | 매그나칩 반도체 유한회사 | Method for manufacturing eeprom cell |
| CN104425366A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(北京)有限公司 | Forming method of semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6232179B1 (en) * | 1997-06-27 | 2001-05-15 | Matsushita Electronics Corporation | Semiconductor device and method of manufacturing the same |
| KR20030006893A (en) * | 2001-07-10 | 2003-01-23 | 삼성전자 주식회사 | Nonvolatile semiconductor device with improved sidewall spacer structure |
| KR20050095429A (en) * | 2004-03-26 | 2005-09-29 | 매그나칩 반도체 유한회사 | Method for manufacturing eeprom cell |
| CN104425366A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(北京)有限公司 | Forming method of semiconductor structure |
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