KR20050095429A - Method for manufacturing eeprom cell - Google Patents
Method for manufacturing eeprom cell Download PDFInfo
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- KR20050095429A KR20050095429A KR1020040020833A KR20040020833A KR20050095429A KR 20050095429 A KR20050095429 A KR 20050095429A KR 1020040020833 A KR1020040020833 A KR 1020040020833A KR 20040020833 A KR20040020833 A KR 20040020833A KR 20050095429 A KR20050095429 A KR 20050095429A
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- Prior art keywords
- oxide film
- floating gate
- nitride film
- sidewall
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 238000000206 photolithography Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 210000004027 cell Anatomy 0.000 description 17
- 238000001312 dry etching Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 210000004692 intercellular junction Anatomy 0.000 description 3
- 125000006850 spacer group Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
본 발명은 콘트롤 게이트의 프로파일이 수직 프로파일이 되도록 형성하여 LDD 스페이서의 면적을 확보함으로써 접합 영역의 항복 전압 증가를 방지할 수 있도록 하는 EEPROM 셀 제조 방법에 관한 것으로, 상기 EEPROM 셀 제조 방법은 실리콘 기판에 터널 산화막, 플로팅 게이트 폴리실리콘, 상부 산화막을 증착하는 단계와; 상기 하드마스크를 두껍게 형성하는 단계와; 상기 하드마스크, 상부 산화막, 플로팅 게이트 폴리실리콘 및 터널 산화막에 대한 사진 및 식각 공정으로 플로팅 게이트를 형성하는 단계와; 상기 플로팅 게이트를 형성한 결과물 전면에 산화막 및 질화막 증착하는 단계와; 상기 질화막 및 산화막을 식각하여 플로팅 게이트 측벽에 사이드월 산화막 및 사이드월 질화막이 형성되도록 하는 단계와; 상기 사이드월 질화막 및 사이드월 산화막을 형성한 결과물을 세정하는 단계와; 상기 세정 공정을 진행하고 고전압 영역용 게이트 산화막을 증착한 후 콘트롤 게이트 폴리실리콘을 증착하는 단계와; 상기 콘트롤 게이트 폴리실리콘을 식각하여 수직 프로파일을 갖는 콘트롤 게이트가 형성되도록 하는 단계를 포함하여 구성된다. The present invention relates to a method for manufacturing an EEPROM cell in which the profile of the control gate is a vertical profile to secure the area of the LDD spacer to prevent an increase in the breakdown voltage of the junction region. Depositing a tunnel oxide film, a floating gate polysilicon, and an upper oxide film; Forming the hard mask thickly; Forming a floating gate by photolithography and etching processes on the hard mask, the upper oxide layer, the floating gate polysilicon, and the tunnel oxide layer; Depositing an oxide film and a nitride film on the entire surface of the resultant of forming the floating gate; Etching the nitride film and the oxide film to form a sidewall oxide film and a sidewall nitride film on a sidewall of the floating gate; Cleaning the resultant of forming the sidewall nitride film and the sidewall oxide film; Performing the cleaning process and depositing a gate oxide film for a high voltage region and then depositing control gate polysilicon; Etching the control gate polysilicon to form a control gate having a vertical profile.
Description
본 발명은 EEPROM 셀 제조 방법에 관한 것으로, 보다 상세하게는 콘트롤 게이트의 프로파일이 수직 프로파일이 되도록 형성하여 LDD 스페이서의 면적을 확보함으로써 접합 영역의 항복 전압 증가를 방지할 수 있도록 하는 EEPROM 셀 제조 방법에 관한 것이다. The present invention relates to a method for manufacturing an EEPROM cell, and more particularly, to an EEPROM cell manufacturing method for forming a profile of a control gate to be a vertical profile to secure an area of an LDD spacer to prevent an increase in breakdown voltage of a junction region. It is about.
EEPROM은 칩을 구성하는 소자의 전하를 전기적으로 변화시킴으로써 데이터를 기록, 소거할 수 있으며, 전기적인 판독이나 기록을 할 수 있어서 시스템 내에 내장된 상태로 프로그램을 다시 할 수도 있다. EEPROM에 있어 프로그램을 하는 동작은 드레인 측에 채널 열전자(channel hot eletron)를 생성시켜 상기 전자를 플로팅 게이트(floating gate)에 축적하여 셀 트랜지스터의 문턱전압을 증가시킴으로써 가능하며, 소거 동작은 소스/기판과 상기 플로팅 게이트 간에 고전압을 발생시켜 플로팅 게이트에 축적된 전자를 방출하여 셀 트랜지스터의 문턱 전압을 낮춤으로써 가능하다.The EEPROM can write and erase data by electrically changing the charges of the devices constituting the chip. The EEPROM can also read and write data, and can be reprogrammed as embedded in the system. Programming in the EEPROM is possible by generating channel hot eletrons on the drain side and accumulating the electrons in the floating gate to increase the threshold voltage of the cell transistors. It is possible to lower the threshold voltage of the cell transistor by generating a high voltage between the floating gate and the electrons accumulated in the floating gate.
상기 EEPROM 셀은 BYTE(8bit) 단위의 기록/소거(Write/Erase) 동작을 시키기 위하여 선택 트랜지스터(Select Transistor)가 단위 셀에 1개씩 반드시 필요하며, 이때 사용되는 선택 트랜지스터는 제 1 폴리실리콘을 이용하는 EEPROM 셀의 플로팅 게이트와 제 2 폴리실리콘을 이용하는 EEPROM 셀의 콘트롤 게이트로 구성된다. The EEPROM cell requires one select transistor in each unit cell to perform write / erase operation in units of 8 bits, and the selection transistor used here uses a first polysilicon. A floating gate of the EEPROM cell and a control gate of the EEPROM cell using the second polysilicon.
이와 같은 EEPROM 셀의 콘트롤 게이트는 프로파일이 둥근 형태로 형성되어 후속 LDD 스페이서 형성시에 LDD 스페이서가 작게 남아 셀 정션의 항복전압 특성이 저하되는 문제점이 발생한다. Such a control gate of the EEPROM cell has a rounded profile, which causes a problem in that the LDD spacer remains small at the time of subsequent LDD spacer formation, thereby lowering the breakdown voltage characteristic of the cell junction.
이하, 첨부된 도면을 참조하여 상기 종래 기술에 의한 EEPROM 셀 제조 방법의 문제점을 상세히 설명하도록 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the problem of the prior art EEPROM cell manufacturing method.
도1a 내지 도1i는 종래 기술에 의한 EEPROM 셀 제조 방법을 나타낸 공정 단면도이다.1A to 1I are cross-sectional views illustrating a method for manufacturing an EEPROM cell according to the prior art.
우선, 도1a에 도시된 바와 같이 실리콘 기판(100)에 터널 산화막(102), 플로팅 게이트 폴리실리콘(104), 상부 산화막/질화막(106) 및 하드마스크용 산화막(108)을 순차 증착한다. First, as shown in FIG. 1A, a tunnel oxide film 102, a floating gate polysilicon 104, an upper oxide film / nitride film 106, and a hard mask oxide film 108 are sequentially deposited on the silicon substrate 100.
그리고 나서, 사진 및 식각 공정을 진행하여 도1b에 도시된 바와 같이 플로팅 게이트(110)를 형성한 후에 도1c에 도시된 바와 같이 산화막(112) 및 질화막(114)을 전면에 증착한다. Then, after forming a floating gate 110 as shown in FIG. 1B by performing a photo and etching process, an oxide film 112 and a nitride film 114 are deposited on the entire surface as shown in FIG. 1C.
그런 다음, 건식 식각 공정을 진행하여 도1d에 도시된 바와 같이 플로팅 게이트 측벽에만 사이드월 산화막(112') 및 사이드월 질화막(114')이 형성되도록 한 후에 세정 공정을 진행하면 도1e에 도시된 바와 같이 하드마스크 산화막(108)이 일부 손실이 된다. After the dry etching process, the sidewall oxide film 112 'and the sidewall nitride film 114' are formed only on the floating gate sidewalls as shown in FIG. 1D. As shown, the hard mask oxide film 108 is partially lost.
상기 세정 공정을 진행한 후에 도1f에 도시된 바와 같이 고전압 영역용 게이트 산화막(116)을 증착하고 콘트롤 게이트 폴리실리콘(118)을 증착한다.After the cleaning process is performed, as shown in FIG. 1F, the gate oxide layer 116 for the high voltage region is deposited and the control gate polysilicon 118 is deposited.
이어서, 콘트롤 게이트 식각 공정을 진행하여 도1g에 도시된 바와 같이 콘트로 게이트가 플로팅 게이트 측면에 스페이서 형태로 형성한 후에 저농도 n형 불순물 주입을 실시한다. Subsequently, a control gate etching process is performed to form a low-concentration n-type impurity after forming a gate in the form of a spacer on the side of the floating gate as shown in FIG. 1G.
그 후, LDD 스페이서용 질화막을 증착한 후 건식 식각 공정을 진행하여 LDD 스페이서(120)를 형성하는데, 이때 도1h에 도시된 바와 같이 콘트롤 게이트의 프로파일이 둥글기 때문에 LDD 스페이서가 너무 작게 남는 현상이 발생한다. LDD 스페이서 형성 후 고농도 n형 불순물을 주입하는데, 상기 LDD 스페이서가 너무 작게 형성되어 셀 정션의 항복 전압이 저하되고, 누설 전류도 증가하는 문제점이 발생하게 된다. Thereafter, a LDD spacer 120 is formed by performing a dry etching process after depositing a nitride film for the LDD spacer. At this time, as shown in FIG. 1H, since the profile of the control gate is rounded, the LDD spacer remains too small. do. After the LDD spacer is formed, a high concentration of n-type impurity is implanted. However, the LDD spacer is formed so small that the breakdown voltage of the cell junction is lowered and the leakage current also increases.
상기와 같은 문제점을 해결하기 위한 본 발명은 하드마스크를 질화막으로 형성하되 높이를 증가시켜 콘트롤 게이트의 프로파일이 수직 프로파일이 되도록 형성하여 LDD 스페이서의 면적을 확보함으로써 접합 영역의 항복 전압 증가를 방지할 수 있도록 하는 EEPROM 셀 제조 방법을 제공하기 위한 것이다. The present invention for solving the above problems is to form a hard mask as a nitride film to increase the height of the control gate profile to form a vertical profile to secure the area of the LDD spacer to prevent the breakdown voltage increase in the junction region The present invention provides a method for manufacturing an EEPROM cell.
상기와 같은 목적을 실현하기 위한 본 발명은 실리콘 기판에 터널 산화막, 플로팅 게이트 폴리실리콘, 상부 산화막을 증착하는 단계와; 상기 하드마스크를 두껍게 형성하는 단계와; 상기 하드마스크, 상부 산화막, 플로팅 게이트 폴리실리콘 및 터널 산화막에 대한 사진 및 식각 공정으로 플로팅 게이트를 형성하는 단계와; 상기 플로팅 게이트를 형성한 결과물 전면에 산화막 및 질화막 증착하는 단계와; 상기 질화막 및 산화막을 식각하여 플로팅 게이트 측벽에 사이드월 산화막 및 사이드월 질화막이 형성되도록 하는 단계와; 상기 사이드월 질화막 및 사이드월 산화막을 형성한 결과물을 세정하는 단계와; 상기 세정 공정을 진행하고 고전압 영역용 게이트 산화막을 증착한 후 콘트롤 게이트 폴리실리콘을 증착하는 단계와; 상기 콘트롤 게이트 폴리실리콘을 식각하여 수직 프로파일을 갖는 콘트롤 게이트가 형성되도록 하는 단계를 포함하는 것을 특징으로 하는 EEPROM 셀 제조 방법The present invention for realizing the above object comprises the steps of depositing a tunnel oxide film, a floating gate polysilicon, an upper oxide film on a silicon substrate; Forming the hard mask thickly; Forming a floating gate by photolithography and etching processes on the hard mask, the upper oxide layer, the floating gate polysilicon, and the tunnel oxide layer; Depositing an oxide film and a nitride film on the entire surface of the resultant of forming the floating gate; Etching the nitride film and the oxide film to form a sidewall oxide film and a sidewall nitride film on a sidewall of the floating gate; Cleaning the resultant of forming the sidewall nitride film and the sidewall oxide film; Performing the cleaning process and depositing a gate oxide film for a high voltage region and then depositing control gate polysilicon; Etching the control gate polysilicon to form a control gate having a vertical profile.
상기 본 발명에 의한 EEPROM 셀 제조 방법에서는, 하드 마스크를 질화막, 또는 산화막과 질화막의 이중 구조로 형성함으로써, 상기 질화막이 캐핑 역할을 하여 세정 공정시 산화막이 손실되는 것을 방지할 뿐만 아니라, 하드마스크 높이를 증가시킴으로써 콘트롤 게이트를 수직 프로파일이 되도록 형성하여 LDD 스페이서의 적정 면적을 확보할 수 있다. In the method for manufacturing an EEPROM cell according to the present invention, the hard mask is formed of a nitride film, or a double structure of an oxide film and a nitride film, thereby preventing the oxide film from being lost during the cleaning process as well as preventing the nitride film from capping and hard mask height. By increasing the control gate to form a vertical profile it is possible to secure the proper area of the LDD spacer.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도2a 내지 도2h는 본 발명에 의한 EEPROM 셀 제조 방법을 나타낸 공정 단면도이다.2A to 2H are cross-sectional views illustrating a method of manufacturing an EEPROM cell according to the present invention.
우선, 도2a에 도시된 바와 같이 실리콘 기판(200)에 터널 산화막(202), 플로팅 게이트 폴리실리콘(204), 상부 산화막(206) 및 하드마스크(208) 질화막을 순차로 증착하되, 상기 질화막(208)은 후속 콘트롤 게이트의 프로파일을 고려하여 높두께를 조절한다. 이때, 상기 하드마스크는 질화막 대신 산화막과 질화막의 이중구조로 형성할 수 있다.First, as shown in FIG. 2A, a tunnel oxide film 202, a floating gate polysilicon 204, an upper oxide film 206, and a hard mask 208 nitride film are sequentially deposited on the silicon substrate 200, and the nitride film ( 208 adjusts the height in consideration of the profile of subsequent control gates. In this case, the hard mask may be formed in a double structure of an oxide film and a nitride film instead of the nitride film.
그리고 나서, 사진 및 식각 공정을 진행하여 도2b에 도시된 바와 같이 플로팅 게이트(210)를 형성한 후에 도2c에 도시된 바와 같이 산화막(212) 및 질화막(214)을 전면에 증착한다. Then, after forming a floating gate 210 as shown in FIG. 2B by performing a photo and etching process, an oxide film 212 and a nitride film 214 are deposited on the entire surface as shown in FIG. 2C.
그런 다음, 건식 식각 공정을 진행하여 도2d에 도시된 바와 같이 플로팅 게이트 측벽에만 사이드월 산화막(212') 및 사이드월 질화막(214')이 형성되도록 한 후에 세정 공정을 진행하게 되는데, 종래와는 달리 하드마스크로 질화막을 이용하기 때문에 하드 마스크가 손실되지 않는다. Then, the dry etching process is performed to form the sidewall oxide film 212 'and the sidewall nitride film 214' only on the floating gate sidewalls as shown in FIG. 2D, and then the cleaning process is performed. Otherwise, since the nitride film is used as the hard mask, the hard mask is not lost.
상기 세정 공정을 진행한 후에 도2e에 도시된 바와 같이 고전압 영역용 게이트 산화막(216)을 증착하고 콘트롤 게이트 폴리실리콘(218)을 증착한다.After the cleaning process is performed, as shown in FIG. 2E, the gate oxide layer 216 for the high voltage region is deposited and the control gate polysilicon 218 is deposited.
이어서, 콘트롤 게이트 식각 공정을 진행하여 도2f에 도시된 바와 같이 콘트로 게이트가 플로팅 게이트 측면에 스페이서 형태로 형성한 후에 저농도 n형 불순물 주입을 실시한다. 이때, 상기 하드마스크로 질화막을 이용하여 높이를 증가시켜 콘트롤 게이트가 종래와는 달리 수직 구간(A)이 형성된다.Subsequently, a control gate etching process is performed to form a low-concentration n-type impurity after the gate is formed in the form of a spacer on the side of the floating gate as shown in FIG. 2F. At this time, the height is increased by using a nitride film as the hard mask, so that the vertical control section A is formed unlike the conventional control gate.
그 후, LDD 스페이서용 질화막을 증착한 후 건식 식각 공정을 진행하여 LDD 스페이서(220)를 형성하는데, 이때 도2g에 도시된 바와 같이 콘트롤 게이트의 프로파일에 수직 구간이 발생하여 LDD 스페이서가 적정 면적이 확보가 된다. After that, a LDD spacer 220 is formed by performing a dry etching process after depositing a nitride film for the LDD spacer. In this case, as shown in FIG. 2G, a vertical section occurs in the profile of the control gate so that the LDD spacer has an appropriate area. It is secured.
상기 LDD 스페이서 형성 후 도2h에 도시된 바와 같이 고농도 n형 불순물을 주입하는데, 상기 LDD 스페이서가 적정 면적 확보됨으로써 셀 정션의 항복전압 저하를 방지하고, 소거시 오프 누설 전류도 감소시킬 수 있다.After forming the LDD spacer, as shown in FIG. 2H, a high concentration n-type impurity is implanted, and the LDD spacer is secured in an appropriate area to prevent the breakdown voltage of the cell junction from decreasing, and also to reduce the off leakage current during erasing.
상기한 바와 같이 본 발명은 EEPROM 셀의 LDD 스페이서를 크게 형성함으로써 접합 영역의 항복 전압 저하를 방지할 수 있으며, 고농도 접합 영역의 채널 영역으로 수직적인 확산에 의한 거리를 상대적으로 멀게함으로써 소거시의 오프 누설 전류를 감소시킬 수 있는 이점이 있다.As described above, the present invention can prevent the breakdown voltage of the junction region from being lowered by forming the LDD spacer of the EEPROM cell large, and can be turned off by erasing the distance due to vertical diffusion relatively to the channel region of the high concentration junction region. There is an advantage that can reduce the leakage current.
도1a 내지 도1i는 종래 기술에 의한 EEPROM 셀 제조 방법을 나타낸 공정 단면도이다.1A to 1I are cross-sectional views illustrating a method for manufacturing an EEPROM cell according to the prior art.
도2a 내지 도2h는 본 발명에 의한 EEPROM 셀 제조 방법을 나타낸 공정 단면도이다. 2A to 2H are cross-sectional views illustrating a method of manufacturing an EEPROM cell according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 - -Explanation of symbols for the main parts of the drawings-
200 : 실리콘 기판 202 : 터널 산화막200 silicon substrate 202 tunnel oxide film
204 : 플로팅 게이트 폴리실리콘 206 : 상부 산화막204: floating gate polysilicon 206: upper oxide film
208 : 하드마스크 210 : 플로팅 게이트208: hard mask 210: floating gate
212 : 산화막 214 : 질화막212: oxide film 214: nitride film
216 : 콘트롤 게이트 폴리실리콘 218 :게이트 산화막 216 control gate polysilicon 218 gate oxide film
220 : 콘트롤 게이트 폴리실리콘 220: control gate polysilicon
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103065952A (en) * | 2011-10-19 | 2013-04-24 | 美格纳半导体有限公司 | Nonvolatile memory device and method of manufacturing thereof |
| CN106611708A (en) * | 2015-10-15 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device |
| CN106611709A (en) * | 2015-10-15 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic apparatus |
| CN108389897A (en) * | 2018-02-02 | 2018-08-10 | 上海华虹宏力半导体制造有限公司 | Grid curb wall and forming method thereof |
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| KR100431300B1 (en) * | 2001-12-22 | 2004-05-12 | 주식회사 하이닉스반도체 | method for fabricating flash memory cell |
| KR100840791B1 (en) * | 2002-07-31 | 2008-06-23 | 삼성전자주식회사 | Method of Forming Gate electrode in non-volatile memory device |
| KR100480619B1 (en) * | 2002-09-17 | 2005-03-31 | 삼성전자주식회사 | SONOS EEPROM having improved programming and erasing performance characteristics and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103065952A (en) * | 2011-10-19 | 2013-04-24 | 美格纳半导体有限公司 | Nonvolatile memory device and method of manufacturing thereof |
| CN106611708A (en) * | 2015-10-15 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device |
| CN106611709A (en) * | 2015-10-15 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic apparatus |
| CN106611708B (en) * | 2015-10-15 | 2019-09-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN106611709B (en) * | 2015-10-15 | 2019-09-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN108389897A (en) * | 2018-02-02 | 2018-08-10 | 上海华虹宏力半导体制造有限公司 | Grid curb wall and forming method thereof |
| CN108389897B (en) * | 2018-02-02 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | Grid side wall and forming method thereof |
| KR20230017029A (en) * | 2021-07-27 | 2023-02-03 | 주식회사 키파운드리 | Manufacturing Method of Non-Volatile Memory Device having Uniform Dielectric Film Profile |
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