CN106611708A - Semiconductor device, preparation method thereof and electronic device - Google Patents
Semiconductor device, preparation method thereof and electronic device Download PDFInfo
- Publication number
- CN106611708A CN106611708A CN201510665802.9A CN201510665802A CN106611708A CN 106611708 A CN106611708 A CN 106611708A CN 201510665802 A CN201510665802 A CN 201510665802A CN 106611708 A CN106611708 A CN 106611708A
- Authority
- CN
- China
- Prior art keywords
- material layer
- layer
- floating gate
- gate material
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 108
- 238000007667 floating Methods 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 13
- -1 LDD ion Chemical class 0.000 claims description 46
- 125000006850 spacer group Chemical group 0.000 claims description 23
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 238000009434 installation Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 238000002513 implantation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 167
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000012212 insulator Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- 239000002184 metal Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000005137 deposition process Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 239000006117 anti-reflective coating Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 229910003822 SiHCl3 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 125000003963 dichloro group Chemical group Cl* 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
The invention relates to a semiconductor device, a preparation method thereof and an electronic device. The method comprises the steps that S1 a semiconductor substrate is provided, and a pad oxide layer and a floating gate material layer are sequentially formed on the semiconductor substrate; S2 LDD ion implantation is carried out, so that an LDD ion implantation area is formed in an expected source drain area in the semiconductor substrate; S3 an isolation material layer, a control gate material layer and a mask layer are formed on the floating gate material layer, and the mask layer, the control gate material layer, the isolation material layer and the floating gate material layer are patterned to form a plurality of spaced-apart gate stacks on both sides of the LDD ion implantation area; and S4 source drain implantation is carried out on both sides of the gate stacks to form a source-drain which surrounds the LDD ion implantation area. According to the method provided by the invention, the performance of the semiconductor device can be improved, and the surface of an active area is clean and rough.
Description
Technical field
The present invention relates to semiconductor device, in particular it relates to a kind of semiconductor device and preparation method thereof, electronic installation.
Background technology
With the high speed development (such as mobile phone, digital camera, MP3 player and PDA etc.) of portable electric appts, for the requirement more and more higher of data storage.Nonvolatile flash memory is due to preservation data are remained under powering-off state the characteristics of, become topmost memory unit in these equipment, wherein, because flash memory (flash memory) can reach very high chip-stored density, and do not introduce new material, manufacturing process is compatible, therefore, it can easily more reliable being integrated into and possesses in digital and analog circuit.
Quasiconductor non-volatile memory (Non-Volatile Semiconductor Memory) becomes the popular domain of memorizer family because of the characteristics of there is power down to remain to holding information for it.Wherein, ETOX (Electron Tunneling Oxide device) structure is mainly made up of insulating barrier between substrate, tunnel oxidation layer, polycrystalline floating boom (FG), grid and polycrystalline control gate (CG).ETOX memorizeies are realized " writing " or " wiping " by the way that electronics is injected or pulled out in floating boom.Due to the change of electronics in floating boom, the threshold voltage of memory cell also can change therewith.When injecting electronics in floating boom, threshold voltage is raised, and is defined as " 1 "；Electronics in floating boom is pulled out and is defined as " 0 ".
With the continuous reduction of dimensions of semiconductor devices, floating gate length and active region width reduce, their size becomes more important for ETOX, wherein active area LDD ion implantings and source and drain injection is more crucial, at present LDD ion implantings are generally formed in after the lamination of floating boom, sealing coat and control gate carries out LDD ion implantings in the both sides of the lamination, but because the depth-width ratio of the lamination is 10:1, in ion implantation process, if ion implanting depth, the effective length of unit component will be affected, Punchthrough is likely to result in, control gate cannot normal work；If ion implanting is shallow, can damage during contact etch and cause device failure.
The ion concentration of source and drain can be caused low if LDD ion implantings are not performed, drain terminal and substrate can produce parasitic capacitance, in order that proper device operation needs to provide bigger voltage to drain terminal, or electric current diminishes, it is impossible to meet the demand of device.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be further described in specific embodiment part.The Summary of the present invention is not meant to attempt the key feature and essential features that limit technical scheme required for protection, does not more mean that the protection domain for attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, there is provided a kind of preparation method of semiconductor device, including：
Step S1：Semiconductor substrate is provided, pad oxide layer and floating gate material layer are sequentially formed with the semiconductor substrate；
Step S2：LDD ion implantings are performed, in the region that source and drain is formed with the expection in the Semiconductor substrate LDD ion implanted regions are formed；
Step S3：Spacer material layer, control gate material layer and mask layer are formed on the floating gate material layer, the mask layer, the control gate material layer, the spacer material layer and the floating gate material layer are patterned, with the both sides in the LDD ion implanted regions some spaced gate stacks are formed；
Step S4：Source and drain injection is performed in the both sides of the gate stack, to form the source and drain for surrounding the LDD ion implanted regions.
Alternatively, step S3 includes：
Step S31：The side perpendicular with the LDD ion implanted regions bearing of trend is upwardly formed fleet plough groove isolation structure in the floating gate material layer and the Semiconductor substrate；
Step S32：Spacer material layer in fleet plough groove isolation structure described in etch-back, with floating gate material layer described in exposed portion；
Step S33：The spacer material layer, the control gate material layer and the mask layer are formed on the floating gate material layer.
Alternatively, step S31 includes：
Step S311：The second mask layer is formed on the floating gate material layer, the floating gate material layer, the Semiconductor substrate and second mask layer is patterned, to be upwardly formed shallow trench in the side perpendicular with the LDD ion implanted regions bearing of trend；
Step S32：Isolated material is filled in the shallow trench, to form the fleet plough groove isolation structure；
Step S33：Remove second mask layer.
Alternatively, in step S4, the depth-width ratio of gate stack is 5 described in source and drain injection:1.
Alternatively, the energy of the LDD ion implantings is 15-30Kev.
Alternatively, the dosage of the LDD ion implantings is 3 × 1014-5×1014。
Alternatively, may further include the step of forming clearance wall on the side wall of the gate stack before the source and drain injection is performed in step S4.
Present invention also offers a kind of semiconductor device prepared based on above-mentioned method.
Present invention also offers a kind of electronic installation, including above-mentioned semiconductor device.
The present invention is in order to solve problems of the prior art, there is provided a kind of preparation method of semiconductor device, forming the followed by execution LDD ion implantings of floating gate layer in the process, simultaneously the thickness of the floating gate layer is less can ensure that the LDD ions are entered in active area, LDD ions enter the determination that source and drain ion concentration can be helped in active area, to improve the performance of semiconductor device, while methods described can also ensure that surfaces of active regions is clean and coarse.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of embodiments of the invention and its description, for explaining the device and principle of the present invention.In the accompanying drawings,
Fig. 1 a-1i are the preparation process schematic diagram of semiconductor device described in an embodiment of the present invention；
Fig. 2 is the preparation technology flow chart of semiconductor device described in an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.It is, however, obvious to a person skilled in the art that the present invention can be carried out without the need for one or more of these details.In other examples, in order to avoid obscuring with the present invention, for some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and should not be construed as being limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings, in order to clear, the size and relative size in Ceng He areas may be exaggerated.From start to finish same reference numerals represent identical element.
It is understood that, be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to " or when " being coupled to " other elements or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or there may be element between two parties or layer.Conversely, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other elements or layer, then there is no element between two parties or layer.It should be understood that although various elements, part, area, floor and/or part can be described using term first, second, third, etc., these elements, part, area, floor and/or part should not be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another element, part, area, floor or part.Therefore, without departing from present invention teach that under, the first element discussed below, part, area, floor or part be represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., can describe for convenience here and by using so as to describe an element or feature shown in figure with other elements or the relation of feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include the different orientation of the device in using and operating.For example, if the device upset in accompanying drawing, then, be described as " below other elements " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term " ... below " and " ... under " may include it is upper and lower two orientation.Device can additionally be orientated (be rotated by 90 ° or other orientations) and spatial description language as used herein is correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the restriction of the present invention.When here is used, " one " of singulative, " one " and " described/should " be also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that term " composition " and/or " including ", when using in this specification, determine the presence of the feature, integer, step, operation, element and/or part, but be not excluded for the presence or addition of one or more other features, integer, step, operation, element, part and/or group.When here is used, term "and/or" includes any and all combination of related Listed Items.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
A kind of specific embodiment of the present invention is illustrated below in conjunction with the accompanying drawings, wherein, Fig. 1 a-1i are the preparation process schematic diagram of semiconductor device described in an embodiment of the present invention；Fig. 2 is the preparation technology flow chart of semiconductor device described in an embodiment of the present invention.
First, execution step 101, there is provided Semiconductor substrate 101, in the Semiconductor substrate 101 pad oxide layer is formed.
First, reference picture 1a, Fig. 1 a are sectional view of the semiconductor device along Y direction.Wherein, Fig. 1 a-1b are sectional view of the semiconductor device along Y direction；Fig. 1 c-1g are sectional view of the semiconductor device along X-direction；Fig. 1 h-1i are sectional view of the semiconductor device along X-direction.Wherein described Semiconductor substrate 101 can be at least one in the following material being previously mentioned：It is laminated on silicon, silicon-on-insulator (SOI), insulator on silicon (SSOI), insulator and is laminated SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Additionally, active area can be defined in Semiconductor substrate 101.Other active devices can also be included on the active region, for convenience, do not indicated in shown figure.
Pad oxide layer 102 is formed in the Semiconductor substrate 101, wherein, the pad oxide layer 102 can select dielectric material commonly used in the art, for example, can select oxide.
The forming method of the pad oxide layer 102 can be high-temperature oxydation or deposition process, it is not limited to a certain method, can be selected as needed.
SiO is selected in the present invention2Used as pad oxide layer 102, the thickness of the pad oxide layer 102 can be 1-20nm to layer, but be not limited solely to the thickness, and those skilled in the art can be adjusted as needed, to obtain more preferable effect.
In this step as a kind of specific embodiment, the SiO2The deposition process of layer can select thermal oxide, ald, chemical vapor deposition, electron beam evaporation or magnetically controlled sputter method.
Execution step 102, forms floating gate material layer 103 and the first mask layer in the pad oxide layer 102, and performs LDD ion implantings, and in the region that source and drain is formed with the expection in the Semiconductor substrate LDD ion implanted regions are formed.
Specifically, as shown in Figure 1a, the floating gate material layer choosing semi-conducting material, such as silicon, polysilicon or Ge etc., a certain material is not limited to, the deposition process of the floating gate material layer can select the one kind in molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG).
In this embodiment, the floating gate material layer of polysilicon is formed, the polysilicon is formed from epitaxy method, specifically, is described further by taking silicon as an example in a particular embodiment, and reacting gas can include hydrogen (H2) carry Silicon chloride. (SiCl4) or trichlorosilane (SiHCl3), silane (SiH4) and dichloro hydrogen silicon (SiH2Cl2) etc. at least one entrance be placed with the reative cell of silicon substrate, carry out high-temperature chemical reaction in reative cell, siliceous reacting gas is reduced or is thermally decomposed, produced silicon atom is in pad oxide layer surface Epitaxial growth.
In this step the first mask layer is formed on the floating gate material layer 103, wherein first mask layer can select conventional mask, for example, can select photoresist layer.
First mask layer is patterned, to form opening, then LDD ion implantings is performed by mask of first mask layer, so that LDD ion implanted regions are formed in X-direction in Semiconductor substrate.
Wherein, in this step the floating gate material layer has less thickness, and to ensure that the LDD ions are entered in active area, LDD ions enter the determination that source and drain ion concentration can be helped in active area.
Wherein, the thickness of the floating gate material layer is not limited to a certain numerical range, is 5 in the depth-width ratio for forming the gate stack that floating boom, sealing coat, control gate and mask layer are formed:1.
Wherein, the energy of the LDD ion implantings is 15-30Kev.The dosage of the LDD ion implantings is 3 × 1014-5×1014。
Deposit the floating gate material layer followed by perform the LDD ion implantings and the pad oxide layer 102 and the floating gate material layer are used as protection, surfaces of active regions can be made to keep coarse, prevent electronics from Punchthrough occurring.
Execution step 103, forms the second mask layer on the floating gate material layer, the floating gate material layer, the Semiconductor substrate and second mask layer is patterned, to be upwardly formed shallow trench in the side perpendicular with the LDD ion implanted regions bearing of trend.
Specifically, as illustrated in figure 1 c, in this step wherein described mask layer can select hard mask layer, such as SiN, to protect the floating gate layer not to be damaged during shallow trench is formed.
Then, dry etch process is performed, successively hard mask layer, floating gate material layer, pad oxide layer and Semiconductor substrate 101 is performed etching to form shallow trench.Specifically, the figuratum photoresist layer of tool can be formed on hard mask layer, dry etching is carried out to hard mask layer by mask of the photoresist layer, to transfer a pattern to hard mask layer, and with photoresist layer and hard mask layer floating gate material layer, pad oxide layer and Semiconductor substrate 101 are performed etching as mask, to form groove.
Execution step 104, fills shallow trench isolated material, to form fleet plough groove isolation structure in groove.
Specifically, as shown in Figure 1 d, shallow trench isolated material can be formed on hard mask layer and in groove, the shallow trench isolated material can be silicon oxide, silicon oxynitride and/or other existing advanced low-k materials；Perform chemical mechanical milling tech and stop on hard mask layer layer, to form fleet plough groove isolation structure.
Finally, hard mask layer is removed.The method for removing remaining hard mask layer can be wet etching process, because the etching agent for removing hard mask layer is thought it is known in the art, therefore no longer describing in detail.
Execution step 105, the spacer material layer in isolation structure described in etch-back, with floating gate material layer described in exposed portion.
Specifically, as shown in fig. le, remove the partial oxide in the fleet plough groove isolation structure by blanket type dry etching (Blank etch) in this step, form groove, to expose the partial sidewall of the floating gate material layer, the step is referred to as (cell open the step of memory element is opened, COPEN) the step of, i.e. by removing the shallow trench isolation oxide between the floating boom of part, with floating gate material Rotating fields described in exposed portion, so that after deposit polycrystalline silicon layer stable contact can be formed with the FGS floating gate structure, avoid because device size reduces the problem for causing contact unstable.
Execution step 106, spacer material layer, control gate material layer and mask layer are formed on the floating gate material layer, the floating gate material layer, the spacer material layer, the control gate material layer and the mask layer are patterned, with the both sides in the LDD ion implanted regions some spaced gate stacks are formed.
Specifically, as shown in Fig. 1 f-1g, form spacer material layer, control gate material layer and mask layer on the floating gate material layer in this step, and pattern the floating gate material layer, the spacer material layer, the control gate material layer and mask layer, to form gate stack.
Wherein, spacer material layer is formed on the floating gate material layer, the spacer material layer can select insulant commonly used in the art, such as ONO (the structural insulation sealing coat of oxidenitride oxide), but be not limited to that the material.
Then control gate material layer is formed in the top of the spacer material layer, wherein the control gate material layer can be selected and the floating gate material layer identical material, it is also possible to from different materials, for example, can form metal gates as control gate.
Wherein, the mask layer can select hard mask layer, for example, can select SiN or metal hard mask layer etc., it is not limited to a certain.
The patterning patterning floating gate material layer, the spacer material layer, the control gate material layer and the mask layer, to form floating boom 102, sealing coat 106, control gate 107 and mask layer 108, to form the gate stack.
Specifically patterning method includes but is not limited to following methods：Organic distribution layer (Organic distribution layer are formed on the mask layer 108, ODL), siliceous bottom antireflective coating (Si-BARC), the photoresist layer of deposit patterned on the siliceous bottom antireflective coating (Si-BARC), or only form the photoresist layer that patterned in the control gate material layer, pattern definition on the photoresist to be formed the figure of grid structure, then with the photoresist layer as mask layer or with the etching organic distribution layer, bottom antireflective coating, the lamination that photoresist layer is formed is floating gate material layer described in mask etch, the spacer material layer, the control gate material layer and mask layer 108.
Then organic distribution layer (Organic distribution layer, ODL), siliceous bottom antireflective coating (Si-BARC), photoresist layer are removed.
In this step, from dry etching, reactive ion etching (RIE), ion beam milling, plasma etching.
Execution step 107, in the Semiconductor substrate and the gate stack gap wall layer 109 is sequentially formed.
Specifically, as shown in figure 1h, in this step, deposit spacer material layer, the spacer material layer choosing oxide or nitride, or both combination.
The spacer material layer 108 is etched, to form the clearance wall 109 on the side wall of the gate stack.
Wherein, in this step from dry etching or wet etching, in the present invention etching, the C-F etchants are CF to preferred C-F etchants4、CHF3、C4F8And C5F8In one or more.In this embodiment, the dry etching can select CF4、CHF3, in addition plus N2、CO2In one kind as etching atmosphere, wherein gas flow be CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure is 30-150mTorr, and etching period is 5-120s.
Source and drain injection is performed in the both sides of the gate stack after the clearance wall is formed, to form the source and drain for surrounding the LDD ion implanted regions, as shown in figure 1i.
So far, the introduction of the preparation process of the semiconductor device of the embodiment of the present invention is completed.After the above step, other correlation steps can also be included, here is omitted.Also, in addition to the foregoing steps, the preparation method of the present embodiment can be to include other steps among above-mentioned each step or between different step, and these steps can realize that here is omitted by various techniques of the prior art.
The present invention is in order to solve problems of the prior art, there is provided a kind of preparation method of semiconductor device, forming the followed by execution LDD ion implantings of floating gate layer in the process, simultaneously the thickness of the floating gate layer is less can ensure that the LDD ions are entered in active area, LDD ions enter the determination that source and drain ion concentration can be helped in active area, to improve the performance of semiconductor device, while methods described can also ensure that surfaces of active regions is clean and coarse.
Wherein, Fig. 2 is the process chart of semiconductor device in the embodiment of the invention, is specifically comprised the following steps：
Step S1：Semiconductor substrate is provided, pad oxide layer and floating gate material layer are sequentially formed with the semiconductor substrate；
Step S2：LDD ion implantings are performed, in the region that source and drain is formed with the expection in the Semiconductor substrate LDD ion implanted regions are formed；
Step S3：Spacer material layer, control gate material layer and mask layer are formed on the floating gate material layer, the mask layer, the control gate material layer, the spacer material layer and the floating gate material layer are patterned, with the both sides in the LDD ion implanted regions some spaced gate stacks are formed；
Step S4：Source and drain injection is performed in the both sides of the gate stack, to form the source and drain for surrounding the LDD ion implanted regions.
Embodiment two
Present invention also offers a kind of semiconductor device, the semiconductor device includes Semiconductor substrate, and the Semiconductor substrate 101 can be at least one in the following material being previously mentioned：It is laminated on silicon, silicon-on-insulator (SOI), insulator on silicon (SSOI), insulator and is laminated SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Additionally, active area can be defined in Semiconductor substrate 101.Other active devices can also be included on the active region, for convenience, do not indicated in shown figure.
Pad oxide layer 102 is formed with the Semiconductor substrate 101, wherein, the pad oxide layer 102 can select dielectric material commonly used in the art, for example, can select oxide.
When from oxide as the pad oxide layer 102, the forming method of the pad oxide layer 102 can be high-temperature oxydation or deposition process, it is not limited to a certain method, can be selected as needed.
SiO is selected in the present invention2Used as pad oxide layer 102, the thickness of the pad oxide layer 102 can be 1-20nm to layer, but be not limited solely to the thickness, and those skilled in the art can be adjusted as needed, to obtain more preferable effect.
Floating boom 103, sealing coat 106, control gate 107 and mask layer 108 are sequentially formed in the pad oxide layer 102, to form the gate stack.
Wherein described floating gate layer selects semi-conducting material, such as silicon, polysilicon or Ge etc., a certain material is not limited to, the deposition process of the floating gate layer can select the one kind in molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG).
The control gate can select identical material with the floating boom, it is also possible to from different materials, for example, can form metal gates as control gate.
Wherein, the mask layer can select hard mask layer, for example, can select SiN or metal hard mask layer etc., it is not limited to a certain.
Clearance wall 109 is formed with the side wall of the gate stack
LDD ion implanted regions are formed with the both sides of the gate stack, and are also formed with surrounding the source and drain of the LDD ion implanted regions in the both sides of the gate stack.
Wherein, the energy of LDD ion implantings is 15-30Kev in the LDD ion implanted regions, and the dosage of the LDD ion implantings is 3 × 1014-5×1014。
In this application because the clearance wall is including the oxide and nitride being sequentially depositing; simultaneously stop-layer is also formed with the outside of the clearance wall as protective layer; avoid the clearance wall is caused damage during etching forms contact hole opening; semiconductor device its cycle performance prepared by methods described is greatly improved; threshold voltage stability is higher, further increases the yield and performance of NOR flash memory.
Embodiment three
Present invention also offers a kind of electronic installation, including the semiconductor device described in embodiment two.Wherein, semiconductor device is the semiconductor device described in embodiment two, or the semiconductor device that the preparation method according to embodiment one is obtained.
The electronic installation of the present embodiment, can be any electronic product such as mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen, MP3, MP4, PSP or equipment, alternatively any intermediate products including the semiconductor device.The electronic installation of the embodiment of the present invention, due to having used above-mentioned semiconductor device, thus with better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the invention is not limited in above-described embodiment, teaching of the invention can also make more kinds of variants and modifications, and these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention is defined by the appended claims and its equivalent scope.
Claims (9)
1. a kind of preparation method of semiconductor device, including：
Step S1：Semiconductor substrate is provided, liner oxidation is sequentially formed with the semiconductor substrate
Nitride layer and floating gate material layer；
Step S2：LDD ion implantings are performed, source and drain is formed with the expection in the Semiconductor substrate
Region in formed LDD ion implanted regions；
Step S3：Spacer material layer, control gate material layer and mask are formed on the floating gate material layer
Layer, patterns the mask layer, the control gate material layer, the spacer material layer and the floating boom material
The bed of material, with the both sides in the LDD ion implanted regions some spaced gate stacks are formed；
Step S4：Source and drain injection is performed in the both sides of the gate stack, to be formed the LDD is surrounded
The source and drain of ion implanted regions.
2. method according to claim 1, it is characterised in that step S3 includes：
Step S31：Note with the LDD ions in the floating gate material layer and the Semiconductor substrate
Enter the perpendicular side of region bearing of trend and be upwardly formed fleet plough groove isolation structure；
Step S32：Spacer material layer in fleet plough groove isolation structure described in etch-back, with exposed portion
The floating gate material layer；
Step S33：The spacer material layer, the control grid material are formed on the floating gate material layer
Layer and the mask layer.
3. method according to claim 2, it is characterised in that step S31 includes：
Step S311：The second mask layer is formed on the floating gate material layer, the floating boom material is patterned
The bed of material, the Semiconductor substrate and second mask layer, with the LDD ion implanted regions
The perpendicular side of bearing of trend is upwardly formed shallow trench；
Step S32：Isolated material is filled in the shallow trench, to form the shallow trench isolation junction
Structure；
Step S33：Remove second mask layer.
4. method according to claim 1, it is characterised in that in step S4,
The depth-width ratio of gate stack is 5 described in the source and drain injection:1.
5. method according to claim 1, it is characterised in that the LDD ion implantings
Energy is 15-30Kev.
6. method according to claim 1, it is characterised in that the LDD ion implantings
Dosage is 3 × 1014-5×1014。
7. method according to claim 1, it is characterised in that holding in step S4
Before the row source and drain injection, to may further include and form clearance wall on the side wall of the gate stack
The step of.
8. the semiconductor device that a kind of method based on described in one of claim 1 to 7 is prepared.
9. a kind of electronic installation, including the semiconductor device described in claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510665802.9A CN106611708B (en) | 2015-10-15 | 2015-10-15 | A kind of semiconductor devices and preparation method thereof, electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510665802.9A CN106611708B (en) | 2015-10-15 | 2015-10-15 | A kind of semiconductor devices and preparation method thereof, electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106611708A true CN106611708A (en) | 2017-05-03 |
| CN106611708B CN106611708B (en) | 2019-09-03 |
Family
ID=58610243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510665802.9A Active CN106611708B (en) | 2015-10-15 | 2015-10-15 | A kind of semiconductor devices and preparation method thereof, electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106611708B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109427584A (en) * | 2017-08-29 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method and semiconductor devices of semiconductor devices |
| CN113130308A (en) * | 2021-03-01 | 2021-07-16 | 上海华力集成电路制造有限公司 | Method for forming ion implantation region |
| CN114678370A (en) * | 2022-05-30 | 2022-06-28 | 广州粤芯半导体技术有限公司 | Flash structure and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789297A (en) * | 1996-09-23 | 1998-08-04 | Mosel Vitelic Inc. | Method of making EEPROM cell device with polyspacer floating gate |
| CN1420543A (en) * | 2001-11-21 | 2003-05-28 | 哈娄利公司 | Double MONOS unit mfg. method and module structure |
| KR20040060583A (en) * | 2002-12-30 | 2004-07-06 | 주식회사 하이닉스반도체 | Method for manufacturing of flash memory device |
| CN1536650A (en) * | 2003-02-06 | 2004-10-13 | ���ǵ�����ʽ���� | Method for making semiconductor integrated circuit and semiconductor integrated circuit madefrom |
| KR20050095429A (en) * | 2004-03-26 | 2005-09-29 | 매그나칩 반도체 유한회사 | Method for manufacturing eeprom cell |
-
2015
- 2015-10-15 CN CN201510665802.9A patent/CN106611708B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789297A (en) * | 1996-09-23 | 1998-08-04 | Mosel Vitelic Inc. | Method of making EEPROM cell device with polyspacer floating gate |
| CN1420543A (en) * | 2001-11-21 | 2003-05-28 | 哈娄利公司 | Double MONOS unit mfg. method and module structure |
| KR20040060583A (en) * | 2002-12-30 | 2004-07-06 | 주식회사 하이닉스반도체 | Method for manufacturing of flash memory device |
| CN1536650A (en) * | 2003-02-06 | 2004-10-13 | ���ǵ�����ʽ���� | Method for making semiconductor integrated circuit and semiconductor integrated circuit madefrom |
| KR20050095429A (en) * | 2004-03-26 | 2005-09-29 | 매그나칩 반도체 유한회사 | Method for manufacturing eeprom cell |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109427584A (en) * | 2017-08-29 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method and semiconductor devices of semiconductor devices |
| CN109427584B (en) * | 2017-08-29 | 2022-05-27 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN113130308A (en) * | 2021-03-01 | 2021-07-16 | 上海华力集成电路制造有限公司 | Method for forming ion implantation region |
| CN114678370A (en) * | 2022-05-30 | 2022-06-28 | 广州粤芯半导体技术有限公司 | Flash structure and preparation method thereof |
| CN114678370B (en) * | 2022-05-30 | 2022-08-02 | 广州粤芯半导体技术有限公司 | Flash structure and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106611708B (en) | 2019-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100517732C (en) | Semiconductor structure and manufacturing method thereof | |
| EP1986240B1 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| US9029256B2 (en) | Charge-trap based memory | |
| CN103050407A (en) | Embedded transistor | |
| US6902978B2 (en) | Method of making the selection gate in a split-gate flash EEPROM cell and its structure | |
| CN1323439C (en) | Nonvolatile memory cell employing a plurality of dielectric nanoclusters and method of fabricating the same | |
| CN106601744A (en) | Embedded flash memory, manufacturing method thereof and electronic device | |
| CN106611708B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN108447866A (en) | Floating-gate device and preparation method thereof | |
| CN105990146A (en) | Semiconductor device, fabrication method thereof and electronic apparatus | |
| CN105355599B (en) | A kind of semiconductor storage unit and preparation method thereof, electronic device | |
| CN105990428A (en) | Semiconductor device, fabrication method thereof and electronic apparatus | |
| US6969881B2 (en) | Partial vertical memory cell and method of fabricating the same | |
| CN107785372A (en) | Semiconductor devices and preparation method thereof, electronic installation | |
| CN108010835A (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN1988179B (en) | Non-volatile floating gate memory cells with polysilicon storage unit and fabrication methods thereof | |
| US6255167B1 (en) | Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate | |
| CN102610508A (en) | Preparation method of floating gate | |
| CN106611709B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN107845637A (en) | A kind of semiconductor devices and preparation method thereof, electronic installation | |
| CN107895723A (en) | Semiconductor devices and preparation method thereof, electronic installation | |
| CN106601686A (en) | Semiconductor device and preparation method thereof, and electronic device | |
| CN100517657C (en) | SONOS Flash memory manufacture method | |
| CN106298676A (en) | Method for manufacturing semiconductor element | |
| CN105789134B (en) | A kind of semiconductor storage unit and preparation method thereof, electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |