CN108735711A - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN108735711A CN108735711A CN201710240157.5A CN201710240157A CN108735711A CN 108735711 A CN108735711 A CN 108735711A CN 201710240157 A CN201710240157 A CN 201710240157A CN 108735711 A CN108735711 A CN 108735711A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, electronic devices.The semiconductor devices includes：Along the bit line of first direction setting, the bit line is electrically connected with device below；Wherein, the bit line includes the first bit line and the second bit line being staggered up and down, and first bit line and second bit line are arranged alternately in the second direction perpendicular with the first direction.Dielectric spacing between bit line can be caused to reduce the breakdown problem brought to avoid since size reduces by the setting, by be staggered up and down can make same layer between adjacent bit line spacing become larger, due to being located at different layers between adjacent bit line, the problem that spacing will not be brought too small, therefore the performance and yield of device can be further increased.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
Increasingly increase for the semiconductor storage demand of high power capacity, the integration density of these semiconductor storages
It is concerned by people, in order to increase the integration density of semiconductor storage, uses many different sides in the prior art
Method, such as multiple storage units are formed on single wafer by reducing wafer size and/or changing interior structural unit, for
By change cellular construction increase integration density method for, carried out attempt by change active area horizontal layout or
Change cell layout and carrys out reduction unit area.
With the continuous diminution of dimensions of semiconductor devices, bit line processing procedure is chosen due to the progress of technology node by huge
War.Since technology node is constantly progressive, the characteristic size of device constantly reduces, the critical size of bit line and the sheet resistance of bit line
(Rs) it is restricted, in order to reduce sheet resistance (Rs), usually selects copper as bit line metal, in order to obtain better copper filling
Performance usually selects reverse trapezoid shape, further such that the dielectric spacing between adjacent bit lines reduces, to hitting between bit line
It wears performance to be affected, and then influences the performance and yield of device.
Therefore need to provide a kind of new semiconductor devices and preparation method thereof, it is existing in the prior art above-mentioned to solve
Problem.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are the present invention provides a kind of semiconductor devices, the semiconductor devices includes：
Along the bit line of first direction setting, the bit line is electrically connected with device below；
Wherein, the bit line includes the first bit line and the second bit line being staggered up and down, and first bit line and
Second bit line is arranged alternately in the second direction perpendicular with the first direction.
Optionally, the semiconductor devices further includes：
Contact structures, between the bit line and the device, the both ends of the contact structures respectively with the bit line
It is electrically connected with the device.
Optionally, the contact structures include different the first contact structures and the second contact structures of height, and described first
Contact structures are electrically connected with first bit line, and second contact structures are electrically connected with second bit line.
Optionally, the semiconductor devices further includes：
Along the wordline of second direction setting.
Optionally, the device includes transistor, and the bit line is electrically connected with the source electrode of the transistor, the wordline with
The grid of the transistor is electrically connected.
Optionally, the semiconductor devices includes the peripheral region on the outside of memory cell region and the storage unit,
In, it is each formed with the bit line in the memory cell region and the peripheral region.
The present invention also provides a kind of preparation method of semiconductor devices, the method includes：
Bit line is formed in a first direction, and the bit line is electrically connected with device below；
Wherein, the bit line includes the first bit line and the second bit line being staggered up and down, and first bit line and
Second bit line is arranged alternately in the second direction perpendicular with the first direction.
Optionally, it forms first bit line and the method for second bit line includes：
There is provided and include the substrate of the device, be formed on the substrate in the first dielectric layer and with the device
First bit line of part electrical connection；
The second dielectric layer is formed on first dielectric layer；
The second bit line being electrically connected with the device is formed in second dielectric layer.
Optionally, the method for formation first bit line includes：
The substrate comprising the device and the interlayer dielectric layer in the substrate are provided, in the interlayer dielectric layer
It is formed with the first contact structures；
The first dielectric layer is formed above first contact structures；
First dielectric layer is patterned, to form the first opening for exposing first contact structures；
The depositing bitlines material layer in first opening, to form first bit line.
Optionally, the method for formation second bit line includes：
First dielectric layer and the interlayer dielectric layer are patterned, in a second direction between first bit line
Contact openings are formed, the device is exposed；
The second dielectric layer for covering first dielectric layer is formed on first dielectric layer；
Second dielectric layer is patterned, to form the second opening and expose the contact openings；
Depositing bitlines material layer forms the second contact structures and described to fill second opening and the contact openings
Second bit line.
Optionally, first opening, the contact openings and/or described the are formed using the method for self-aligned double patterning case
Two openings.
Optionally, the method for the self-aligned double patterning case includes：
Mask stack and photoresist layer are sequentially formed on first dielectric layer or second dielectric layer, and to the light
Resistance is exposed development, to form cylindricality pattern；
Using the cylindricality pattern as mask stack described in mask etch, and then form the column construction of mask stack；
Conformal deposited spacer material layer, to cover the column construction；
The spacer material layer is etched, to form clearance wall on the side wall of the column construction；
It removes the column construction and retains the clearance wall；
Using the clearance wall as the first dielectric layer described in mask etch, to form first opening；Or between described
Gap wall is the second dielectric layer and first dielectric layer described in mask etch, to form second opening.
Optionally, the method further includes the steps that formation wordline, the word before or after forming the bit line
Line is arranged in a second direction.
Optionally, the device includes transistor, and the bit line is electrically connected with the source electrode of the transistor, the wordline with
The grid of the transistor is electrically connected.
The present invention also provides a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
In order to overcome problems of the prior art, the present invention provides a kind of semiconductor devices and preparation method thereof,
It sets the bit line to two layers interlocked up and down in the semiconductor devices, i.e., the described bit line includes being staggered up and down
First bit line and the second bit line, and first bit line and second bit line are perpendicular with the first direction second
It is arranged alternately on direction.Dielectric spacing between bit line can be caused to reduce bring to avoid since size reduces by the setting
Breakdown problem, by be staggered up and down can make same layer between adjacent bit line spacing become larger, between adjacent bit line due to
Positioned at different layers, the problem that spacing will not be brought too small, therefore the performance and yield of device can be further increased.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is the vertical view of semiconductor devices neutrality line described in the prior art；
Fig. 2A is sectional view of the bit line in semiconductor devices described in the prior art along word-line direction；
Fig. 2 B are sectional view of the peripheral region in semiconductor devices described in the prior art along word-line direction；
Fig. 3 A are the vertical view of heretofore described semiconductor devices neutrality line；
Fig. 3 B are sectional view of the bit line in heretofore described semiconductor devices along word-line direction；
Fig. 3 C are sectional view of the peripheral region in heretofore described semiconductor devices along word-line direction；
Fig. 4 A-4F are sectional view of the heretofore described semiconductor devices neutrality line preparation process along word-line direction；
Fig. 5 is a kind of schematic flow chart of the manufacturing method of semiconductor devices of one embodiment of the present of invention；
Fig. 6 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but include due to for example manufacturing caused shape
Shape deviation.For example, be shown as the injection region of rectangle its edge usually there is circle or bending features and/or implantation concentration ladder
Degree, rather than the binary from injection region to non-injection regions changes.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiment.
The set-up mode of the current bit line is as shown in Figure 1, wherein it is located at same layer between adjacent bit line 205,206,
And the interlaced setting on bit line extending direction, wherein the bit line 205,206 is electrically connected with the device of lower section, example
If the device includes the through-hole 203 being formed in dielectric layer 202, the lower section of through-hole 203 could be formed with metal layer, Jin Erjin
At metal interconnection structure, the metal interconnection structure is electrically connected row with the IC circuits or transistor device formed in substrate 201,
As shown in Figure 2 A.Wherein, the substrate includes center and peripheral region, and the peripheral region is arranged in the center
Around, the set-up mode of the bit line in the peripheral region with the bit line of center set-up mode, as shown in Figure 2 B, in institute
State in peripheral region further includes the gate via 204 being connected with grid and metal layer 207.
With the continuous diminution of dimensions of semiconductor devices, bit line processing procedure is chosen due to the progress of technology node by huge
War.Since technology node is constantly progressive, the characteristic size of device constantly reduces, the critical size of bit line and the sheet resistance of bit line
(Rs) it is restricted, in order to reduce sheet resistance (Rs), usually selects copper as bit line metal, in order to obtain better copper filling
Performance usually selects reverse trapezoid shape, further such that the dielectric spacing between adjacent bit lines reduces, to hitting between bit line
It wears performance to be affected, and then influences the performance and yield of device.
For this purpose, in order to solve the problems, such as presently, there are, the present invention provides a kind of semiconductor devices, as shown in figs. 3 a-3 c,
The semiconductor devices includes：
Along the bit line of first direction setting, the bit line is electrically connected with device below；
Wherein, the bit line includes the first bit line 305 and the second bit line 307 being staggered up and down, and described first
Bit line 305 and second bit line 307 are arranged alternately in the second direction perpendicular with the first direction.
Specifically, wherein it refers to adjacent two to be staggered and be arranged alternately up and down between first bit line and the second bit line
Interval between a first bit line is corresponding up and down with the second bit line, on the interval and the first bit line between two neighboring second bit line
Lower correspondence.
Wherein, as shown in Figure 3A, Fig. 3 A are the vertical view of heretofore described semiconductor devices neutrality line, wherein left hand view
Shape is the vertical view of the layer where the second bit line 307, and right figure is the vertical view of the layer where the first bit line 305, first
Line 305 and second bit line 307 are located in two layers to be staggered up and down, therefore change same layer position in current technique and hand over
The mode of mistake setting, the mode for selecting different layers to be staggered can preferably improve Jie between bit line by the change
Electric spacing improves the process window of bit line.
Wherein, the bit line is metal wire, is used to each device in same direction, such as first direction forming electricity
Connection, such as the bit line are used to the source electrode (not shown) of the transistor in the substrate 301 forming electrical connection, such as scheme
Shown in 3B.
Wherein, the bit line is elongated metal line, and the extending direction of the bit line is defined as first direction, wherein
With first direction wordline is formed in perpendicular second direction, wherein the wordline is electrically connected with the grid of the transistor,
As shown in Figure 3A, wherein the wordline can be the conventional wordline in this field, details are not described herein.
Wherein, first bit line and second bit line are located in two dielectric layers of stacked on top setting.
Such as first bit line is set in the first dielectric layer 309 in the present invention, second bit line is set to
In two dielectric layers 310, wherein second dielectric layer 310 is located on first dielectric layer 309, and then is formed and interlocked up and down
The bit line of setting.
The wherein described upper and lower directions refers to the direction of device stacked on top unless otherwise specified.
The semiconductor devices further includes：
Contact structures, between the bit line and the device, the both ends of the contact structures respectively with the bit line
It is electrically connected with the device.
The contact structures include different the first contact structures 303 and the second contact structures 304 of height, and described first connects
It touches structure 303 to be electrically connected with first bit line 305, second contact structures 304 are electrically connected with second bit line 307.
So-called height is the size on substrate thickness direction, and also the as described contact structures are directed toward the direction of bit line, not special
In the case of explanation, height is with reference to the explanation in this application.
Wherein, since first bit line and second bit line are staggered up and down, first contact structures
303 and second contact structures 304 be highly different in the up-down direction, to meet first bit line and second bit line
The demand being staggered up and down.
The present invention provides a kind of semiconductor devices and preparation method thereof, set the bit line in the semiconductor devices
It is set to two layers up and down staggeredly, i.e., the described bit line includes the first bit line and the second bit line being staggered up and down, and described the
One bit line and second bit line are arranged alternately on the direction perpendicular with the first direction.It can be kept away by the setting
Exempt to cause dielectric spacing between bit line to reduce the breakdown problem brought since size reduces, by be staggered up and down can make it is same
Adjacent bit line spacing becomes larger between layer, due to being located at different layers between adjacent bit line, will not bring spacing is too small to ask
Topic, therefore the performance and yield of device can be further increased.
Embodiment one
The present invention provides a kind of semiconductor devices, and as shown in figs. 3 a-3 c, the semiconductor devices includes：
Along the bit line of first direction setting, the bit line is electrically connected with device below；
Wherein, the bit line includes the first bit line 305 and the second bit line 307 being staggered up and down, and described first
Bit line 305 and second bit line 307 are arranged alternately in the second direction perpendicular with the first direction.
Specifically, wherein it refers to adjacent two to be staggered and be arranged alternately up and down between first bit line and the second bit line
Interval between a first bit line is corresponding up and down with the second bit line, on the interval and the first bit line between two neighboring second bit line
Lower correspondence.
Wherein, as shown in Figure 3A, Fig. 3 A are the vertical view of heretofore described semiconductor devices neutrality line, wherein left hand view
Shape is the vertical view of the layer where the first bit line 305, and right figure is the vertical view of the layer where the second bit line 307, first
Line 305 and second bit line 307 are located in two layers to be staggered up and down, therefore change same layer position in current technique and hand over
The mode of mistake setting, the mode for selecting different layers to be staggered can preferably improve Jie between bit line by the change
Electric spacing improves the process window of bit line.
Wherein, the bit line is metal wire, is used to each device in same direction, such as first direction forming electricity
Connection, such as the bit line are used to the source electrode (not shown) of the transistor in the substrate 301 forming electrical connection, such as scheme
Shown in 3B.
Wherein, the bit line is elongated metal line, and the extending direction of the bit line is defined as first direction, wherein
Wordline 308 is formed in perpendicular second direction with first direction, wherein the grid of the wordline 308 and the transistor
Electrical connection, as shown in Figure 3A, wherein the wordline can be the conventional wordline in this field, details are not described herein.
Wherein, first bit line and second bit line are located in two dielectric layers of stacked on top setting.
Such as first bit line is set in the first dielectric layer 309 in the present invention, second bit line is set to
In two dielectric layers 310, wherein second dielectric layer 310 is located on first dielectric layer 309, and then is formed and interlocked up and down
The bit line of setting.
The wherein described upper and lower directions refers to the direction of device stacked on top unless otherwise specified.
The semiconductor devices further includes：
Contact structures, between the bit line and the device, the both ends of the contact structures respectively with the bit line
It is electrically connected with the device.
The contact structures include the first contact that height is different on the direction extended from contact structures to the bit line
Structure 303 and the second contact structures 304, first contact structures 303 are electrically connected with first bit line 305, and described second
Contact structures 304 are electrically connected with second bit line 307.
Wherein, since first bit line and second bit line are staggered up and down, first contact structures
303 and second contact structures 304 be highly different in the up-down direction, to meet first bit line and second bit line
The demand being staggered up and down.
Substrate 301 is provided, interlayer dielectric layer 302 is formed in the substrate 301, in the interlayer dielectric layer 302
It is formed with interconnection structure, the device being electrically connected with the interconnection structure is formed in the substrate, is formed in a first direction
Bit line, the bit line are electrically connected by the interconnection structure with device below.
Wherein the substrate 301 can be following at least one of the material being previously mentioned：Silicon, silicon-on-insulator (SOI),
Be laminated on insulator silicon (SSOI), stacking SiGe (S-SiGeOI) on insulator, germanium on insulator SiClx (SiGeOI) and
Germanium on insulator (GeOI) etc..
Wherein, it is formed with various devices in the substrate 301, such as is formed with various cmos devices and passive device
Deng.
As an example, the first functional component can also be formed in substrate 301, such as transistor, interconnection structure and penetrate
Frequency device.
Wherein, transistor can be normal transistor, high-k/metal gate transistors, fin transistor or other are suitable
Transistor.Interconnection structure may include metal layer (such as layers of copper or aluminium layer), metal plug etc..Radio-frequency devices may include inductance
(inductor) devices such as.
In addition to including transistor, radio-frequency devices and interconnection structure, cmos device can also include other various feasible groups
Part, such as resistance, capacitance, MEMS device etc., are not defined herein.
Wherein, the concrete structure and forming method of the various components in cmos device, those skilled in the art can roots
It is selected with reference to the prior art according to actual needs, details are not described herein again.
It is formed with interlayer dielectric layer 302 on the substrate, wherein the interlayer dielectric layer 302 can be silicon oxide layer, packet
It includes and is formed using thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process
There are the material layer of doped or undoped silica, such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron phosphorus
Silica glass (BPSG).In addition, interlayer dielectric layer 302 can also be the spin cloth of coating-type glass (spin- for adulterating boron or adulterating phosphorus
On-glass, SOG), doping phosphorus tetraethoxysilane (PTEOS) or boron-doped tetraethoxysilane (BTEOS).Its thickness
It is not limited to a certain numerical value.
The interlayer dielectric layer 302 can also be plasma reinforced chemical vapour deposition oxide or low- K insulating layer material
Expect (such as black brick, black diamond).
Then be formed with interconnection structure in the interlayer dielectric layer, wherein the interconnection structure include contact structures with
Metal layer is arranged alternately.
Wherein, the contact structures include through-hole and contact hole, and the first contact is formed in the interlayer dielectric layer 302
Structure 303 is used to be electrically connected with the first bit line wherein first contact structures 303 select through-hole.
Wherein, the device is transistor, the source electrode of first contact structures 303 and the transistor in the present invention
Electrical connection.
In addition, being formed with the first dielectric layer 309, the interlayer dielectric layer 302 and first on the interlayer dielectric layer 302
Etching stopping layer can also be formed between dielectric layer 309, for the terminal as etching.
Wherein first dielectric layer 309 can be silicon oxide layer, including the use of thermal chemical vapor deposition (thermal CVD)
The material layer for having doped or undoped silica that manufacturing process or high-density plasma (HDP) manufacturing process are formed, example
Such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).First dielectric layer 309 also may be used
To be the tetraethoxysilane for adulterating boron or adulterating the spin cloth of coating-type glass (spin-on-glass, SOG) of phosphorus, doping phosphorus
(PTEOS) or boron-doped tetraethoxysilane (BTEOS).Its thickness is not limited to a certain numerical value.First dielectric layer
309 can also be plasma reinforced chemical vapour deposition oxide or low- K insulating layer material (such as black brick, black
diamond)。
The side wall of first contact structures can be vertical or inclined, it is not limited to a certain.
First contact structures are reverse trapezoid shape in the present invention.
Similarly, the second contact structures 304, institute are also formed in the interlayer dielectric layer 302 and the first dielectric layer 309
The second contact structures 304 are stated to be electrically connected with second bit line 307.
Optionally, the side wall of second contact structures 304 can be vertical or inclined, it is not limited to a certain
Kind.
Second contact structures are reverse trapezoid shape in the present invention.
Wherein, first bit line 305 can select conductive material, such as can select metal material or doped
Semiconductor material layer, in the present invention bottom electrode material layer preferred metal materials, such as the metal material include Pt,
One or more of Au, Cu, Ti and W are in the present invention Ni metal, select Ni metal that can not only reduce cost, and
And selection metallic copper forms the technique of the silicon hole and prior art can be compatible with process simplification.
The second dielectric layer 310 for covering first dielectric layer is formed on first dielectric layer；The second
Line is formed in second dielectric layer.
Second dielectric layer 310 can be silicon oxide layer, be manufactured including the use of thermal chemical vapor deposition (thermal CVD)
The material layer for having doped or undoped silica that technique or high-density plasma (HDP) manufacturing process are formed, such as not
Doped silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).Second dielectric layer 310 can also be
It adulterates boron or adulterates the spin cloth of coating-type glass (spin-on-glass, SOG) of phosphorus, adulterates the tetraethoxysilane (PTEOS) of phosphorus
Or boron-doped tetraethoxysilane (BTEOS).Its thickness is not limited to a certain numerical value.Second dielectric layer 310 may be used also
To be plasma reinforced chemical vapour deposition oxide or low- K insulating layer material (such as black brick, black diamond).
It can also be formed with etching stopping layer between second dielectric layer 310 and first dielectric layer 309.
Wherein, second bit line 307 can select conductive material, such as can select metal material or doped
Semiconductor material layer, in the present invention bottom electrode material layer preferred metal materials, such as the metal material include Pt,
One or more of Au, Cu, Ti and W are in the present invention Ni metal, select Ni metal that can not only reduce cost, and
And selection metallic copper forms the technique of the silicon hole and prior art can be compatible with process simplification.
Wherein, the substrate includes center and peripheral region, the week of the peripheral region being arranged in the center
Enclose, the set-up mode of the bit line in the peripheral region with the bit line of center set-up mode, as shown in Figure 3 C, described
Further include the gate via being connected with grid and metal layer 306 in peripheral region.
The present invention provides a kind of semiconductor devices, are set as interlocking up and down by the bit line in the semiconductor devices
Two layers, i.e., the described bit line includes the first bit line and the second bit line being staggered up and down, and first bit line and described
Second bit line is arranged alternately on the direction perpendicular with the first direction.It can be subtracted to avoid due to size by the setting
It is small that dielectric spacing between bit line is caused to reduce the breakdown problem brought, by be staggered up and down can make same layer between it is adjacent
Bit line spacing becomes larger, due to being located at different layers between adjacent bit line, the problem that spacing will not be brought too small, therefore can be into
One step improves the performance and yield of device.
Embodiment two
In the following, the one exemplary side of manufacturing method for the semiconductor devices that embodiment proposes with reference to the accompanying drawings to describe the present invention
The detailed step of method.Wherein, Fig. 4 A-4F are heretofore described semiconductor devices neutrality line preparation process cuing open along word-line direction
View；Fig. 5 is a kind of schematic flow chart of the manufacturing method of semiconductor devices of one embodiment of the present of invention.
Fig. 5 is a kind of schematic flow chart of the manufacturing method of semiconductor devices of an alternative embodiment of the invention, tool
Include body：
Step S1：Bit line is formed in a first direction, and the bit line is electrically connected with device below；Wherein, institute's rheme
Line includes the first bit line and the second bit line being staggered up and down, and first bit line and second bit line with it is described
It is arranged alternately in the perpendicular second direction of first direction.
The manufacturing method of the semiconductor devices of the present embodiment, specifically comprises the following steps：
First as shown in Figure 4 A, substrate 301 is provided, interlayer dielectric layer 302 is formed in the substrate 301, described
It is formed with interconnection structure in interlayer dielectric layer 302, the device being electrically connected with the interconnection structure is formed in the substrate,
First party is upwardly formed bit line, and the bit line is electrically connected by the interconnection structure with device below.
Specifically, as described in Fig. 4 A, wherein the substrate 301 can be following at least one of the material being previously mentioned：
Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI) on insulator, on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc..
Wherein, it is formed with various devices in the substrate 301, such as is formed with various cmos devices and passive device
Deng.
As an example, the first functional component can also be formed in substrate 301, such as transistor, interconnection structure and penetrate
Frequency device.
Wherein, transistor can be normal transistor, high-k/metal gate transistors, fin transistor or other are suitable
Transistor.Interconnection structure may include metal layer (such as layers of copper or aluminium layer), metal plug etc..Radio-frequency devices may include inductance
(inductor) devices such as.
In addition to including transistor, radio-frequency devices and interconnection structure, cmos device can also include other various feasible groups
Part, such as resistance, capacitance, MEMS device etc., are not defined herein.
Wherein, the concrete structure and forming method of the various components in cmos device, those skilled in the art can roots
It is selected with reference to the prior art according to actual needs, details are not described herein again.
Interlayer dielectric layer 302 is formed on the substrate, wherein the interlayer dielectric layer 302 can be silicon oxide layer, including
Have using what thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process were formed
The material layer of doped or undoped silica, such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron phosphorus silicon
Glass (BPSG).In addition, interlayer dielectric layer 302 can also be the spin cloth of coating-type glass (spin-on- for adulterating boron or adulterating phosphorus
Glass, SOG), doping phosphorus tetraethoxysilane (PTEOS) or boron-doped tetraethoxysilane (BTEOS).Its thickness is simultaneously
It is not limited to a certain numerical value.The interlayer dielectric layer 302 can also be plasma reinforced chemical vapour deposition oxide or low K
Insulating layer material (such as black brick, black diamond).
Then interconnection structure is formed in the interlayer dielectric layer, wherein the interconnection structure includes contact structures and gold
Belong to layer to be arranged alternately.
Wherein, the contact structures include through-hole and contact hole, and the first contact is formed in the interlayer dielectric layer 302
Structure 303 is used to be electrically connected with the first bit line wherein first contact structures 303 select through-hole.
Wherein, the device selects transistor, the source of first contact structures 303 and the transistor in the present invention
Pole is electrically connected.
The forming method of the bit line is further described below in conjunction with the accompanying drawings.
First, step 1 is executed, forms the first dielectric layer 309, the interlayer dielectric layer on the interlayer dielectric layer 302
It can also be formed with etching stopping layer (not shown) between 302 first dielectric layers 309, be used for the terminal as etching,
This is repeated no more.
Wherein first dielectric layer 309 can be silicon oxide layer, including the use of thermal chemical vapor deposition (thermal CVD)
The material layer for having doped or undoped silica that manufacturing process or high-density plasma (HDP) manufacturing process are formed, example
Such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).First dielectric layer 309 also may be used
To be the tetraethoxysilane for adulterating boron or adulterating the spin cloth of coating-type glass (spin-on-glass, SOG) of phosphorus, doping phosphorus
(PTEOS) or boron-doped tetraethoxysilane (BTEOS).Its thickness is not limited to a certain numerical value.First dielectric layer
309 can also be plasma reinforced chemical vapour deposition oxide or low- K insulating layer material (such as black brick, black
diamond)。
Then mask stack is formed on first dielectric layer 309, as shown in Figure 4 A, wherein the mask stack can be with
Including but not limited to organic insulator (ODL), bottom antireflective coating (Bottom Anti Reflective Coating,
BARC) or photoresist layer etc., details are not described herein.
Step 2 is executed, first dielectric layer is patterned, to form the first opening for exposing first contact structures.
Specifically, as shown in Figure 4 B, the first opening is formed, to expose first contact structures, wherein described first opens
The forming method of mouth can select conventional patterning method, such as form mask stack and carry out dry etching or wet method erosion
It carves, and then forms first opening.
The method of self-aligned double patterning case is selected to form first opening, the side of the self-aligned double patterning case in this application
Method includes：
Step A1：Mask stack is formed on first dielectric layer, forms photoresist layer on the mask stack, and
It is exposed development, to form cylindricality pattern；
Step A2：Using the cylindricality pattern as mask stack described in mask etch, and then form the cylindricality knot of mask stack
Structure；
Step A3：Conformal deposited spacer material layer, to cover the column construction；
Step A4：The spacer material layer is etched, to form clearance wall on the side wall of the column construction；
Step A5：The column construction is removed, the clearance wall is only retained；
Step A6：Using the clearance wall as the first dielectric layer described in mask etch, and then form first opening.
Wherein, the photoresist layer can select positive photoresist or negative photoresist etc., it is not limited to a certain.
Wherein, one kind that the method for above-mentioned self-aligned double patterning case is merely exemplary, the present invention can also select others
Double patterning method does not limit to the example.
Wherein, in the step A6, the first opening in order to obtain bigger depth-to-width ratio can to reduce the size of opening
First opening is formed in the method for selecting deep reaction ion etching (DRIE), such as in the deep reaction ion etching
(DRIE) gas hexa-fluoride (SF is selected in step6) be used as process gas, apply radio-frequency power supply so that hexa-fluoride react into
Gas forms high ionization, and control operating pressure is 20mTorr-8Torr in the etching step, power 600W, and frequency is
13.5MHz, Dc bias can the continuous control in -500V-1000V, ensure the needs of anisotropic etching, select deep reaction
Ion etching (DRIE) can keep very high etching photoresist selection ratio.Deep reaction ion etching (DRIE) system can be with
Select the common equipment of ability, it is not limited to a certain model.
Wherein, the side wall of first opening can be vertical or inclined, it is not limited to a certain.
First opening is reverse trapezoid shape in the present invention.
Step 3 is executed, the depositing bitlines material layer in first opening, to form first bit line 305.
Specifically, as shown in Figure 4 C, the bit line material layer can select chemical vapor deposition (CVD) in this step
Low-pressure chemical vapor deposition (LPCVD), the laser of the formation such as method, physical vapour deposition (PVD) (PVD) method or atomic layer deposition (ALD) method
One kind in ablation deposition (LAD) and selective epitaxy growth (SEG).Preferred atomic layer deposition (ALD) method in the present invention.
Wherein, first bit line 305 can select conductive material, such as can select metal material or doped
Semiconductor material layer, in the present invention bottom electrode material layer preferred metal materials, such as the metal material include Pt,
One or more of Au, Cu, Ti and W are in the present invention Ni metal, select Ni metal that can not only reduce cost, and
And selection metallic copper forms the technique of the silicon hole and prior art can be compatible with process simplification.
Step 4 is executed, the interlayer dielectric layer 302 and first dielectric layer 309 are patterned, at described first
Contact openings are formed between line, expose the device.
Specifically, as shown in Figure 4 D, the method for self-aligned double patterning case can equally be selected to form described connect in this step
Opening is touched, specific steps are referred to other double patterning methods in step 2 or this field, and details are not described herein.
Wherein, engraving method can also select deep reaction ion etching (DRIE), and details are not described herein.
Step 5 is executed, as shown in Figure 4 E, is formed on first dielectric layer and covers the second of first dielectric layer
Dielectric layer 310；Second dielectric layer is patterned, to form the second opening and expose the contact openings.
Specifically, as shown in Figure 4 E, second dielectric layer 310 can be silicon oxide layer in this step, including the use of heat
Doping that chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process were formed have or
The material layer of undoped silica, such as undoped silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass
(BPSG).Second dielectric layer 310 can also be adulterate boron or adulterate phosphorus spin cloth of coating-type glass (spin-on-glass,
SOG the tetraethoxysilane (PTEOS) or boron-doped tetraethoxysilane (BTEOS) of phosphorus), are adulterated.Its thickness does not limit to
In a certain numerical value.Second dielectric layer 310 can also be plasma reinforced chemical vapour deposition oxide or low- K insulating layer
Material (such as black brick, black diamond).
It can also be formed with etching stopping layer between second dielectric layer 310 and first dielectric layer.
Wherein, the method that the method for forming the second opening can select self-aligned double patterning case forms the contact openings, has
Body step is referred to other double patterning methods in step 2 or this field, and details are not described herein.
Wherein, engraving method can also select deep reaction ion etching (DRIE), and details are not described herein.
Optionally, second opening is reverse trapezoid shape.
Step 6 is executed, depositing bitlines material layer, filling second opening and the contact openings connect to form second
Touch structure and second bit line.
Specifically, as illustrated in figure 4f, depositing bitlines material layer is opened with filling second opening and the contact simultaneously
Mouthful, it is formed simultaneously the second contact structures 304 and second bit line 307.
It can be formed simultaneously second contact structures 304 and second bit line 307 in this step, can also first fill out
The contact openings are filled, second contact structures 304 are formed, second opening is refilled, forms second bit line afterwards
307, specific method is not further herein to be limited.
The bit line material layer can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) in this step
Low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the choosing of the formation such as method or atomic layer deposition (ALD) method
Select one kind in epitaxial growth (SEG).Preferred atomic layer deposition (ALD) method in the present invention.
Wherein, second bit line 307 can select conductive material, such as can select metal material or doped
Semiconductor material layer, in the present invention bottom electrode material layer preferred metal materials, such as the metal material include Pt,
One or more of Au, Cu, Ti and W are in the present invention Ni metal, select Ni metal that can not only reduce cost, and
And selection metallic copper forms the technique of the silicon hole and prior art can be compatible with process simplification.
So far, the introduction for preparing the semiconductor devices of the embodiment of the present invention is completed.After the above step, may be used also
To include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the manufacturing method of the present embodiment may be used also
To include other steps among above-mentioned each step or between different steps, these steps can be by current technique
Various techniques realize that details are not described herein again.
The present invention provides a kind of semiconductor devices and preparation method thereof, set the bit line in the semiconductor devices
It is set to two layers up and down staggeredly, i.e., the described bit line includes the first bit line and the second bit line being staggered up and down, and described the
One bit line and second bit line are arranged alternately on the direction perpendicular with the first direction.It can be kept away by the setting
Exempt to cause dielectric spacing between bit line to reduce the breakdown problem brought since size reduces, by be staggered up and down can make it is same
Adjacent bit line spacing becomes larger between layer, due to being located at different layers between adjacent bit line, will not bring spacing is too small to ask
Topic, therefore the performance and yield of device can be further increased.
Embodiment three
The present invention also provides a kind of electronic devices, including the semiconductor devices described in embodiment one.Wherein, semiconductor device
Part is the semiconductor devices described in embodiment one, or the semiconductor devices that the preparation method according to embodiment two obtains.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
Standby or any intermediate products for including circuit.The electronic device of the embodiment of the present invention, due to the use of above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Fig. 6 shows the example of mobile phone handsets.Mobile phone handsets 400, which are equipped with, to be included in shell 401
Display portion 402, operation button 403, external connection port 404, loud speaker 405, microphone 406 etc..
The wherein described mobile phone handsets include the semiconductor devices described in embodiment one, and the semiconductor devices includes：
Along the bit line of first direction setting, the bit line is electrically connected with device below；Wherein, the bit line includes staggeredly setting up and down
The first bit line and the second bit line set, and first bit line and second bit line are perpendicular with the first direction
It is arranged alternately in second direction.It sets the bit line to two layers interlocked up and down, i.e. institute's rheme in the semiconductor devices
Line includes the first bit line and the second bit line being staggered up and down, and first bit line and second bit line with it is described
First direction is arranged alternately on perpendicular direction.It can be caused to be situated between bit line to avoid due to size reduction by the setting
Electric spacing reduces the breakdown problem brought, by be staggered up and down can make same layer between adjacent bit line spacing become larger, phase
Due to being located at different layers between adjacent bit line, the problem that spacing will not be brought too small, therefore device can be further increased
Performance and yield.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (15)
1. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes：
Along the bit line of first direction setting, the bit line is electrically connected with device below；
Wherein, the bit line includes the first bit line and the second bit line being staggered up and down, and first bit line and described
Second bit line is arranged alternately in the second direction perpendicular with the first direction.
2. semiconductor devices according to claim 1, which is characterized in that the semiconductor devices further includes：
Contact structures, between the bit line and the device, the both ends of the contact structures respectively with the bit line and institute
State device electrical connection.
3. semiconductor devices according to claim 2, which is characterized in that the contact structures include different first of height
Contact structures and the second contact structures, first contact structures are electrically connected with first bit line, second contact structures
It is electrically connected with second bit line.
4. semiconductor devices according to claim 1, which is characterized in that the semiconductor devices further includes：
Along the wordline of second direction setting.
5. semiconductor devices according to claim 4, which is characterized in that the device includes transistor, the bit line with
The source electrode of the transistor is electrically connected, and the wordline is electrically connected with the grid of the transistor.
6. semiconductor devices according to claim 1, which is characterized in that the semiconductor devices includes memory cell region
With the peripheral region on the outside of the storage unit, wherein be respectively formed in the memory cell region and the peripheral region
Rheme line.
7. a kind of preparation method of semiconductor devices, which is characterized in that the method includes：
Bit line is formed in a first direction, and the bit line is electrically connected with device below；
Wherein, the bit line includes the first bit line and the second bit line being staggered up and down, and first bit line and described
Second bit line is arranged alternately in the second direction perpendicular with the first direction.
8. the method according to the description of claim 7 is characterized in that the method for forming first bit line and second bit line
Including：
The substrate for including the device is provided, is formed on the substrate in the first dielectric layer and electric with the device
First bit line of connection；
The second dielectric layer is formed on first dielectric layer；
The second bit line being electrically connected with the device is formed in second dielectric layer.
9. according to the method described in claim 8, it is characterized in that, the method for forming first bit line includes：
Substrate comprising the device and the interlayer dielectric layer in the substrate are provided, formed in the interlayer dielectric layer
There are the first contact structures；
The first dielectric layer is formed above first contact structures；
First dielectric layer is patterned, to form the first opening for exposing first contact structures；
The depositing bitlines material layer in first opening, to form first bit line.
10. according to the method described in claim 9, it is characterized in that, the method for forming second bit line includes：
First dielectric layer and the interlayer dielectric layer are patterned, to be formed between first bit line in a second direction
Contact openings expose the device；
The second dielectric layer for covering first dielectric layer is formed on first dielectric layer；
Second dielectric layer is patterned, to form the second opening and expose the contact openings；
Depositing bitlines material layer forms the second contact structures and described second to fill second opening and the contact openings
Bit line.
11. according to the method described in claim 10, it is characterized in that, forming described first using the method for self-aligned double patterning case
Opening, the contact openings and/or second opening.
12. according to the method for claim 11, which is characterized in that the method for the self-aligned double patterning case includes：
Sequentially form mask stack and photoresist layer on first dielectric layer or second dielectric layer, and to the photoresist into
Row exposure imaging, to form cylindricality pattern；
Using the cylindricality pattern as mask stack described in mask etch, and then form the column construction of mask stack；
Conformal deposited spacer material layer, to cover the column construction；
The spacer material layer is etched, to form clearance wall on the side wall of the column construction；
It removes the column construction and retains the clearance wall；
Using the clearance wall as the first dielectric layer described in mask etch, to form first opening；Or with the clearance wall
For the second dielectric layer described in mask etch and first dielectric layer, it is open with forming described second.
13. the method according to the description of claim 7 is characterized in that the method further include before forming the bit line or
The step of wordline is formed after person, the wordline is arranged in a second direction.
14. according to the method for claim 13, which is characterized in that the device includes transistor, the bit line with it is described
The source electrode of transistor is electrically connected, and the wordline is electrically connected with the grid of the transistor.
15. a kind of electronic device, which is characterized in that the electronic device includes the semiconductor device described in one of claim 1 to 6
Part.
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| WO2023010003A1 (en) * | 2021-07-27 | 2023-02-02 | Micron Technology, Inc. | Electronic devices comprising multilevel bitlines, and related methods and systems |
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| CN108735711B (en) | 2021-04-23 |
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