CN108735711B

CN108735711B - Semiconductor device, preparation method thereof and electronic device

Info

Publication number: CN108735711B
Application number: CN201710240157.5A
Authority: CN
Inventors: 张永兴; 杨海玩; 李晓波
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-04-13
Filing date: 2017-04-13
Publication date: 2021-04-23
Anticipated expiration: 2037-04-13
Also published as: CN108735711A

Abstract

The invention relates to a semiconductor device, a manufacturing method thereof and an electronic device. The semiconductor device includes: a bit line disposed along a first direction, the bit line electrically connected to a device therebelow; the bit lines comprise first bit lines and second bit lines which are arranged in an up-and-down staggered mode, and the first bit lines and the second bit lines are arranged in a second direction perpendicular to the first direction in an alternating mode. Through the arrangement, the breakdown problem caused by reduction of the dielectric distance between the bit lines due to size reduction can be avoided, the distance between the adjacent bit lines on the same layer can be increased through the up-down staggered arrangement, and the problem that the distance is too small due to the fact that the adjacent bit lines are located on different layers can be avoided, so that the performance and the yield of the device can be further improved.

Description

Semiconductor device, preparation method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method thereof and an electronic device.

Background

In order to increase the integration density of semiconductor memory devices, which are receiving attention due to increasing demands for high-capacity semiconductor memory devices, many different methods have been used in the prior art, such as forming a plurality of memory cells on a single wafer by reducing the wafer size and/or changing the internal structural unit, and for increasing the integration density by changing the cell structure, attempts have been made to reduce the cell area by changing the planar arrangement of the active region or changing the cell layout.

As semiconductor device dimensions continue to shrink, bit line processes have become challenging due to advances in technology nodes. Due to the continuous progress of the technical nodes, the feature size of the device is continuously reduced, the critical dimension of the bit line and the sheet resistance (Rs) of the bit line are limited, copper is usually selected as the bit line metal in order to reduce the sheet resistance (Rs), and an inverted trapezoid shape is usually selected in order to obtain better copper filling performance, so that the dielectric distance between adjacent bit lines is further reduced, and the breakdown performance between the bit lines is influenced, and further the performance and the yield of the device are influenced.

Therefore, it is desirable to provide a new semiconductor device and a method for manufacturing the same to solve the above problems in the prior art.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to overcome the problems existing at present, the present invention provides a semiconductor device comprising:

a bit line disposed along a first direction, the bit line electrically connected to a device therebelow;

the bit lines comprise first bit lines and second bit lines which are arranged in an up-and-down staggered mode, and the first bit lines and the second bit lines are arranged in a second direction perpendicular to the first direction in an alternating mode.

Optionally, the semiconductor device further comprises:

and the contact structure is positioned between the bit line and the device, and two ends of the contact structure are respectively and electrically connected with the bit line and the device.

Optionally, the contact structure includes a first contact structure and a second contact structure having different heights, the first contact structure is electrically connected to the first bit line, and the second contact structure is electrically connected to the second bit line.

Optionally, the semiconductor device further comprises:

word lines arranged along the second direction.

Optionally, the device comprises a transistor, the bit line is electrically connected to a source of the transistor, and the word line is electrically connected to a gate of the transistor.

Optionally, the semiconductor device includes a memory cell region and a peripheral region outside the memory cell, wherein the bit line is formed in both the memory cell region and the peripheral region.

The invention also provides a preparation method of the semiconductor device, which comprises the following steps:

forming a bit line in a first direction, the bit line being electrically connected with a device therebelow;

Optionally, the method of forming the first bit line and the second bit line comprises:

providing a substrate containing the device, and forming a first bit line in a first dielectric layer and electrically connected with the device on the substrate;

forming a second dielectric layer on the first dielectric layer;

forming a second bit line in the second dielectric layer in electrical connection with the device.

Optionally, the method of forming the first bit line comprises:

providing a substrate containing the device and an interlayer dielectric layer positioned on the substrate, wherein a first contact structure is formed in the interlayer dielectric layer;

forming a first dielectric layer over the first contact structure;

patterning the first dielectric layer to form a first opening exposing the first contact structure;

depositing a bit line material layer in the first opening to form the first bit line.

Optionally, the method of forming the second bit line comprises:

patterning the first dielectric layer and the interlevel dielectric layer to form contact openings between the first bit lines in a second direction, exposing the devices;

forming a second dielectric layer on the first dielectric layer covering the first dielectric layer;

patterning the second dielectric layer to form a second opening and expose the contact opening;

and depositing a bit line material layer to fill the second opening and the contact opening to form a second contact structure and the second bit line.

Optionally, the first opening, the contact opening and/or the second opening are formed using a self-aligned double patterning method.

Optionally, the method of self-aligning double patterns comprises:

sequentially forming a mask lamination layer and a photoresist layer on the first dielectric layer or the second dielectric layer, and exposing and developing the photoresist to form a cylindrical pattern;

etching the mask lamination by taking the cylindrical pattern as a mask so as to form a cylindrical structure of the mask lamination;

conformally depositing a spacer material layer to cover the columnar structure;

etching the spacer material layer to form a spacer on the sidewall of the pillar structure;

removing the columnar structure and reserving the gap wall;

etching the first dielectric layer by using the gap wall as a mask to form the first opening; or etching the second dielectric layer and the first dielectric layer by using the gap wall as a mask to form the second opening.

Optionally, the method further comprises the step of forming a word line before or after forming the bit line, the word line being arranged in the second direction.

The invention also provides an electronic device comprising the semiconductor device.

In order to overcome the problems in the prior art, the present invention provides a semiconductor device and a method for manufacturing the same, in which bit lines are arranged in two layers staggered up and down, that is, the bit lines include first bit lines and second bit lines staggered up and down, and the first bit lines and the second bit lines are alternately arranged in a second direction perpendicular to the first direction. Through the arrangement, the breakdown problem caused by reduction of the dielectric distance between the bit lines due to size reduction can be avoided, the distance between the adjacent bit lines on the same layer can be increased through the up-down staggered arrangement, and the problem that the distance is too small due to the fact that the adjacent bit lines are located on different layers can be avoided, so that the performance and the yield of the device can be further improved.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 is a top view of a bitline in a semiconductor device according to the prior art;

fig. 2A is a cross-sectional view of a bit line in a semiconductor device according to the related art, taken along a word line direction;

fig. 2B is a cross-sectional view of a peripheral region in the semiconductor device in the prior art, taken along a word line direction;

FIG. 3A is a top view of a bit line in the semiconductor device of the present invention;

fig. 3B is a cross-sectional view of a bit line in the semiconductor device according to the present invention, taken along a word line direction;

fig. 3C is a cross-sectional view of a peripheral region in the semiconductor device according to the present invention, taken along a word line direction;

FIGS. 4A-4F are cross-sectional views of a process for fabricating a bit line in a semiconductor device according to the present invention, taken along a word line direction;

fig. 5 is a schematic flow chart of a method of manufacturing a semiconductor device of an embodiment of the present invention;

fig. 6 shows a schematic view of an electronic device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

The bit lines are arranged in the manner shown in fig. 1, wherein

adjacent bit lines

205 and 206 are located in the same layer and are arranged in a staggered manner in the extending direction of the bit lines, wherein the

bit lines

205 and 206 are electrically connected to the device below, for example, the device includes a via 203 formed in a dielectric layer 202, a metal layer may be formed below the via 203, and a metal interconnection structure is formed, and the metal interconnection structure is electrically connected to an IC circuit or a transistor device formed in a substrate 201, as shown in fig. 2A. The substrate includes a central region and a peripheral region, the peripheral region is disposed around the central region, the bit lines in the peripheral region are disposed in the same manner as the bit lines in the central region, as shown in fig. 2B, and the peripheral region further includes a gate via 204 and a metal layer 207 connected to the gate.

To this end, in order to solve the problems existing at present, the present invention provides a semiconductor device, as shown in fig. 3A to 3C, including:

the bit lines include first bit lines 305 and second bit lines 307 arranged to be staggered up and down, and the first bit lines 305 and the second bit lines 307 are alternately arranged in a second direction perpendicular to the first direction.

Specifically, the first bit lines and the second bit lines are arranged in a vertically staggered manner and in an alternating manner, that is, the intervals between two adjacent first bit lines correspond to the second bit lines vertically, and the intervals between two adjacent second bit lines correspond to the first bit lines vertically.

As shown in fig. 3A, fig. 3A is a top view of bit lines in the semiconductor device of the present invention, wherein the left side of the graph is a top view of a layer where the second bit line 307 is located, the right side of the graph is a top view of a layer where the first bit line 305 is located, and the first bit line 305 and the second bit line 307 are located in two layers which are staggered up and down, so that a staggered manner of a same layer position in the current process is changed, and a staggered manner of different layers is selected, by which a dielectric distance between bit lines can be better increased, and a process window of the bit lines is improved.

The bit lines are metal lines for electrically connecting devices in the same direction, for example, a first direction, for example, the bit lines are used for electrically connecting sources (not shown) of transistors in the substrate 301, as shown in fig. 3B.

The bit lines are strip-shaped metal lines, the extending direction of the bit lines is defined as a first direction, and word lines are formed in a second direction perpendicular to the first direction, wherein the word lines are electrically connected to the gates of the transistors, as shown in fig. 3A, and the word lines may be conventional word lines in the art, which is not described herein again.

Wherein the first bit line and the second bit line are located in two dielectric layers stacked one above the other.

For example, in the present invention, the first bit line is disposed in the first dielectric layer 309, and the second bit line is disposed in the second dielectric layer 310, wherein the second dielectric layer 310 is disposed on the first dielectric layer 309, thereby forming bit lines staggered up and down.

Wherein the up-down direction refers to a direction in which devices are stacked up and down without specific description.

The semiconductor device further includes:

The contact structure includes a first contact structure 303 and a second contact structure 304 having different heights, the first contact structure 303 is electrically connected to the first bit line 305, and the second contact structure 304 is electrically connected to the second bit line 307. The height is a dimension in a thickness direction of the substrate, that is, a direction in which the contact structure points to the bit line, and in the present application, the explanation is highly referred to unless otherwise specified.

Wherein, because the first bit lines and the second bit lines are arranged in a staggered manner, the heights of the first contact structures 303 and the second contact structures 304 are different in the vertical direction, so as to meet the requirement that the first bit lines and the second bit lines are arranged in a staggered manner.

The invention provides a semiconductor device and a preparation method thereof, wherein bit lines are arranged in two layers which are staggered up and down in the semiconductor device, namely the bit lines comprise first bit lines and second bit lines which are staggered up and down, and the first bit lines and the second bit lines are alternately arranged in a direction perpendicular to the first direction. Through the arrangement, the breakdown problem caused by reduction of the dielectric distance between the bit lines due to size reduction can be avoided, the distance between the adjacent bit lines on the same layer can be increased through the up-down staggered arrangement, and the problem that the distance is too small due to the fact that the adjacent bit lines are located on different layers can be avoided, so that the performance and the yield of the device can be further improved.

Example one

The present invention provides a semiconductor device, as shown in fig. 3A to 3C, including:

As shown in fig. 3A, fig. 3A is a top view of bit lines in the semiconductor device of the present invention, wherein a left side pattern is a top view of a layer where a first bit line 305 is located, a right side pattern is a top view of a layer where a second bit line 307 is located, and the first bit line 305 and the second bit line 307 are located in two layers which are staggered up and down, so that a manner of staggering positions of the same layer in the prior art is changed, and a manner of staggering different layers is selected, by which a dielectric distance between the bit lines can be better increased, and a process window of the bit lines is improved.

The bit lines are strip-shaped metal lines, the extending direction of the bit lines is defined as a first direction, and word lines 308 are formed in a second direction perpendicular to the first direction, wherein the word lines 308 are electrically connected to the gates of the transistors, as shown in fig. 3A, and the word lines may be conventional word lines in the art, which is not described herein again.

The semiconductor device further includes:

The contact structure includes a first contact structure 303 and a second contact structure 304 which are different in height in a direction extending from the contact structure to the bit line, the first contact structure 303 is electrically connected to the first bit line 305, and the second contact structure 304 is electrically connected to the second bit line 307.

Providing a substrate 301, forming an interlayer dielectric layer 302 on the substrate 301, forming an interconnection structure in the interlayer dielectric layer 302, forming a device electrically connected with the interconnection structure in the substrate, and forming a bit line in a first direction, wherein the bit line is electrically connected with the device below the bit line through the interconnection structure.

Wherein the substrate 301 may be at least one of the following mentioned materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.

Various devices, such as various CMOS devices and passive devices, are formed in the substrate 301.

As an example, first functional components such as transistors, interconnect structures, and radio frequency devices may also be formed in the substrate 301.

The transistors may be normal transistors, high-k metal gate transistors, fin-type transistors, or other suitable transistors. The interconnect structure may include a metal layer (e.g., a copper or aluminum layer), a metal plug, and the like. The radio frequency device may include an inductor (inductor) or the like.

In addition to transistors, rf devices, and interconnect structures, CMOS devices may include various other possible components, such as resistors, capacitors, MEMS devices, and the like, without limitation.

The specific structure and the forming method of each component in the CMOS device may be selected by those skilled in the art according to actual needs by referring to the prior art, and are not described herein again.

An interlayer dielectric layer 302 is formed on the substrate, wherein the interlayer dielectric layer 302 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer 302 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron. The thickness thereof is not limited to a certain value.

The interlayer dielectric layer 302 may also be a plasma enhanced chemical vapor deposition oxide or a low K dielectric layer material (such as black brick).

And then forming an interconnection structure in the interlayer dielectric layer, wherein the interconnection structure comprises contact structures and metal layers which are alternately arranged.

The contact structure includes a via hole and a contact hole, and a first contact structure 303 is formed in the interlayer dielectric layer 302, wherein the first contact structure 303 is a via hole for electrically connecting to a first bit line.

In the present invention, the device is a transistor, and the first contact structure 303 is electrically connected to a source of the transistor.

In addition, a first dielectric layer 309 is formed on the interlayer dielectric layer 302, and an etching stop layer may be formed between the interlayer dielectric layer 302 and the first dielectric layer 309 to serve as an end point of etching.

The first dielectric layer 309 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). The first dielectric layer 309 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron. The thickness thereof is not limited to a certain value. The first dielectric layer 309 may also be a plasma enhanced chemical vapor deposition oxide or a low K dielectric layer material (such as black brick).

The sidewalls of the first contact structure may be vertical or inclined, and are not limited to a certain kind.

In the present invention, the first contact structure has an inverted trapezoidal shape.

Similarly, a second contact structure 304 is also formed in the interlayer dielectric layer 302 and the first dielectric layer 309, and the second contact structure 304 is electrically connected to the second bit line 307.

Alternatively, the sidewalls of the second contact structure 304 may be vertical or inclined, and are not limited to a certain kind.

In the present invention, the second contact structure has an inverted trapezoidal shape.

The first bit line 305 may be made of a conductive material, for example, a metal material or a doped semiconductor material layer, in the present invention, the bottom electrode material layer is preferably made of a metal material, for example, the metal material includes one or more of Pt, Au, Cu, Ti, and W, in the present invention, the metal material is Cu, and the process of forming the through silicon via using metal copper is compatible with the existing process, so as to simplify the process.

Forming a second dielectric layer 310 on the first dielectric layer to cover the first dielectric layer; the second bit line is formed in the second dielectric layer.

The second dielectric layer 310 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). The second dielectric layer 310 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron. The thickness thereof is not limited to a certain value. The second dielectric layer 310 may also be a plasma enhanced chemical vapor deposition oxide or a low K dielectric layer material (such as black brick).

An etch stop layer may also be formed between the second dielectric layer 310 and the first dielectric layer 309.

In the present invention, the bottom electrode material layer is preferably made of a metal material, for example, the metal material includes one or more of Pt, Au, Cu, Ti, and W, and in the present invention, the bottom electrode material layer is made of metal Cu, and the process of forming the through-silicon via using metal Cu is compatible with the existing process, thereby simplifying the process.

The substrate includes a central region and a peripheral region, the peripheral region is disposed around the central region, the bit lines in the peripheral region are disposed in the same manner as the bit lines in the central region, as shown in fig. 3C, and the peripheral region further includes a gate via and a metal layer 306 connected to the gate.

The present invention provides a semiconductor device in which the bit lines are arranged in two layers staggered up and down, that is, the bit lines include first bit lines and second bit lines staggered up and down, and the first bit lines and the second bit lines are alternately arranged in a direction perpendicular to the first direction. Through the arrangement, the breakdown problem caused by reduction of the dielectric distance between the bit lines due to size reduction can be avoided, the distance between the adjacent bit lines on the same layer can be increased through the up-down staggered arrangement, and the problem that the distance is too small due to the fact that the adjacent bit lines are located on different layers can be avoided, so that the performance and the yield of the device can be further improved.

Example two

Hereinafter, detailed steps of an exemplary method of a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIGS. 4A to 4F are cross-sectional views of a process for manufacturing a bit line in a semiconductor device according to the present invention, taken along a word line direction; fig. 5 is a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 5 is a schematic flow chart of a method of manufacturing a semiconductor device of another embodiment of the present invention, specifically including:

step S1: forming a bit line in a first direction, the bit line being electrically connected with a device therebelow; the bit lines comprise first bit lines and second bit lines which are arranged in an up-and-down staggered mode, and the first bit lines and the second bit lines are arranged in a second direction perpendicular to the first direction in an alternating mode.

The method for manufacturing the semiconductor device of the embodiment specifically includes the following steps:

first, as shown in fig. 4A, a substrate 301 is provided, an interlayer dielectric layer 302 is formed on the substrate 301, an interconnection structure is formed in the interlayer dielectric layer 302, a device electrically connected to the interconnection structure is formed in the substrate, and a bit line is formed in a first direction, and the bit line is electrically connected to the device below through the interconnection structure.

Specifically, as shown in fig. 4A, the substrate 301 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.

An interlayer dielectric layer 302 is formed on the substrate, wherein the interlayer dielectric layer 302 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer 302 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron. The thickness thereof is not limited to a certain value. The interlayer dielectric layer 302 may also be a plasma enhanced chemical vapor deposition oxide or a low K dielectric layer material (such as black brick).

The method for forming the bit line is further described below with reference to the drawings.

First, step one is performed to form a first dielectric layer 309 on the interlayer dielectric layer 302, and an etch stop layer (not shown) may be further formed between the interlayer dielectric layer 302 and the first dielectric layer 309 for serving as an etching end point, which is not described herein again.

A mask stack is then formed on the first dielectric layer 309, as shown in fig. 4A, wherein the mask stack may include, but is not limited to, an organic insulating layer (ODL), a Bottom Anti-Reflective Coating (BARC), a photoresist layer, or the like, which is not described herein again.

And step two, patterning the first dielectric layer to form a first opening exposing the first contact structure.

Specifically, as shown in fig. 4B, a first opening is formed to expose the first contact structure, wherein a conventional patterning method may be used as the method for forming the first opening, for example, forming a mask stack and performing dry etching or wet etching to form the first opening.

The first opening is formed by a self-aligned double-pattern method, which comprises the following steps:

step A1: forming a mask lamination on the first dielectric layer, forming a photoresist layer on the mask lamination, and carrying out exposure and development to form a cylindrical pattern;

step A2: etching the mask lamination by taking the cylindrical pattern as a mask so as to form a cylindrical structure of the mask lamination;

step A3: conformally depositing a spacer material layer to cover the columnar structure;

step A4: etching the spacer material layer to form a spacer on the sidewall of the pillar structure;

step A5: removing the columnar structure and only reserving the gap wall;

step A6: and etching the first dielectric layer by using the gap wall as a mask so as to form the first opening.

The photoresist layer may be a positive photoresist or a negative photoresist, and is not limited to any one.

The above-mentioned method of self-aligning the double patterns is only an exemplary one, and the present invention may also select other double pattern methods, and is not limited to this example.

Wherein, in the step A6, in order to obtain a first opening with a larger aspect ratio to reduce the size of the opening, a Deep Reactive Ion Etching (DRIE) method may be selected to form the first opening, for example, a silicon hexafluoride (SF) gas is selected in the Deep Reactive Ion Etching (DRIE) step₆) And applying a radio frequency power supply as a process gas to ensure that the reaction gas of the silicon hexafluoride forms high ionization, wherein the working pressure is controlled to be 20mTorr-8Torr, the power is 600W, the frequency is 13.5MHz, the direct current bias can be continuously controlled within-500V-1000V in the etching step, the requirement of anisotropic etching is ensured, and the selection of Deep Reactive Ion Etching (DRIE) can keep a very high etching photoresist selectivity. The Deep Reactive Ion Etching (DRIE) system may be selected from apparatuses commonly used in the art, and is not limited to a certain model.

Wherein, the side wall of the first opening may be vertical or inclined, but not limited to a certain one.

In the present invention, the first opening has an inverted trapezoidal shape.

Step three is performed to deposit a bit line material layer in the first opening to form the first bit line 305.

Specifically, as shown in fig. 4C, in this step, the bit line material layer may be selected from one of Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG) formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD), or the like. An Atomic Layer Deposition (ALD) method is preferred in the present invention.

Step four is performed to pattern the interlayer dielectric layer 302 and the first dielectric layer 309 to form a contact opening between the first bit lines to expose the device.

Specifically, as shown in fig. 4D, a self-aligned dual-pattern method may also be used to form the contact opening in this step, and reference may be made to step two or other dual-pattern methods in the art in this step, which is not described herein again.

Wherein, the etching method can also be Deep Reactive Ion Etching (DRIE), which is not described herein.

Performing step five, as shown in fig. 4E, forming a second dielectric layer 310 on the first dielectric layer to cover the first dielectric layer; and patterning the second dielectric layer to form a second opening and expose the contact opening.

Specifically, as shown in fig. 4E, the second dielectric layer 310 in this step may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). The second dielectric layer 310 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron. The thickness thereof is not limited to a certain value. The second dielectric layer 310 may also be a plasma enhanced chemical vapor deposition oxide or a low K dielectric layer material (such as black brick).

An etch stop layer may also be formed between the second dielectric layer 310 and the first dielectric layer.

The method for forming the second opening may use a self-aligned double-pattern method to form the contact opening, and the specific step may refer to step two, or other double-pattern methods in the art, which are not described herein again.

Optionally, the second opening is in the shape of an inverted trapezoid.

And executing a sixth step of depositing a bit line material layer and filling the second opening and the contact opening to form a second contact structure and the second bit line.

Specifically, as shown in fig. 4F, a bit line material layer is deposited to simultaneously fill the second opening and the contact opening, and simultaneously form a second contact structure 304 and the second bit line 307.

In this step, the second contact structure 304 and the second bit line 307 may be formed at the same time, or the contact opening may be filled first, the second contact structure 304 is formed, the second opening is filled again, and then the second bit line 307 is formed, which is not further limited herein.

In this step, the bit line material layer may be formed by one of Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) using Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD). An Atomic Layer Deposition (ALD) method is preferred in the present invention.

Thus, the introduction of the embodiment of the present invention to manufacture the semiconductor device is completed. After the above steps, other related steps may also be included, which are not described herein again. Besides the above steps, the manufacturing method of this embodiment may further include other steps in the above steps or between different steps, and these steps may be implemented by various processes in the current process, and are not described herein again.

EXAMPLE III

The invention also provides an electronic device comprising the semiconductor device of the first embodiment. The semiconductor device is the semiconductor device described in the first embodiment, or the semiconductor device obtained by the manufacturing method described in the second embodiment.

The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the semiconductor device.

Wherein figure 6 shows an example of a mobile telephone handset. The mobile phone handset 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.

Wherein the mobile phone handset comprises the semiconductor device of embodiment one, the semiconductor device comprising: a bit line disposed along a first direction, the bit line electrically connected to a device therebelow; the bit lines comprise first bit lines and second bit lines which are arranged in an up-and-down staggered mode, and the first bit lines and the second bit lines are arranged in a second direction perpendicular to the first direction in an alternating mode. The bit lines are arranged in two layers staggered up and down in the semiconductor device, that is, the bit lines include first bit lines and second bit lines staggered up and down, and the first bit lines and the second bit lines are alternately arranged in a direction perpendicular to the first direction. Through the arrangement, the breakdown problem caused by reduction of the dielectric distance between the bit lines due to size reduction can be avoided, the distance between the adjacent bit lines on the same layer can be increased through the up-down staggered arrangement, and the problem that the distance is too small due to the fact that the adjacent bit lines are located on different layers can be avoided, so that the performance and the yield of the device can be further improved.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

the bit lines comprise first bit lines and second bit lines which are arranged in an up-down staggered mode, and the first bit lines and the second bit lines are arranged in a second direction perpendicular to the first direction in an alternating mode;

forming a contact structure between the bit line and the device, wherein two ends of the contact structure are respectively electrically connected with the bit line and the device, and the contact structure is in an inverted trapezoidal shape;

wherein the method of forming the first bit line comprises: providing a substrate containing the device and an interlayer dielectric layer positioned on the substrate, wherein a first contact structure is formed in the interlayer dielectric layer; forming a first dielectric layer over the first contact structure; patterning the first dielectric layer to form a first opening exposing the first contact structure; depositing a bit line material layer in the first opening to form the first bit line;

the method of forming the second bit line comprises: patterning the first dielectric layer and the interlevel dielectric layer to form contact openings between the first bit lines in a second direction, exposing the devices; forming a second dielectric layer on the first dielectric layer covering the first dielectric layer; patterning the second dielectric layer to form a second opening and expose the contact opening; depositing a bit line material layer to fill the second opening and the contact opening to form a second contact structure and the second bit line;

forming the first opening, the contact opening, and/or the second opening using a self-aligned double pattern method, the self-aligned double pattern method comprising:

conformally depositing a spacer material layer to cover the columnar structure;

removing the columnar structure and reserving the gap wall;

2. The method of claim 1, further comprising the step of forming a word line before or after forming the bit line, the word line being disposed along the second direction.

3. The method of claim 2, wherein the device comprises a transistor, wherein the bit line is electrically connected to a source of the transistor, and wherein the word line is electrically connected to a gate of the transistor.

4. A semiconductor device prepared by the method of any one of claims 1 to 3, comprising:

and the contact structure is positioned between the bit line and the device, two ends of the contact structure are respectively electrically connected with the bit line and the device, and the contact structure is in an inverted trapezoidal shape.

5. The semiconductor device according to claim 4, wherein the contact structure includes a first contact structure and a second contact structure which are different in height, the first contact structure is electrically connected to the first bit line, and the second contact structure is electrically connected to the second bit line.

6. The semiconductor device according to claim 4, further comprising:

word lines arranged along the second direction.

7. The semiconductor device of claim 6, wherein the device comprises a transistor, wherein the bit line is electrically connected to a source of the transistor, and wherein the word line is electrically connected to a gate of the transistor.

8. The semiconductor device according to claim 4, wherein the semiconductor device comprises a memory cell region and a peripheral region outside the memory cell, wherein the bit line is formed in each of the memory cell region and the peripheral region.

9. An electronic device, characterized in that the electronic device comprises the semiconductor device according to any one of claims 4 to 8.