CN113540347B - Capacitor, semiconductor device, electronic apparatus, and method of manufacturing the same - Google Patents
Capacitor, semiconductor device, electronic apparatus, and method of manufacturing the same Download PDFInfo
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- CN113540347B CN113540347B CN202010291407.XA CN202010291407A CN113540347B CN 113540347 B CN113540347 B CN 113540347B CN 202010291407 A CN202010291407 A CN 202010291407A CN 113540347 B CN113540347 B CN 113540347B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 62
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 43
- 230000004888 barrier function Effects 0.000 claims description 40
- 230000008569 process Effects 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 193
- 239000011229 interlayer Substances 0.000 description 10
- 238000003860 storage Methods 0.000 description 10
- 239000004020 conductor Substances 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 8
- 230000015654 memory Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910001922 gold oxide Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- -1 siOH Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present application relates to a cylindrical capacitor structure and a semiconductor device, including: a semiconductor substrate; a plurality of capacitors on the semiconductor substrate, the capacitors including a lower electrode, a dielectric layer, and an upper electrode; a support located above the top of the lower electrode. The capacitor and the semiconductor device obtained by the manufacturing method can effectively solve the problems of inclination and collapse of the lower electrode in the manufacturing method while ensuring the depth-to-width ratio.
Description
Technical Field
The present application relates to a capacitor and a method of manufacturing the same, and also relates to a semiconductor device including the capacitor, an electronic apparatus, and a method of manufacturing the same.
Background
In recent years, semiconductor manufacturers are increasingly researching semiconductor devices with high integration and high speed, as semiconductor users require the semiconductor devices to have low power consumption, high memory capacity and high speed characteristics. In particular, a dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used as a semiconductor memory cell because of its free data input and output capability and large memory capacity.
In order to rapidly improve the integration and scalability of the memory, the integration density of semiconductor devices is continuously increased, and the design size standard of semiconductor devices is continuously reduced. For example, typically, a DRAM is a collection of cells, with one MOS (Metal Oxide Semiconductor) transistor and one storage capacitor per cell. As the integration level increases, the size of the semiconductor chip decreases, and the size of the capacitor also necessarily decreases, and the decrease in the size of the capacitor gradually decreases the pitch between the electrodes to thereby decrease the capacitance of the capacitor accordingly, thereby decreasing the charge storage capacity of the capacitor. However, even in view of the increased integration of semiconductor memories, it is necessary to make the capacitor have a sufficient capacitance to ensure smooth operation and performance of the semiconductor memory device.
The capacitance of the capacitor depends on the thickness of the dielectric layer, the dielectric constant, and the contact area between the upper Electrode (TE) and the lower Electrode (BE). Accordingly, in order to solve the contradiction between the above-mentioned downsizing of design and improvement of storage capacitance, including increasing the surface area of the storage electrode (capacitor lower electrode), decreasing the thickness of the dielectric layer, and using a dielectric layer having a High dielectric constant (High-k), are all methods of increasing the capacitance of the capacitor.
Among these methods, enlarging the surface area of the storage electrode (including maximizing the height of the cylindrical capacitor) is most commonly used. Specifically, a capacitor having a single cylindrical memory (OCS, one Cylinder Storage) structure in which the total effective area of the capacitor can be increased by increasing the vertical area while reducing the horizontal area occupied by the capacitor in the semiconductor memory cell, thereby increasing the storage capacitance.
As shown in fig. 1a to 1e, the following method is commonly used in the prior art to manufacture cylindrical capacitors:
first, referring to fig. 1a, an interlayer insulating layer 102 may be formed on an upper surface of a semiconductor substrate (not shown), then a memory node pad 104 is formed on the interlayer insulating layer, then an etch stop layer 106 is formed on surfaces of the interlayer insulating layer 102 and the memory node pad 104, and then a mold oxide layer 106 is formed on the surface of the etch stop layer 106;
next, referring to fig. 1b, a photoresist pattern is formed on the upper surface of the mold oxide layer 108 using a conventional photolithography process and using a hard mask layer (not shown), thereby forming a trench 110 exposing a predetermined region of the lower electrode corresponding to the memory node pad 104, and then the hard mask layer is removed;
next, referring to fig. 1c, a conductive material is deposited on the surfaces of the patterned die oxide layer 108 and the trench 110 to form a lower electrode layer 112;
next, referring to fig. 1d, blanket filling with sacrificial oxide 114 is performed and then a planarization process is performed to expose the top surfaces of the die oxide layer 108 and the lower electrode layer 112;
next, referring to fig. 1e, the lower electrode 112 is obtained by etching away the mold oxide layer 108 and the sacrificial oxide 114;
next, a dielectric layer and an upper electrode are deposited on the lower electrode surface to finally form a cylindrical capacitor (not shown).
However, the storage node electrode using the capacitor having the OCS structure described above has a relatively high Aspect Ratio (Aspect Ratio), i.e., its vertical height is much larger than its width. Such high aspect ratio storage node electrodes are prone to tilting (landing) or collapsing (Collapse). In particular, tilting or collapsing of the lower electrode is more easily caused due to surface tension in the removal process of a Mold oxide layer (gold oxide) formed between storage electrode nodes. In order to solve the above-mentioned problem of tilting or collapsing of the electrode, in the process step of manufacturing the lower electrode, a process step of forming a supporting layer is added, and even a plurality of supporting layers are required to be added to prevent tilting or collapsing of the lower electrode due to the increasing aspect ratio, as shown in fig. 1f, a first mold oxide layer 108a is formed on the surface of the etch stop layer 106, then a first supporting layer 109a is formed, then a second mold oxide layer 108b is formed, and a second supporting layer 109b is formed, and then a hard mask layer 111 is formed on the surface of the second supporting layer, so that the lower electrode 112 with the first supporting layer 109a and the second supporting layer 109b can be finally obtained (as shown in fig. 1 h) after the subsequent steps and the opening treatment of the supporting layer as described above, the removal of the mold oxide layer and the sacrificial layer (as shown in fig. 1 g).
Although the use of the support layer is effective to avoid tilting or collapsing of the lower electrode due to the high aspect ratio, the deposition step of the support layer and the subsequent opening step of the support layer require more materials, and the completion time of the entire manufacturing process is increased due to the addition of more process steps, thereby reducing productivity and increasing costs.
Disclosure of Invention
The purpose of the application is realized through the following technical scheme:
in accordance with one or more embodiments, the present application discloses a cylindrical capacitor structure comprising:
a semiconductor substrate;
a plurality of first capacitors on the semiconductor substrate, the first capacitors including a lower electrode, a first dielectric layer, and a first upper electrode;
and the support is used for supporting the lower electrode and is positioned on the inner wall and the outer wall of the first dielectric layer.
In accordance with one or more embodiments, the present application also discloses a method of manufacturing a capacitor structure, comprising the following process steps:
providing a semiconductor substrate, wherein a sacrificial mould layer is arranged on the semiconductor substrate;
forming a support layer on the sacrificial mold layer;
etching the supporting layer and the sacrificial mold layer to form a first groove, wherein the first groove corresponds to the position where the lower electrode is formed;
forming a lower electrode layer, a first dielectric layer and a first upper electrode layer in the first groove in sequence, wherein the first upper electrode comprises a first barrier layer and a first electrode layer;
forming a support disc above the first lower electrode, the support disc extending downward from an inner ring and an outer ring, the inner ring being located on top of the first dielectric layer, the outer ring being located on top of the remaining support layer;
removing the remaining sacrificial mold layer to form a second recess;
a second dielectric layer and a second upper electrode are formed in the second recess, the second upper electrode including a second barrier layer and a second electrode layer.
According to one or more embodiments, the application also discloses a semiconductor device, an electronic device and the like comprising the capacitor structure or the capacitor structure prepared by the manufacturing method.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
fig. 1a to 1h are schematic views of a conventional cylindrical capacitor manufacturing process.
Fig. 2a-2p are schematic views of a process for manufacturing a cylindrical capacitor according to embodiments of the present application.
Detailed Description
The present application will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. However, the present application is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit of the present application.
Moreover, relative terms, such as "lower" or "bottom" and "upper" or "top," are used herein to describe one element's relationship to another element as illustrated in the figures. It should be understood that relative terms include different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being below another element would then be oriented on top of the other element. The exemplary term "lower" therefore includes both "lower" and "upper" directions, depending on the particular orientation of the figure. Likewise, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented above the other elements. Thus, the exemplary terms "below" or "under" encompass both an orientation of above and below.
Embodiments of the present application are described herein with reference to cross-sectional views (and/or plan views) that schematically illustrate idealized embodiments of the present application. Likewise, deviations from the schematic shape due to, for example, manufacturing processes and/or tolerances, may be expected. Thus, embodiments of the present application are not to be considered as limiting the specific shape of the regions described herein, but rather as including deviations in shape that result, for example, from manufacturing. For example, etched regions illustrated or described as rectangular typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present application.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Those skilled in the art will appreciate that a reference to a structural or functional component configured adjacent to another component may have portions that overlap or underlie the other component.
The application discloses a capacitor structure and a method of manufacturing the same. The shape of the capacitor may be, for example, cylindrical, spherical, rectangular, and any suitable shape that may be obtained by techniques in the art. The following examples take a capacitor having a cylindrical structure as an example, but the present application is not limited thereto. In one embodiment of the present application, a supporting layer is provided, and a specific capacitor structure and a specific process are as follows:
as shown in fig. 2o and 2p, a semiconductor device including a capacitor structure is illustrated in an embodiment of the present application, and may be used in, for example, some electronic device, such as a smart phone, a computer, a tablet computer, a wearable smart device, an artificial smart device, a mobile power supply, and the like. The semiconductor device includes a semiconductor substrate, for example, a semiconductor substrate of a circuit element of a MOS (Metal Oxide Semiconductor) transistor, on which functional parts (not shown) such as a gate electrode, a source/drain electrode, a bit line, and the like are formed. An interlayer insulating layer 201 (Interlayer Insulation) is formed on the semiconductor substrate; landing pads 202 (Landing pads) are formed on the interlayer insulating layer 201. A lower electrode 208 is formed on the landing pad 202, and the lower electrode in this embodiment has a cylindrical side wall and a bottom wall, and an upper opening is formed in the lower electrode 208, and the side wall and the bottom wall form the inside of the lower electrode. A first dielectric layer 209 and a first upper electrode are sequentially formed on the inner side of the sidewall of the lower electrode, wherein the first upper electrode has a first barrier layer 210 (in other embodiments, the first barrier layer may not be provided as needed) and a first upper electrode layer 211, the first barrier layer 210 has substantially the same height as the lower electrode 208, the first dielectric layer 209 is higher than the heights of the lower electrode 208 and the first barrier layer 210 (the heights of the three are based on the top heights thereof), the first upper electrode layer 211 fills the inner space of the lower electrode, and the lower electrode 208, the first dielectric layer 209 and the first upper electrode form a first capacitor. A second dielectric layer 213 and a second upper electrode are sequentially formed on the outer side of the lower electrode sidewall, the second upper electrode includes a second barrier layer 214 (in other embodiments, the second barrier layer may not be provided as needed) and a second upper electrode layer 215, the second upper electrode layer 215 fills the space on the outer side of the lower electrode, and the lower electrode 208 and the second upper electrode form a second capacitor. A disk-shaped support 205 'is formed on the upper portion of the inner and outer walls of the first dielectric layer 209 while the support 205' protrudes downward from both sides of the first dielectric layer 209, covers the top of the lower electrode 208 and the first barrier layer 210, and extends in the horizontal direction from the top of the sidewall of the lower electrode covered thereby to both the inside and outside of the lower electrode. Meanwhile, since the disk-shaped support 205' extends to the outside of the lower electrode so that the second upper electrode has a structure with a small upper side and a large lower side, and the turning surface with a small upper side and a large lower side is located within the height range of the support 205', the support 205' just covers the turning surface. The uppermost is an upper electrode plate 216 that communicates the first upper electrode inside the lower electrode 208 and the second upper electrode outside the lower electrode 208 to collectively form an upper electrode opposite to the lower electrode, thereby completing the construction of the inside first capacitor and the outside second capacitor. Furthermore, in this embodiment, as can also be seen in fig. 2o and 2p, unlike the prior art, the dielectric layers include a first dielectric layer 209 located inside the sidewall of the lower electrode 208 and a second dielectric layer 213 located outside the sidewall of the lower electrode 208, both of which are not connected (or referred to as discontinuous); also, in this embodiment, as can also be seen in fig. 2o and 2p, unlike the prior art, the barrier layer also includes a first barrier layer 210 located inside the sidewall of the lower electrode 208 and a second barrier layer 214 located outside the sidewall of the lower electrode 208, which are also not in communication (or referred to as discontinuous).
Next, referring to fig. 2a-2p, a process for manufacturing the semiconductor device and materials used according to an embodiment of the present application will be described in further detail:
in the process of the present application, a semiconductor substrate having a circuit element such as a BCAT (Buried Channel Array Transistor) transistor formed thereon may be provided, and functional components (not shown) such as a gate electrode, a source/drain electrode, and a bit line may be formed on the semiconductor substrate.
As shown in fig. 2a, an interlayer insulating layer 201 (Interlayer Insulation) may be formed on the semiconductor substrate; a Landing Pad 202 (Landing Pad) is formed on the interlayer insulating layer 201, and the Landing Pad 202 may be made of a material such as W or Co.
Subsequently, an etch stop layer 203 (Stopper) may be formed on the surfaces of the interlayer insulating layer 201 and the landing pad 202, the etch stop layer 203 being composed of a nitride material, such as silicon nitride.
A sacrificial Mold layer 204 (gold) may be formed on the surface of the etch stop layer 203, where the sacrificial Mold layer 204 is commonly an Oxide, i.e., a sacrificial Mold layer of Oxide (gold Oxide), and the material may include any one or more of doped oxides, such as SiO2, siOH, PSG (Phosphosilicate glass ), BPSG (Borophosphosilicate glass, borophosphosilicate glass), siCOH, TEOS (tetraethyl orthosilicate); the sacrificial mold layer may also be a layered structure of a plurality of layers, such as a layered structure of TEOS. The sacrificial mold layer may be formed by a suitable process such as Chemical Vapor Deposition (CVD), low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).
Subsequently, a support material, which is a nitride, may be deposited on the surface of the oxide sacrificial mold layer 204 to form a support layer 205 (support), and specifically any one or a combination of two or more of SiN, siCN, BNx, which has a high etching selectivity with the materials of the lower electrode, the upper electrode, and the dielectric layer in the capacitor, thereby facilitating the subsequent selective etching.
Subsequently, a Hard Mask layer 206 (HM, hard Mask) may be formed on the surface of the support layer 205, and may include a common Hard Mask material such as polysilicon (Poly-Si), doped silicon (Dope-Si), amorphous Carbon (ACL), spin-on Silicon (SOH) layer, etc., formed using a CVD process.
The hard mask layer 206 may then be subjected to a photolithographic process using conventional photolithographic means to yield a patterned hard mask layer.
As shown in fig. 2b, the oxide sacrificial mold layer 204 may then be etched according to the patterned hard mask layer 206 until the etch stop layer 203 is etched away to expose the landing pad 202, forming a first recess 207, which may be etched using a conventional dry etching process, for example, using CH 2 F 2 /O 2 /Ar/CHF 3 A dry etching process of fluorine-containing gas; conventional wet etching processes, including, for example, HF and NH, may also be employed 4 F, e.g. a mixture of HF and NH in a ratio of about 1:6 to 1:10 4 LAL solution of F.
Subsequently, the hard mask layer 206 may be removed, for example, using conventional ashing processes or the like.
As shown in fig. 2c, a first conductive material may then be deposited on the inner walls of the first recess 207 and the surface of the support layer 205 to form a Bottom Electrode layer 208; since the current technology generally employs a dielectric material with a high dielectric constant, e.g., ta 2 O 5 、Al 2 O 3 And/or HfO 2 And the like are used as dielectric layers of capacitors, and the quality of the interface between the dielectric material and the polysilicon electrode may be degraded. In particular, the interface quality between the dielectric material and the polysilicon electrode may decrease with an increase in dielectric constant, and therefore, a metal with a high work function (work function), such as TiN, is preferably used x 、TaN x 、WN x Any one or more than two refractory metal materials are used as the lower electrode to replace the traditional polysilicon electrode. The deposition process may be a common CVD, PECVD, ALD (atomic layer vapor deposition) process.
As shown in fig. 2d, a High-k dielectric material (High-k Dielectrics) may then be deposited on the surface of the lower electrode layer 208 to form a first dielectric layer 209 that serves to separate the lower electrode layer from a subsequently deposited first upper electrode to form a capacitor; the high dielectric material can be AlO x 、HfO x 、ZrO x 、TaO x And the like, or a combination of any one or two or more thereof.
As shown in fig. 2e, a Barrier material, which is TiN, may then be deposited on the surface of the first dielectric layer 209 to form a first Barrier layer 210 (Barrier Metal) of the first upper electrode x 、TaN x 、WN x Any one or a combination of two or more refractory metal materials. The barrier layer is mainly used to prevent material diffusion between layers, however, the process of forming the barrier layer is not necessary, and this step may be omitted if necessary, and it is understood that the structure formed later may not have the first barrier layer.
As shown in fig. 2f, a second conductive material may then be deposited to cover the first barrier layer 210 and fill the first recess 207 to form a first upper Electrode layer 211 (Top Electrode) of the first upper Electrode; the second conductive material is metal W or doped silicon. The first upper electrode layer 211 and the first barrier layer 210 together form a first upper electrode.
As shown in fig. 2g, the surface of the first upper electrode may then be planarized until the top of the support layer 205 is exposed; the planarization process employs a chemical mechanical planarization (Chemical Mechanical Planarization, CMP) process.
As shown in fig. 2h, the bottom electrode layer 208 and the first barrier layer 210 on both sides of the first dielectric layer 209 may be selectively etched back to form a etched back groove; portions of the lower electrode layer 208 and the first barrier layer 210 may be etched back together using a relatively simple and easy wet etch process.
As shown in fig. 2i, the support material may then be redeposited over the entire semiconductor substrate to backfill the etched trenches until the surface of the support layer 205' is substantially filled, the same support material may be used for both support layers, and the deposition process may be performed using ALD. In the capacitor structure of the present application, as shown in fig. 2p, since the first dielectric layer 209 is not etched back, the top height is higher than the bottom electrode layer 208 and the first barrier layer 210, which are selectively etched back at both sides, and thus the support 205' is located at both sides of the inner wall and the outer wall of the first dielectric layer 209; meanwhile, the support 205' is located above the top of the lower electrode 208 and extends from the top of the sidewall of the lower electrode 208 to the inside and outside of the lower electrode 208 in the horizontal direction, whereas the height of the support in the prior art is lower than the top of the lower electrode and is located outside the sidewall of the lower electrode.
As shown in fig. 2j, the surface of the filled support layer 205' may then be apertured to expose the remaining oxide sacrificial mold layer 204; the cell Pattern of the openings has any one or a combination of two or more of Linear Type Slit (Linear Type Slit) or Mesh Pattern (Mesh Pattern). The perforated support layer 205' is the structure of the support plate. Specifically, in order to form the openings and the support disk structure, a mask having a support disk shape may be first formed on the surface of the support layer 205', then the support layer 205' may be etched according to the mask to form the openings and the support disk structure remains, and then the mask layer may be removed using an ashing process or the like. After the support disk is formed over the first dielectric layer 209, it can be seen that the support disk extends down to an inner ring that is above the top of the first barrier layer 210 remaining after the etch back and an outer ring that is above the top of the lower electrode layer 208 remaining after the etch back.
As shown in fig. 2k, the remaining oxide sacrificial mold layer 204 may then be removed by opening holes, etching to form second recesses 212; the wet etching process is adopted, but the lower electrode layer 208 is not isolated, but is supported by the first dielectric layer 209, the first barrier layer 210 and the first upper electrode layer 211 which are formed inside the lower electrode 208, so that the surface tension of the lower electrode layer is reduced to at least 1/2 of that of the original manufacturing method, and the problems of inclination and collapse caused by the surface tension caused by the wet etching process are effectively avoided. Also because of the above advantages, compared with the prior art that even more than two support layers must be used, the use of the support layers in the embodiments of the present application can be reduced, for example, only one support layer can be provided, and also unnecessary deposition, cleaning and other related process steps are naturally reduced, so that the working procedures are saved, and the cost is saved.
As shown in fig. 2l, a high dielectric material may then be deposited on the inner walls of the second recess 212 and the surface of the support layer 205' to form a second dielectric layer 213; the high dielectric material can be AlO x 、HfO x 、ZrO x 、TaO x Any one or a combination of two or more of the following; the deposition process is, for example, an ALD process.
As shown in fig. 2m, a barrier material may then be deposited on the surface of the second dielectric layer 213 to form a second barrier layer 214; the barrier material is TiN x 、TaN x 、WN x Any one or the combination of more than two refractory metal materials; the deposition process is an ALD process. The barrier layer is mainly used to prevent diffusion of materials between layers, however, the process of forming the barrier layer is not required, and can be omitted if necessary, and it is understood that the structure formed later will not have the second barrierAnd a blocking layer.
Subsequently, a second conductive material may be deposited to cover the second barrier layer 214 and fill the second recess 212 to form a second upper electrode layer 215; the second conductive material is metal W or doped silicon. The deposition process may be CVD, PECVD, or the like. The second upper electrode layer 215 and the second barrier layer 214 form a second upper electrode. Because of the special structure of the supporting disc formed in the process of opening the holes, the formed second upper electrode can be in a structure with a small upper part and a large lower part, the turning surface with the small upper part and the large lower part is positioned in the height range of the supporting layer, and the supporting layer can cover the turning surface.
As shown in fig. 2n, the surface of the second upper electrode layer 215 may then be planarized until the top surface of the support layer is exposed; the planarization process employs a chemical mechanical planarization (Chemical Mechanical Planarization, CMP) process.
As shown in fig. 2o, the support layer 205 'may then be etched back to expose the first upper electrode layer 211, and the remaining support layer becomes a support 205' in the capacitor structure, which may serve as a support for the high aspect ratio lower electrode. The back etching support layer is plasma etching performed under the condition of Low Bias Power or No Bias Power by adopting fluorine-based gas or mixed gas containing fluorine-based gas; wherein the fluorine-based gas is selected from CHF 3 、CH 2 F 2 、CHF 3 、CH x F y 、NF 3 、SF 6 Any one or a mixture of two or more of them. By adopting the etching gas, high selectivity can be generated for the material of the supporting layer, the lower electrode, the dielectric layer and the top electric layer, so that the supporting layer can be etched back effectively and the lower electrode, the dielectric layer and the top electric layer can be reserved.
As shown in fig. 2p, subsequently, a second conductive material may be redeposited to form an upper electrode Plate 216 (TE Plate) to conduct the exposed first upper electrode layer 211 and second upper electrode layer 215; the second conductive material is metal W or doped silicon.
In addition to the above embodiments, two or more support layers may be provided to obtain a larger aspect ratio than the conventional cylindrical capacitor, so as to meet the requirements of higher integration and continuously reduced design size. This is achieved by only depositing two sacrificial oxide films and two support layers, respectively, with the aid of the method of manufacturing in this application of depositing the first and second dielectric layers, the barrier layer and the upper electrode, respectively.
The cylindrical capacitor and the semiconductor device obtained by the manufacturing method can effectively solve the problems of inclination and collapse of the lower electrode in the manufacturing method while ensuring the depth-to-width ratio.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (14)
1. A cylindrical capacitor structure comprising:
a semiconductor substrate;
a plurality of first capacitors on the semiconductor substrate, the first capacitors including a lower electrode, a first dielectric layer, and a first upper electrode;
a support for supporting the lower electrode, directly located on the inner and outer walls of the first dielectric layer;
the second dielectric layer and the second upper electrode are positioned on the outer side of the side wall of the lower electrode, and the lower electrode, the second dielectric layer and the second upper electrode form a second capacitor; the second upper electrode is provided with a mechanism with a small upper part and a large lower part, and the turning surface with the small upper part and the large lower part is positioned in the height range of the support; the support covers the turning surface.
2. The capacitor structure of claim 1, characterized in that:
the top of the first dielectric layer is higher than the top of the lower electrode.
3. The capacitor structure of claim 1, characterized in that:
the first upper electrode comprises a first barrier layer and a first electrode layer; wherein the top of the first dielectric layer is higher than the top of the first barrier layer.
4. The capacitor structure of claim 1, characterized in that:
the first upper electrode is in communication with the second upper electrode.
5. A capacitor structure as claimed in any one of claims 1 to 4, wherein:
the support extends in a horizontal direction from the top of the sidewall of the lower electrode toward both the inside and outside of the lower electrode.
6. A capacitor structure as claimed in claim 3, wherein:
the support overlies the lower electrode and the first barrier layer.
7. The capacitor structure of claim 1, characterized in that:
the support comprises a nitride material.
8. The capacitor structure of claim 7, characterized in that: the nitride material comprises SiN, siCN,BN x Any one or a combination of two or more of them.
9. A method of manufacturing a capacitor structure comprising the process steps of:
providing a semiconductor substrate, wherein a sacrificial mould layer is arranged on the semiconductor substrate;
forming a support layer on the sacrificial mold layer;
etching the supporting layer and the sacrificial mold layer to form a first groove;
sequentially forming a lower electrode layer, a first dielectric layer and a first upper electrode layer in the first groove, wherein the first upper electrode layer comprises a first barrier layer and a first electrode layer;
forming a support disk above the first dielectric layer, the support disk extending downward beyond an inner ring and an outer ring, the inner ring being located on top of the first barrier layer, the outer ring being located on top of the lower electrode layer;
removing the remaining sacrificial mold layer to form a second recess;
a second dielectric layer and a second upper electrode are formed in the second recess, the second upper electrode including a second barrier layer and a second electrode layer.
10. The manufacturing method according to claim 9, characterized in that: the step of forming a support disk over the first dielectric layer includes:
flattening until the top of the supporting layer is exposed;
selectively etching to remove the tops of the lower electrode layers and the first barrier layers which are positioned on two sides of the first dielectric layer;
filling a supporting material layer on the whole semiconductor substrate;
etching the support material layer to form the support plate.
11. The manufacturing method according to claim 10, characterized in that: the step of etching the support material layer to form the support plate includes:
forming a mask in the shape of a support disk on the support material layer;
etching the support material layer;
the mask is removed.
12. The manufacturing method according to claim 9, characterized in that: after forming the second upper electrode, the method further comprises:
performing a CMP process on the second electrode layer until the support plate is exposed;
etching the support disc back until the top of the support disc is removed;
filling the second electrode layer material.
13. A semiconductor device comprising a capacitor structure as claimed in any one of claims 1 to 8, or comprising a capacitor structure prepared by a method of manufacturing as claimed in any one of claims 9 to 12.
14. An electronic device comprising the semiconductor device according to claim 13.
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| CN107393909A (en) * | 2017-07-25 | 2017-11-24 | 睿力集成电路有限公司 | Double sided capacitor and its manufacture method |
| CN109148426A (en) * | 2018-09-29 | 2019-01-04 | 长鑫存储技术有限公司 | Capacitance structure and forming method thereof |
| CN110504284A (en) * | 2018-05-17 | 2019-11-26 | 长鑫存储技术有限公司 | Columnar capacitor array structure and preparation method |
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| KR20100051344A (en) * | 2008-11-07 | 2010-05-17 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming using the same |
| CN107393909A (en) * | 2017-07-25 | 2017-11-24 | 睿力集成电路有限公司 | Double sided capacitor and its manufacture method |
| CN110504284A (en) * | 2018-05-17 | 2019-11-26 | 长鑫存储技术有限公司 | Columnar capacitor array structure and preparation method |
| CN109148426A (en) * | 2018-09-29 | 2019-01-04 | 长鑫存储技术有限公司 | Capacitance structure and forming method thereof |
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