CN115206970A - Capacitor, semiconductor device, electronic apparatus, and method of manufacturing the same - Google Patents

Abstract

The application relates to a capacitor structure comprising: a semiconductor substrate; a plurality of storage node contacts on the semiconductor substrate; each storage node contact part is provided with a lower electrode of a semi-surrounding structure, and each two opposite lower electrodes of the semi-surrounding structure form a pair of lower electrode pairs surrounding the upper electrode; the two opposite lower electrodes and the upper electrodes of the lower electrode pair are separated by a dielectric layer. The capacitor and the semiconductor device obtained by the manufacturing method can effectively reduce the difficulty of the manufacturing process on the premise of ensuring the performance of devices such as the storage capacity of a capacitor storage unit, and the like, and break through the limitation of the traditional 6F2 groove process mode on the basis of simplifying the process, so that the gap between the capacitors is reduced, the size of the prepared capacitor is smaller than that of the existing capacitor, and the integration level of the semiconductor device is improved.

Description

Capacitor, semiconductor device, electronic apparatus, and method of manufacturing the same

Technical Field

The present application relates to a capacitor and a method of manufacturing the same, and also relates to a semiconductor device, an electronic apparatus, and a method of manufacturing the same including the capacitor.

Background

In recent years, semiconductor manufacturers have been increasingly researching high-integration, high-speed semiconductor devices, as semiconductor users demand semiconductor devices having low power consumption, high storage capacity, and high-speed characteristics. In particular, dynamic Random Access Memory (DRAM) is widely used as a semiconductor Memory cell because of its free data input/output capability and large storage capacity.

However, in order to rapidly improve the integration and scalability of the memory, the integration density of the semiconductor device is continuously increased, and the design size standard of the semiconductor device is also continuously reduced. For example, a DRAM is typically a collection of cells, each of which has a MOS (Metal Oxide Semiconductor) transistor and a storage capacitor. As the integration level increases, the size of the semiconductor chip decreases, and the size of the capacitor necessarily decreases, which gradually decreases the distance between the electrodes and accordingly decreases the capacitance of the capacitor, thereby decreasing the storage capacity of the capacitor. However, even in consideration of the increase in the integration degree of the semiconductor memory, it is necessary to make the capacitor have a sufficient capacitance to ensure smooth operation and performance of the semiconductor memory device.

There are two main types of currently used DRAM memories: one is a DRAM memory with an 8F2 memory cell area; the other is a DRAM memory with a 6F2 cell area. Among them, a DRAM memory having 8F2 memory cells is widely used in a DRAM memory due to an improved signal-to-noise ratio, but consumes more memory cell area than a memory having 6F2 memory cells because it has many vacant areas. While memories having 6F2 memory cells provide some improvement in reducing the area of the memory cells, there are problems with producing them using this technique, such as process difficulties associated with smaller memory cells.

Therefore, how to provide a manufacturing method of a capacitor memory cell with a simpler manufacturing process to achieve a smaller memory cell area and a higher charge storage capability is an important technical problem to be solved urgently by those skilled in the art.

Disclosure of Invention

The purpose of the application is realized by the following technical scheme:

in accordance with one or more embodiments, the present application discloses a capacitor structure comprising:

a semiconductor substrate;

a plurality of storage node contacts on the semiconductor substrate;

each storage node contact part is provided with a lower electrode of a semi-surrounding structure, and each two opposite lower electrodes of the semi-surrounding structure form a pair of lower electrode pairs surrounding the upper electrode;

the two opposite lower electrodes and the upper electrodes of the lower electrode pair are separated by a dielectric layer.

In accordance with one or more embodiments, the present application also discloses a method of manufacturing a capacitor structure, comprising the process steps of:

providing a semiconductor substrate, wherein a storage node contact part is arranged on the semiconductor substrate;

forming a sacrificial mold layer on a semiconductor substrate;

etching the sacrificial mold layer to form a plurality of lower electrode grooves, and exposing the surfaces of two adjacent storage node contact parts in each lower electrode groove;

depositing a lower electrode layer to fill the lower electrode groove, and then carrying out chemical mechanical planarization treatment or back etching treatment to expose the sacrificial mold layer;

etching the lower electrode layer and the sacrificial mold layer to form an upper electrode groove, wherein the upper electrode groove divides the lower electrode layer into a pair of opposite lower electrodes with a semi-surrounding structure;

and forming a dielectric layer and an upper electrode in the upper electrode groove.

The application also discloses a semiconductor device, an electronic device and the like comprising the capacitor structure or the capacitor structure prepared by the manufacturing method according to one or more embodiments.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application, or may be learned by the practice of the embodiments. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1a-1h are schematic diagrams of a process for fabricating a capacitor structure according to an embodiment of the present disclosure.

Fig. 2 is a cross-sectional top view of a capacitor structure of an embodiment of the present application.

Fig. 3 is a pattern used when forming the lower electrode groove in the embodiment of the present application.

Fig. 4a to 4c are patterns used when forming the upper electrode groove in the embodiment of the present application.

FIG. 5 is a diagram showing the corresponding position relationship between the upper electrode groove and the lower electrode groove.

Detailed Description

The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. However, the present application is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" and the like include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit of the present application.

Moreover, relative terms, such as "lower" or "bottom" and "upper" or "top," are used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the lower side of another element would then be turned over to be on the upper side of the other element. The exemplary term "lower" therefore includes both "lower" and "upper" directions, depending on the particular orientation of the figure. Likewise, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented above the other elements. Thus, the exemplary terms "below" or "beneath" encompass both an orientation of above and below.

Embodiments of the present application are described herein with reference to cross-sectional (and/or plan) views that schematically illustrate idealized embodiments of the present application. Likewise, deviations from the schematic shape due to, for example, manufacturing processes and/or tolerances, can be expected. Thus, embodiments of the present application are not to be considered as limiting the particular shapes of regions illustrated herein, but to include deviations in shapes that result, for example, from manufacturing. For example, etched areas illustrated or described as rectangles typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present application.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. It will be understood by those skilled in the art that references to a structural or functional component disposed adjacent to another component may have portions that overlap or underlie the other component.

The application discloses a capacitor structure and a manufacturing method thereof. Each storage node of the capacitor has a lower electrode of a semi-surrounding structure, which may be, for example, semi-cylindrical in shape, and two opposing lower electrodes of the semi-surrounding structure form a lower electrode pair surrounding an upper electrode, and any suitable shape that can be obtained by one skilled in the art. The following embodiments take a capacitor formed by a lower electrode having a semi-cylindrical semi-surrounding structure as an example, but the application is not limited thereto, and the specific capacitor structure and the manufacturing process are as follows:

as shown in fig. 1h and fig. 2, the semiconductor device including a capacitor structure is illustrated in this embodiment mode, and the semiconductor device may be used in some electronic device, such as a smart phone, a computer, a tablet computer, a wearable smart device, an artificial smart device, a mobile power supply, and the like. The Semiconductor device includes a Semiconductor substrate, for example, a Semiconductor substrate of a circuit element of a MOS (Metal Oxide Semiconductor) transistor, on which functional components (not shown) such as a gate, a source/drain, and a bit line are formed. An Interlayer insulating layer 201 (Interlayer Insulation) is formed on the semiconductor substrate; a Storage Node contact 202 (Storage Node) is formed on the interlayer insulating layer 201. A lower electrode 209 may be formed on the upper portion of each storage node contact 202, the lower electrode 208 in this embodiment has, for example, a semi-cylindrical, C-shaped, open semi-surrounding structure, and the C-shaped openings of the two lower electrodes 209A and 209B located above two adjacent storage nodes are mirror-opposed to each other to form a lower electrode pair surrounding the periphery of the upper electrode 210, and a dielectric layer 210 is formed between the lower electrode 209A, the lower electrode 209B, and the upper electrode 219 to separate the three from each other. Thus, the bottom electrode 209A and the top electrode 211, and the bottom electrode 209B and the top electrode 211 form two independent capacitor memory cells. Viewed from the whole, on a cross section parallel to the semiconductor substrate, all the lower electrodes may be linearly arranged in parallel along the first direction, and the linearly arranged lower electrodes are distributed in a staggered manner on two adjacent lines; meanwhile, all the upper electrodes can also be linearly arranged in parallel along a second direction perpendicular to the first direction, and the linearly arranged upper electrodes are also in staggered distribution on two adjacent lines. In other embodiments, it is also possible to make the upper electrodes on the same line be connected two by two as one body, or it is also possible to make all the upper electrodes on the same line be connected to one another as one body, in a cross section parallel to the semiconductor substrate.

Referring next to fig. 1a-1h, the process and materials used for the semiconductor device according to one embodiment of the present application will be described in further detail:

in the process of the present application, a semiconductor substrate on which a circuit element such as a BCAT (Buried Channel Array Transistor) is already formed may be provided, and functional components (not shown) such as a gate, a source/drain, and a bit line may be formed on the semiconductor substrate.

As shown in fig. 1a, an Interlayer insulating layer 201 (Interlayer Insulation) may be formed on a semiconductor substrate; a Storage Node 202 (Storage Node) is formed on the interlayer insulating layer 201, and the Storage Node 202 (Storage Node) may be formed of a material such as W or Co.

Subsequently, a sacrificial Mold layer 203 (Mold) may be formed on the surface of the interlayer insulating layer 201 and the storage node 202, and the sacrificial Mold layer 203 may be formed of an Oxide, that is, an Oxide sacrificial Mold layer (Mold Oxide), and a material thereof may include a doped Oxide, for example, any one or a combination of two or more of SiO2, siOH, PSG (Phosphosilicate glass), BPSG (Borophosphosilicate glass), siCOH, TEOS (tetra ethyhosphosilicate, tetraethoxysilane); the sacrificial layer may also be a multi-layer layered structure, such as a TEOS layered structure. The sacrificial layer may be formed by a suitable process such as Chemical Vapor Deposition (CVD), low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).

Subsequently, a Hard Mask layer 204 (HM, hard Mask) may be formed on the surface of the sacrificial oxide film layer 203, and the Hard Mask layer may include a common Hard Mask material such as a polysilicon (Poly-Si), a doped silicon (Dope-Si), an Amorphous Carbon (ACL), a spin-on Silicon (SOH) layer, and the like, which are formed by a CVD process. In other embodiments, the hard mask layer may not be formed, and the photoresist layer may be directly used for patterning and subsequent etching.

Subsequently, a PhotoResist layer 205 (PR) may be formed on the surface of the hard mask layer 204, and the PhotoResist layer may be formed using, for example, a spin coating process or the like; subsequently, the photoresist layer 205 may be patterned by a developing process to expose the surface of the hard mask layer 204. The mask pattern for removing the photoresist portion is shown in fig. 3, and the mask pattern is composed of a plurality of rectangular lower electrode groove mask pattern units, which may be linearly arranged in parallel along a first direction on a cross section parallel to the semiconductor substrate and in a staggered distribution on two adjacent lines; the projection of each lower electrode recess mask pattern unit onto a cross-section parallel to the semiconductor substrate is normalized to substantially cover two adjacent storage nodes (see structure shown in connection with fig. 2).

As shown in fig. 1b, a photoresist layer 205 patterned according to the mask pattern shown in fig. 3 may be etched by a conventional etching means to obtain a lower electrode groove 206, and a top view cross-sectional structure of the lower electrode groove 206 may be shown in fig. 2 and 3, wherein a rectangular frame of the lower electrode groove mask pattern unit substantially corresponds to a position of the lower electrode groove, that is, the etching of the lower electrode groove 206 may be based on that the bottom of the groove substantially exposes all surfaces of two adjacent storage nodes 202. The etch may be performed using a conventional dry etch process, e.g., using CH ₂ F ₂ /O ₂ /Ar/CHF ₃ The dry etching process of the fluorine-containing gas; conventional wet etch processes may also be used, including, for example, HF and NH ₄ Mixed buffer solutions of F, e.g. HF: NH mixed in a ratio of about 1: 6 to 1: 10 ₄ LAL solution of F.

The hard mask layer 204 and the photoresist layer 205 may then be removed, for example, using a conventional ashing process or the like.

As shown in fig. 1c, a lower Electrode material may be deposited in the lower Electrode groove 206 to fill the lower Electrode groove 206 and cover the sacrificial mold layer 203, forming a lower Electrode layer 207 (Bottom Electrode); since the prior art generally employs high dielectric constant dielectric materials, e.g. Ta ₂ O ₅ 、Al ₂ O ₃ And/or HfO ₂ Etc. are used as dielectric layers of capacitors and the quality of the interface between the dielectric material and the polysilicon electrode may be reduced. In particular, the quality of the interface between the dielectric material and the polysilicon electrode may decrease as the dielectric constant increases, and therefore, high work function (work function) metals, such as TiN, may be used _x 、TaN _x 、WN _x Any one or more than two of the refractory metal materials are combined into the lower electrode to replace the traditional polysilicon electrode. The deposition process may employ a common CVD, PECVD, ALD (atomic layer vapor deposition), or the like.

As shown in fig. 1d, the surface of the lower electrode layer may be subsequently subjected to a Chemical Mechanical Planarization (CMP) process until the top surface of the sacrificial mold layer 203 is exposed, so that the lower electrode layers may be isolated from each other. Of course, other processes may be used to perform an Etch Back (Etch Back) process on the surface of the lower electrode layer to expose the top surface of the sacrificial layer 203 so as to isolate the lower electrode layers from each other, such as a reactive ion dry etching process (RIE).

As shown in fig. 1e, a Hard Mask layer 204' (HM, hard Mask) may be subsequently formed on the surfaces of the lower electrode layer 207 and the sacrificial mold layer 203, and the Hard Mask layer may include a common Hard Mask material such as a polysilicon (Poly-Si), a doped silicon (Dope-Si), an Amorphous Carbon (ACL), a spin-on Silicon (SOH) layer, or the like, which is formed using a CVD process. In other embodiments, the hard mask layer may not be formed, and the photoresist layer may be directly used for patterning and subsequent etching.

As shown in fig. 1f, a PhotoResist layer 205 '(PR) may then be formed on the surface of the hard mask layer 204', which may be formed using, for example, a spin-on process; subsequently, the photoresist layer 205 'may be patterned by a developing process to expose the surface of the hard mask layer 204', and the patterning may employ, for example, a double patterning technique or a multiple patterning technique. The mask pattern for removing the photoresist portion is shown in fig. 4a, and the mask pattern is composed of a plurality of upper electrode groove mask pattern units which are crossed in a "+" shape, and the plurality of upper electrode groove mask pattern units can be linearly arranged in parallel along a second direction perpendicular to the first direction on a section parallel to the semiconductor substrate, and are distributed in a staggered manner on two adjacent lines; as shown in fig. 5, the upper electrode groove mask pattern units may correspond to the lower electrode groove mask pattern units one-to-one, and an intersection of a "+" cross of a projection of each upper electrode groove mask pattern unit on a section parallel to the semiconductor substrate is aligned with a center of a projection of the corresponding lower electrode groove mask pattern unit on a section parallel to the semiconductor substrate, such that all projections of the "+" cross of patterns extending in the first direction fall inside projections of the lower electrode groove mask pattern units to mainly form deposition grooves of the dielectric layer and the upper electrodes in the lower electrode layer, and projections of the patterns extending in the second direction extend outside projections of the lower electrode groove mask pattern units to "split" each lower electrode layer unit into two independent lower electrodes to form a lower electrode pair surrounding the upper electrodes; in this embodiment, similar to the rectangular shape of the lower electrode groove mask pattern unit, the pattern of the upper electrode groove mask pattern unit extending along the first direction and the pattern of the upper electrode groove mask pattern unit extending along the second direction are both rectangular, and in order to realize the respective functions, the width of the lower electrode groove mask pattern unit is greater than the width of the pattern of the upper electrode groove mask pattern unit extending along the first direction (so as to ensure that all the patterns of the upper electrode groove mask pattern unit extending along the first direction fall inside the lower electrode groove mask pattern), the width of the pattern of the upper electrode groove mask pattern unit extending along the first direction is greater than the width of the pattern of the upper electrode groove mask pattern unit extending along the second direction (so that the pattern of the upper electrode groove mask pattern unit extending along the second direction can realize the "spacing" function), and at the same time, the length of the pattern of the upper electrode groove mask pattern unit extending along the second direction is at least slightly greater than the width of the lower electrode groove mask pattern unit (so as to ensure that the pattern of the upper electrode groove mask pattern unit extending along the second direction extends outside the lower electrode groove mask pattern to ensure the "spacing". In other embodiments, as shown in fig. 4b, two adjacent "+" crosses on the same line are connected, so that the patterning process becomes simpler and easier, and the process difficulty is reduced on the premise of not affecting the device performance; and further in other embodiments, all "+" crosses on the same line can also be connected to each other as shown in fig. 4c to further simplify the pattern and process.

Subsequently, a conventional etching means may be used to perform an etching process on the hard mask layer 204 'and the lower electrode layer 207 according to the patterned photoresist layer 205' to obtain an upper electrode groove 208, a cross-sectional top view of the upper electrode groove 208 may correspond to that shown in fig. 4a, 4B, or 4C, a bottom of the upper electrode groove 208 is standard to expose surfaces of two adjacent storage nodes 202, and after the etching, each lower electrode layer 207 is divided into two lower electrodes 209A and 209B having a semi-cylindrical and C-shaped opening and a semi-surrounding structure. The etch may be performed using a conventional dry etch process, e.g., using CH ₂ F ₂ /O ₂ /Ar/CHF ₃ The dry etching process of the fluorine-containing gas; conventional wet etch processes may also be used, including, for example, HF and NH ₄ Mixed buffer solutions of F, e.g. HF: NH mixed in a ratio of about 1: 6 to 1: 10 ₄ LAL solution of F.

The hard mask layer 204 'and photoresist layer 205' may then be removed, for example, using a conventional ashing process or the like.

As shown in fig. 1g, a high dielectric material may then be deposited on the inner walls of the upper electrode groove 208 and the surfaces of the lower electrodes (including all the lower electrodes 209A and 209B) and the sacrificial mold layer 203 to form a dielectric layer 210; alO can be used as the high dielectric material _x 、HfO _x 、ZrO _x 、TaO _x Etc. or two or more of themCombining; the deposition process is, for example, an ALD process.

As shown in fig. 1h, an upper electrode material may then be deposited on the surface of the dielectric layer 210 to cover the dielectric layer 210 and fill the upper electrode recess 208 to form an upper electrode 211; the upper electrode material adopts metal W or doped silicon and the like. The deposition process may be CVD, PECVD, etc. As shown in the cross-sectional plan view of fig. 2, it is obtained that a lower electrode 209 is formed on the upper portion of each storage node 202, the lower electrode 209 has a semi-enclosed structure with a semi-cylindrical shape and a C-shape, and the openings of the semi-cylindrical shapes are mirror-opposed to each other, so that two lower electrodes 209A and 209B located above two adjacent storage nodes form a lower electrode pair, the lower electrode pair surrounds the periphery of the upper electrode 211, a dielectric layer 210 is formed between the lower electrode 209A, the lower electrode 209B and the upper electrode 211, and the lower electrode 209A, the upper electrode 211, the lower electrode 209B and the upper electrode 211 are separated from each other, and the lower electrode 209A, the upper electrode 211 and the lower electrode 209B form two independent capacitor storage units. Of course, based on the difference of the patterning, a capacitor in which the upper electrodes adjacent to each other along the same line in the second direction are connected two by two in the entire vertical direction to the semiconductor substrate to form a whole may also be obtained, that is, four lower electrodes (two lower electrode pairs) correspond to the upper electrodes that are integrated in the entire vertical direction to the semiconductor substrate; it is also possible to make all the upper electrodes on the same line along the second direction integrally connected to each other in the entire direction perpendicular to the semiconductor substrate, that is, all the lower electrode pairs on the same column correspond to the upper electrodes integrally formed in the entire direction perpendicular to the semiconductor substrate.

The capacitor and the semiconductor device obtained by the manufacturing method can effectively reduce the difficulty of the manufacturing process on the premise of ensuring the device performances such as the storage capacity of a capacitor storage unit, and the like, and break through the limitation of the traditional 6F2 groove process mode on the basis of simplifying the process, thereby reducing the gap between the capacitors, preparing the capacitor with a smaller size than that of the existing capacitor, and improving the integration level of the semiconductor device.

In the above description, details of the techniques such as patterning and etching of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the disclosure, and these alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (15)

1. A capacitor structure, comprising:

a semiconductor substrate;

a plurality of storage node contacts on the semiconductor substrate;

each storage node contact part is provided with a lower electrode of a semi-surrounding structure, and each two opposite lower electrodes of the semi-surrounding structure form a pair of lower electrode pairs surrounding the upper electrode;

the two opposite lower electrodes and the upper electrodes of the lower electrode pair are separated by a dielectric layer.

2. The capacitor structure of claim 1, wherein:

on a cross section parallel to the semiconductor substrate, the lower electrodes are linearly arranged in parallel along a first direction, and the upper electrodes are linearly arranged in parallel along a second direction perpendicular to the first direction.

3. A capacitor structure according to claim 2, characterized in that:

the lower electrodes in linear arrangement are in staggered distribution on two adjacent lines; or, the lower electrodes arranged linearly are distributed in a staggered manner on two adjacent lines, and the upper electrodes arranged linearly are distributed in a staggered manner on two adjacent lines.

4. A capacitor structure according to claim 2, characterized in that:

the upper electrodes on the same line are connected into a whole in pairs; alternatively, all the upper electrodes on the same line are connected to each other as a single body.

5. The capacitor structure of any one of claims 1-4, wherein:

and on a section parallel to the semiconductor substrate, each two opposite lower electrodes of the semi-surrounding structure are in opposite C shapes.

6. A method for manufacturing a capacitor structure comprises the following process steps:

providing a semiconductor substrate, wherein a storage node contact part is arranged on the semiconductor substrate;

forming a sacrificial mold layer on a semiconductor substrate;

etching the sacrificial mold layer to form a plurality of lower electrode grooves, and exposing the surfaces of two adjacent storage node contact parts in each lower electrode groove;

depositing a lower electrode layer to fill the lower electrode groove, and then carrying out chemical mechanical planarization treatment or back etching treatment to expose the sacrificial mold layer;

etching the lower electrode layer and the sacrificial mold layer to form an upper electrode groove, wherein the upper electrode groove divides the lower electrode layer into a pair of opposite lower electrodes with a semi-surrounding structure;

and forming a dielectric layer and an upper electrode in the upper electrode groove.

7. The manufacturing method according to claim 6, characterized in that:

when the sacrificial film layer is etched to form a plurality of lower electrode grooves, the adopted plurality of lower electrode groove mask pattern units are linearly arranged on the section parallel to the semiconductor substrate along the first direction in a parallel mode, and the lower electrode groove mask pattern units are distributed in a staggered mode on two adjacent lines.

8. The manufacturing method according to claim 7, characterized in that:

when the lower electrode layer and the sacrificial mold layer are etched to form the upper electrode groove, a plurality of upper electrode groove mask pattern units which correspond to the lower electrode groove mask pattern units one by one are adopted, the upper electrode groove mask pattern units are linearly arranged in parallel along a second direction perpendicular to the first direction on a cross section parallel to the semiconductor substrate, each upper electrode groove mask pattern unit is approximately in a cross shape of a plus sign, the cross point of the projection of each upper electrode groove mask pattern unit on the cross section parallel to the semiconductor substrate of the plus sign is aligned with the center of the projection of the corresponding lower electrode groove mask pattern unit on the cross section parallel to the semiconductor substrate, the projections of the patterns extending along the first direction of the plus sign all fall into the projection of the lower electrode groove mask pattern units, and the projections of the patterns extending along the second direction extend to the outside of the projection of the lower electrode groove mask pattern units.

9. The manufacturing method according to claim 8, characterized in that:

every two adjacent pattern units which are crossed in a plus shape and are on the same line in the second direction are connected; alternatively, all pattern units crossing at a "+" cross on the same line in the second direction are connected to each other.

10. The manufacturing method according to claim 8, characterized in that:

the pattern of the lower electrode groove mask pattern unit, the pattern of the upper electrode groove mask pattern unit extending along the first direction and the pattern of the upper electrode groove mask pattern unit extending along the second direction are rectangular, and the width of the pattern of the upper electrode groove mask pattern unit extending along the first direction is larger than the width of the pattern of the upper electrode groove mask pattern unit extending along the second direction.

11. The manufacturing method according to claim 6, characterized in that:

the etching is carried out according to the patterned photoresist layer and the mask layer; alternatively, the etching is performed only on the basis of a patterned photoresist layer.

12. The manufacturing method according to claim 11, characterized in that:

the patterning is performed by double patterning (double patterning) or multiple patterning (multiple patterning) techniques.

13. A semiconductor device comprising a capacitor structure according to any one of claims 1 to 5 or a capacitor structure produced by the method of manufacture according to any one of claims 6 to 12.

14. An electronic device comprising the semiconductor device according to claim 13.

15. The electronic device of claim 14, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.

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