KR20030055797A - a method for manufacturing capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of improving capacitance by increasing the surface area of MIM capacitor. CONSTITUTION: After forming an insulating layer(103) on a logic circuit region, the first metal patterns(102) are formed in the insulating layer. The first interlayer dielectric(107) having the first trench and the first via hole is formed on the resultant structure. The first plug(109b) is filled into the first via hole and the first spacer(105a) is formed at both sidewalls of the first trench. The second metal pattern(110b) is formed to connect the first plug and a lower electrode(110a) is simultaneously formed in the first trench. A dielectric film(111) is formed on the lower electrode. The second interlayer dielectric(112) having the second trench and the second via hole is formed on the resultant structure. The second plug(114) is filled into the second via hole, and the second spacer is formed at both sidewalls of the second trench. An upper wiring(115b) is formed to connect the second plug(114) and an upper electrode(115a) is simultaneously formed in the second trench.

Description

A method for manufacturing capacitor of semiconductor device

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device capable of improving capacitance by increasing the surface area of a capacitor having a metal-insulator-metal (MIM) type structure.

Recently, a mixed semiconductor (MML: Merged Memory Logic), in which memory and logic are formed on a single chip, is showing increasing interest and is increasingly used. In addition, the MML semiconductor device can manufacture logic and memory in a single process on a single chip, enabling high-speed operation and low power consumption compared to existing chips without special design changes.

However, since the manufacturing process of the memory product and the manufacturing process of the logic product are simultaneously manufactured on one chip, the size of a single chip increases, and thus, there are many difficulties in proceeding with the manufacturing process.

In addition, in memory, transistors focus on preventing leakage current rather than requiring high current driving force, but logic products must be manufactured in one chip with both characteristics such as high current driving capability.

On the other hand, in general, when the capacitor has a poly insulator poly (PIP) structure, since the upper electrode and the lower electrode are used as conductive polysilicon, an oxidation reaction occurs at the interface between the upper electrode / lower electrode and the dielectric thin film to form a natural oxide film, thereby forming the entire capacitor. There is a disadvantage that the size of is reduced.

To solve this problem, the structure of the capacitor was changed from MIS (Metal Insulator Silicon) to MIM (Metal Insulator Metal). Among them, the MIM type capacitor is mainly used in high-performance semiconductor devices because of its low resistivity and no parasitic capacitance caused by depletion. It is used.

Hereinafter, a capacitor manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional semiconductor device.

Although not shown in FIG. 1A, word lines and bit lines are formed in a memory cell region on a semiconductor substrate having a memory cell region and a logic circuit region, and gate electrodes are formed in the logic circuit region.

Subsequently, a first planarization insulating film 11 is formed on the resultant, and a first metal layer 12, a dielectric film 13, and a second metal layer are formed on the first planarizing insulating film 11 in the logic circuit region. 14) are formed in sequence.

After depositing the first photoresist 15 on the second metal layer 14, the first photoresist 15 is patterned by using an exposure and development process and the patterned first photoresist 15. The second metal layer 14 and the dielectric film 13 are selectively etched using a mask as a mask to form the upper electrode 14a of the capacitor.

After removing the patterned first photoresist 15 as shown in FIG. 1B, a second photoresist 16 is deposited on the entire surface. The second photoresist 16 is patterned by using an exposure and development process.

Subsequently, the first metal layer 12 is selectively etched using the patterned second photoresist 16 as a mask to form a lower electrode 12a and a lower metal wiring 12b of the capacitor.

After removing the second photoresist 16 as shown in FIG. 1C, a second planarization insulating film 17 is formed on the resultant, and the lower metal wiring 12b and the lower part are formed using a photolithography process. A plurality of via holes 18 are formed to expose the electrode 12a and the upper electrode 14a.

As shown in FIG. 1D, a third metal layer is deposited on the second planarization insulating layer 17 including the plurality of via holes 18, and then a plug 19 is formed using an etch back process. In this case, the third metal layer 19 is tungsten.

Subsequently, after depositing a fourth metal layer on the resultant, the fourth metal layer is selectively removed through a photolithography process to form the upper wiring 20a, and at the same time, the upper electrode 14a and the lower electrode of the capacitor ( The connection wiring 20b of 12a is formed.

However, there is a problem in the method of manufacturing a capacitor of the semiconductor device as described above.

Conventional MIM capacitors have a flat planar structure, with a dielectric film having a thickness of ˜600 kW and an upper electrode of ˜1500 kW, and a step of about 2000 kW occurs with a portion where no capacitor is formed.

In addition, large capacitance is required due to the increase in the density of the device and the decrease in the design loop, but the capacitance value that can be obtained for a certain area is limited because the conventional capacitor relies only on the increase of the planar area.

An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device having a high capacitance by increasing the area of the dielectric film of the MIM capacitor by using a trench.

1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional semiconductor device.

2A through 2F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101: first interlayer insulating film 102: first metal pattern

103: second interlayer insulating film 104a: first trench

104b: first via hole 105a: first spacer

105b: first plug 106: second metal pattern

107: third interlayer insulating film 108a: second trench

108b: second via hole 109a: second spacer

109b: second plug 110: third metal layer

110a: lower electrode 110b: third metal pattern

111 dielectric film 112 fourth interlayer insulating film

113a: third trench 113b: third via hole

114: third plug 115a: upper electrode

115b: Connection wiring

In the method of manufacturing a capacitor of a semiconductor device of the present invention for achieving the above object, in the MIM capacitor manufacturing method, a word line and a bit line are formed in a memory cell region on a semiconductor substrate, and a gate electrode is formed in the logic circuit region. In the semiconductor device formed, forming a planarization insulating film on the resultant portion of the logic circuit region, and forming a plurality of first metal patterns having a predetermined interval between the planarizing insulating film, the first metal pattern is Forming a first interlayer insulating film having a first trench and a first via hole to be exposed, forming a first plug to fill the first via hole and simultaneously forming a first spacer on the sidewalls of the first trench; A second metal pattern is formed to be connected to the first plug and a lower electrode of the capacitor is formed in the first trench. Forming a dielectric film on the lower electrode, and forming a second interlayer insulating film having a second trench and a second via hole so that the dielectric film is exposed and the lower electrode and the second metal pattern are exposed. And forming a second plug on the sidewalls of the second trench at the same time to form the second plug to fill the second via hole, and forming a metal wiring to be connected to the second plug, and at the same time on the second trench. Forming an upper electrode of the capacitor.

Further, after forming the first plug and the first spacer, forming a third metal pattern to be connected to the first plug, exposing the third metal pattern, and exposing the first metal pattern. Forming a third interlayer insulating film having a third via hole and a third trench, and forming a third plug on the sidewalls of the third trench while forming a third plug to fill the third via hole. It features.

The first, second and third plugs and the first, second and third spacers are preferably formed by depositing tungsten on the entire surface and then performing an etch back process.

It is also preferable to carry out the CMP process after depositing the tungsten.

In addition, the first, second and third trenches may be formed larger than the first, second and third via holes.

Hereinafter, a capacitor manufacturing method of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, word lines and bit lines are formed in a memory cell region on a semiconductor substrate having a memory cell region and a logic circuit region, but gate electrodes are formed in the logic circuit region.

Subsequently, a first interlayer insulating film 101 is formed on the resultant, and a plurality of first metal patterns 102 are selectively formed on the first interlayer insulating film 101 of the logic circuit region. A second interlayer insulating film 103 is formed in the film.

Subsequently, the second interlayer insulating layer 103 is selectively etched so that the first metal pattern 102 is exposed through the photolithography process on the second interlayer insulating layer 103 to form a first trench 104a and a first via hole. Form 104b.

As shown in FIG. 2B, a first metal layer is deposited on the second interlayer insulating layer 103 including the first trench 104a and the first via hole 104b, and then etched back or CMP (Chemical Mechanical Polishing). By using the process, the first spacer 105a is formed on the sidewall of the first trench 104a, and the first plug 105b is formed to fill the first via hole 104b. In this case, the first metal layer is tungsten.

Subsequently, a second metal pattern 106 is formed to be connected to the first plug 105b, a third interlayer insulating layer 107 is formed on the resultant, and then photolithography is performed on the third interlayer insulating layer 107. By using the process, the second trench 108a is formed to expose the first trench 104a and the second via hole 108b is formed to expose the second metal pattern 106.

As shown in FIG. 2C, a second metal layer is deposited on the third interlayer insulating layer 107 including the second trench 108a and the second via hole 108b, and then, by using an etch back process or a CMP process. The second spacer 109a is formed on the sidewall of the second trench 108a and the second plug 109b is formed to fill the second via hole 108b. In this case, the second metal layer is tungsten.

Subsequently, the third metal layer 110 and the dielectric film 111 are sequentially deposited on the resultant, and the dielectric film 111 is selectively etched.

As shown in FIG. 2D, the third metal layer 110 is selectively etched using the photolithography process to define the lower electrode 110a and the third metal pattern 110b of the capacitor. do.

As illustrated in FIG. 2E, a fourth interlayer insulating layer 112 is deposited on the resultant, and the fourth interlayer insulating layer 112 is selectively etched through a photolithography process to expose the dielectric layer 111. The third trench 113a is formed and a plurality of third via holes 113b are formed to expose the lower electrode 110b and the third metal pattern 110b of the capacitor.

The first, second, and third trenches 104a, 108a, and 113a may be formed larger than the first, second, and third via holes 104b, 108b, and 113b.

As shown in FIG. 2F, after depositing a fourth metal layer on the fourth interlayer insulating layer 112 including the third trench 113a and the third via hole 113b, an etch back process or a CMP process may be performed. A third plug 114 is formed in the third trench 113a and the third via hole 113b. In this case, the fourth metal layer is tungsten.

Subsequently, after depositing a fifth metal layer on the resultant, a capacitor upper electrode 115a is defined on the third spacer 114a through a photolithography process, and a plurality of connected to the third plug 114b is formed. The connection wiring 115b is formed.

As described above, according to the method of manufacturing a capacitor of the semiconductor device of the present invention, since the upper electrode of the capacitor is formed in the trench region, it is possible to solve the step difference problem of the conventional stack capacitor.

In addition, it is possible to form a capacitor having a large capacitance through an increase in surface area using a trench, an increase in capacitance that depends only on an area increase on a conventional plane.

That is, since the trench depth can be adjusted, the capacitance value of a certain region can be obtained without changing the capacitor pattern size.

Claims (5)

In a semiconductor device in which a word line and a bit line are formed in a memory cell region on a semiconductor substrate, and a gate electrode is formed in the logic circuit region. Forming a planarization insulating film on the resultant portion of the logic circuit region, and forming a plurality of first metal patterns having a predetermined interval between the planarizing insulating films; Forming a first interlayer insulating film having a first trench and a first via hole to expose the first metal pattern; Forming a first spacer on the sidewalls of the first trench at the same time as the first plug is formed to fill the first via hole; Forming a second metal pattern to be connected to the first plug and simultaneously forming a lower electrode of the capacitor in the first trench; Forming a dielectric film on the lower electrode; Forming a second interlayer insulating film having a second trench and a second via hole so that the dielectric film is exposed and the lower electrode and the second metal pattern are exposed; Forming a second plug on the sidewalls of the second trench while forming a second plug to fill the second via hole; And forming a metal wiring to be connected to the second plug and simultaneously forming an upper electrode of the capacitor in the second trench. The method of claim 1, After forming the first plug and the first spacer, forming a third metal pattern to be connected to the first plug; Forming a third interlayer insulating layer having a third via hole and a third trench so that the third metal pattern is exposed and the first metal pattern is exposed; And forming a third spacer on the sidewalls of the third trench at the same time as the third plug is formed to fill the third via hole. The method according to claim 1 or 2, And the first, second and third plugs and the first, second and third spacers are formed by depositing tungsten on the entire surface and then performing an etch back process. The method of claim 3, wherein And depositing the tungsten, and then performing a CMP process. The method according to claim 1 or 2, And the first, second and third trenches are formed larger than the first, second and third via holes.