KR20010061518A - Method of manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is to reduce topology difference between a memory region and a logic region in MML(memory merged logic) process to secure process margin of a photolithography and contact etching process for formation of metal contact, thereby increasing production yields and reliability of the device. CONSTITUTION: A word line(42) is formed on a memory region and a logic region of a semiconductor substrate(41). The first interlayer dielectric(43) is formed on the entire structure. A bit line(44) is formed on the first interlayer dielectric in the memory region, and in a portion to be formed of a metal contact of the memory region and the logic region, the first dummy contact pattern and the first dummy pad pattern are formed respectively. The second interlayer dielectric(45) is formed on the entire structure. A capacitor is formed on the second interlayer dielectric in the memory region, and in a portion to be formed of a metal contact of the memory region and the logic region, the second dummy contact pattern and the second dummy pad pattern are formed respectively. The third interlayer dielectric is formed on the entire structure. The metal contacts for substrate, word line, bit line and capacitor are formed by implementing a metal contact process.

Description

Method of manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to reduce the topology difference between a memory region and a logic region generated in a memory merged logic (MML) process in which a memory region and a logic region are in one chip. The present invention relates to a method of manufacturing a semiconductor device capable of securing a process margin of a photolithography process for forming a metal contact and a contact etching process.

In general, in the MML process where memory and logic are in one chip, the topology of the memory region continues to accumulate until the metal contact process, whereas the logic region has a pattern of only the device isolation layer and the gate portion, thereby increasing the topology difference. .

1A and 1B are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.

Referring to FIG. 1A, after forming an isolation layer (not shown) on the semiconductor substrate 11 to define an active region, a word line is formed in each of the memory region M and the logic region L. Referring to FIG. (12) is formed. The first interlayer insulating film 13 is formed over the entire structure including the word line 12. The bit line 14 is formed in a portion of the first interlayer insulating layer 13 of the memory area M through a bit line contact mask and a bit line mask process. The second interlayer insulating film 15 is formed over the entire structure including the bit lines 14. The capacitor 16 is formed in a portion of the second interlayer insulating layer 15 of the memory region M through a capacitor contact mask and a capacitor mask process. The third interlayer insulating film 18 is formed over the entire structure including the capacitor 16.

In the above, the device isolation layer, the word line 12, the bit line 14, and the capacitor 16 are formed in the memory region M, whereas only the device isolation layer and the word line 12 are formed in the logic region L. Therefore, the topology difference between the memory region M and the logic region L after the third interlayer insulating film 18 is formed is intensified.

Referring to FIG. 1B, in order to reduce the topology difference between the memory region M and the logic region L, the third interlayer insulating layer 18 is partially polished by a chemical mechanical polishing (cMP) process to planarize the surface, and The contact process is performed to form the substrate metal contact 21, the word line metal contact 22, the bit line metal contact 23, and the capacitor metal contact 24.

In the above-described conventional method, a chemical mechanical polishing (cMP) process is applied to a premetal dielectric (PMd) to solve the topological difference, but the memory region (M) and the logic region after the chemical mechanical polishing process is completed. The topological difference between (L) is still more than 4000 Hz. In this state, when the metal contact process, which is a subsequent process, is difficult to secure process margins of the photolithography process and the contact etching process due to the difference in topology, metal contact defects are caused. In particular, the depth of the metal contact 21 for the substrate formed on the substrate 11 in the memory region M or the logic region L may be 2 μm or more, so that a high aspect ratio is required during the contact etching process. It makes the metal contact process more difficult.

Accordingly, the present invention not only secures the process margin of the photolithography process and the contact etching process for forming the metal contact by reducing the difference in topology between the memory area and the logic area, but also manufactures a semiconductor device capable of reducing the aspect ratio during the contact etching process. The purpose is to provide a method.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including forming word lines on a semiconductor substrate in a memory area and a logic area; Forming a first interlayer insulating film on the entire structure; Forming a bit line on the first interlayer insulating layer of the memory region, and forming a first dummy contact pattern and a first dummy pad pattern at a position where a metal contact between the memory region and the logic region is to be formed; Forming a second interlayer insulating film on the entire structure; Forming a capacitor on the second interlayer insulating layer of the memory region, and forming a second dummy contact pattern and a second dummy pad pattern at a position where a metal contact between the memory region and the logic region is to be formed; Forming a third interlayer insulating film on the entire structure; And forming a metal contact process for a substrate, a metal contact for a word line, a metal contact for a bit line, and a metal contact for a capacitor by performing a metal contact process in the order of the first oxide etching process, the conductive material etching process, and the second oxide etching process. Characterized in that comprises a.

1A and 1B are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.

2A to 2D are cross-sectional views of devices for explaining a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

3 is an enlarged detailed cross-sectional view of the capacitor portion of FIG.

<Explanation of symbols for the main parts of the drawings>

11, 41: semiconductor substrate 12, 42: word line

13, 43: first interlayer insulating film 14, 44: bit line

15, 45: second interlayer insulating film 16, 46: capacitor

46a: lower electrode 46b: dielectric film

46c: upper electrode 47: insulating film pattern

18 and 48: third interlayer insulating film 21 and 51: metal contact for substrate

22, 52: Metal contact for word line 23, 53: Metal contact for bit line

24, 54: Metal contact for capacitor

51a and 51b: metal contacts for first and second substrates

52a and 52b: metal contacts for first and second word lines

53a and 53b: metal contacts for first and second bit lines

54a and 54b: metal contacts for first and second capacitors

61: first dummy contact pattern 62: first dummy pad pattern

63: second dummy contact pattern 64: second dummy pad pattern

M: memory area L: logic area

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, after forming an isolation layer (not shown) on the semiconductor substrate 41 to define an active region, a word line is formed in each of the memory region M and the logic region L. Referring to FIG. To form 42. The first interlayer insulating film 43 is formed over the entire structure including the word line 42. A bit line 44 is formed in a portion of the first interlayer insulating layer 43 of the memory area M through a bit line contact mask and a bit line mask process, and simultaneously formed in the memory area M and the logic area L, respectively. The first dummy contact pattern 61 and the first dummy pad pattern 62 are formed. The second interlayer insulating film 45 is formed on the entire structure including the bit lines 44 and the dummy patterns 61 and 62. A capacitor 46 is formed in a portion of the second interlayer insulating layer 45 of the memory region M through a capacitor contact mask and a capacitor mask process, and at the same time, a second dummy contact in each of the memory region M and the logic region L. The pattern 63 and the second dummy pad pattern 64 are formed. The third interlayer insulating film 18 is formed over the entire structure including the capacitor 46 and the dummy patterns 63 and 64.

In the above description, the word line 42, the bit line 44, and the capacitor 46 are formed of a conductive material such as silicon, silicon compound, tungsten, tungsten compound, aluminum, aluminum compound, copper, or copper compound. The first, second, and third interlayer insulating films 43, 45, and 48 are formed of an oxide-based material.

The first dummy contact pattern 61 and the first dummy pad pattern 62 are formed of the same conductive material as the bit line 44 at the position where the metal contact for the substrate is to be formed. The first dummy contact pattern 61 is formed such that the first interlayer insulating film 43 remains to some extent with the semiconductor substrate 41.

The second dummy contact pattern 63 and the second dummy pad pattern 64 may have capacitors at positions where the metal contact for the substrate is to be formed, where the metal contact for the word line is to be formed, and where the metal contact for the bit line is to be formed. It is formed of the same conductive material as 46). The second dummy contact pattern 63 at the position where the substrate metal contact is to be formed is connected to the first dummy pad pattern 62 at the same position. The second dummy contact pattern 63 at the position where the word line metal contact is to be formed is formed such that the interlayer insulating layers 43 and 45 are left to some extent with the word line 42. The second dummy pad pattern 64 at the position where the bit line metal contact is to be formed is formed without a separate dummy contact pattern. When the second interlayer insulating layer on the bit line 44 is thick, the second dummy pad pattern 64 is not connected to the bit line 44. A separate dummy contact pattern may be formed.

As shown in FIG. 2A, in the process of forming each of the bit lines 44 and the capacitors 46, the dummy patterns 61, 62, 63, and 64 may be formed not only in the memory region M but also in the logic region L. FIG. ), The memory region M and the logic region L after forming the third interlayer insulating film 48 are flat without a topological difference.

2B to 2D, a metal contact process is performed to form a metal contact 51 for a substrate, a metal contact 52 for a word line, a metal contact 53 for a bit line, and a metal contact 54 for a capacitor. The metal contact process may be performed in order of a first etching process using an oxide etchant, a second etching process using a conductive material etchant, and a third etching process using an oxide etchant.

In the above-described first etching process using an oxide etchant, as illustrated in FIG. 2B, the metal contact 51a for the first substrate and the metal contact for the first word line to which the second dummy pad pattern 64 is exposed. A portion of the third interlayer insulating layer 48 is etched to form 52a and the first bit line metal contact 53a and the first capacitor metal contact 54a exposing the capacitor 46, respectively. The first substrate metal contact 51a and the first word line metal contact 52a are formed in the memory area M and the logic area L, respectively.

The second etching process using the conductive material etchant includes dummy patterns 61, 62, which are conductive material patterns exposed through the respective first metal contacts 51a, 52a, 53a, and 54a, as shown in FIG. 2C. 63 and 64 are removed to form a second substrate metal contact 51b, a second word line metal contact 52b, a second bit line metal contact 53b, and a second capacitor metal contact 54b. do. The bottom of each of the second substrate metal contact 51b, the second word line metal contact 52b, and the second bit line metal contact 53b may have a first or / and second interlayer insulating film 43 or / and 45. ) Meanwhile, in order to prevent the capacitor 46 from fully penetrating during the second etching process using the conductive material etchant, the capacitor 46 should be formed in the structure shown in FIG. 3 unlike the conventional capacitor structure. That is, the insulating film pattern 47 exists between the lower electrode 46a and the upper electrode 46c in the capacitor 46 composed of the lower electrode 46a, the dielectric film 46b, and the upper electrode 46c. The insulating layer pattern 47 is formed during the formation of the lower electrode 46a and serves as an etch stop layer during the second etching process.

The third etching process using the oxide etchant may include the first or / and second interlayer insulating film 43 or / and exposed through the respective first metal contacts 51b, 52b, and 53b, as shown in FIG. 2D. 45 is etched to complete the substrate metal contact 51, the word line metal contact 52, the bit line metal contact 53, and the capacitor metal contact 54.

The present invention described above is a technique for securing a process margin of a photolithography process and a contact etching process for forming a metal contact by reducing a topology difference between a memory region and a logic region generated in an MML process having a memory region and a logic region in one chip. In addition, when forming a conductive pattern as a cell component in a memory area, a dummy pattern is formed at a location where a subsequent metal contact is to be formed in a region where the pattern density of the logic area as well as the memory area is low. There is no difference in topology, and the etching process for forming a metal contact is performed in three steps in the order of oxide etching, conductive material etching, and oxide etching, thereby reducing the aspect ratio for each step.

As described above, the present invention not only secures the process margins of the photolithography process and the contact etching process for forming the metal contact, but also omits the chemical mechanical polishing process for the planarization of the surface, thereby increasing the reliability and yield of the device. Can be improved and high integration of the device can be realized.

Claims (7)

Forming word lines on semiconductor substrates in memory regions and logic regions; Forming a first interlayer insulating film on the entire structure; Forming a bit line on the first interlayer insulating layer of the memory region, and forming a first dummy contact pattern and a first dummy pad pattern at a position where a metal contact between the memory region and the logic region is to be formed; Forming a second interlayer insulating film on the entire structure; Forming a capacitor on the second interlayer insulating layer of the memory region, and forming a second dummy contact pattern and a second dummy pad pattern at a position where a metal contact between the memory region and the logic region is to be formed; Forming a third interlayer insulating film on the entire structure; And Forming a metal contact for a substrate, a metal contact for a word line, a metal contact for a bit line, and a metal contact for a capacitor by performing a metal contact process in the order of the first oxide etching process, the conductive material etching process, and the second oxide etching process. The manufacturing method of the semiconductor element characterized by including. The method of claim 1, The word line, bit line and capacitor are formed of a conductive material such as silicon, silicon compound, tungsten, tungsten compound, aluminum, aluminum compound, copper, copper compound. The method of claim 1, And the first, second and third interlayer insulating films are formed of an oxide-based material. The method of claim 1, The first dummy contact pattern and the first dummy pad pattern may be formed at a position at which a metal contact for a substrate is to be formed using the same process and the same material as that of the bit line, and the first dummy contact pattern may not be connected to a semiconductor substrate. The manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 1, The second dummy contact pattern and the second dummy pad pattern may be formed of the same process and the same material as that of the capacitor to form a metal contact for a substrate, a location for forming a metal contact for a word line, and a location for forming a metal contact for a bit line. The second dummy contact pattern at a position where a metal contact for a substrate is to be formed is connected to the first dummy pad pattern at a same position, and the second dummy contact pattern at a position where a metal contact for a word line is to be formed And not to be connected to the word line. The method of claim 1, The first oxide etching process etches the third interlayer insulating film to expose the second dummy pad pattern and the capacitor, and the conductive material etching process etches the dummy patterns to expose the lower interlayer insulating film. The oxide etching process is a method of manufacturing a semiconductor device, characterized in that for etching all the interlayer insulating film exposed to complete the metal contact. The method of claim 1, The capacitor includes a lower electrode, a dielectric film, and an upper electrode, wherein an insulating film pattern is formed between the lower electrode and the upper electrode.