KR100250741B1 - The manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve the reliability of a semiconductor device by removing a global step of a cell region and a peripheral circuit region. CONSTITUTION: The first polysilicon layer is formed on a cell region(A) and a peripheral circuit region(B). The polysilicon layer pattern is formed on the peripheral circuit region(B). A sacrificial oxide layer is formed on an upper portion of the whole structure. The first lower electrode(24) and a sacrificial oxide layer pattern are formed by etching selected regions of the sacrificial oxide layer and the polysilicon layer pattern. A sacrificial oxide layer pattern for buffering a global step is formed on the cell region(A). The second polysilicon layer is formed on the cell region(A) and the peripheral circuit region(B). The second lower electrode(27) is formed at a sidewall of the sacrificial oxide layer pattern of the cell region(A). The second polysilicon layer pattern is formed on the sacrificial oxide layer pattern for buffering the global step. A lower electrode of a capacitor is formed by removing the sacrificial oxide layer pattern of the cell region(A). A dielectric layer(29) and the third polysilicon layer are formed on an upper portion of the whole structure. An upper electrode(30) of the capacitor of the cell region is formed by removing the third polysilicon layer, the dielectric layer(29), and the second polysilicon layer pattern. The second insulating planarization layer is formed on the upper portion of the whole structure.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a stack capacitor used in a DRAM semiconductor device.

As DRAM devices using a stacked capacitor structure become more integrated, horizontal free space becomes smaller when forming capacitors. Thus, there is a lack of capacitance to store enough charge for data storage of the device. The lack of capacitance makes the DRAM device inoperable, and even if possible, the refresh cycle is shortened so that the yield is remarkably low, and it is very difficult to construct a circuit with a short refresh cycle. Is essential for the development of.

An easy way to ensure the capacitance of a capacitor with a narrow horizontal clearance is to increase the surface area by increasing the height of the vertical capacitor. Meanwhile, since the capacitor is formed only in the cell region of the DRAM device, the height of the capacitor structure is increased to secure the capacitance, which increases only the height of the cell region. The increased height only in the cell area creates a global step between the cell area and the surrounding circuit area. This will be described with reference to FIG. 1.

1 is a cross-sectional view of a device for explaining a conventional method of manufacturing a semiconductor device, in which a junction 12 is formed in a selected region on a semiconductor substrate 11 of a cell region A, and the cell region and peripheral circuit regions A and B) A first insulating planarization film 13 is formed on the top. The selected region of the first insulating planarization layer 13 of the cell region A is etched to form contact holes through which the junction 12 is exposed. Contact holes in the cell region A are filled to form a first lower electrode 14 connected to the junction 12, and the second lower electrode 15 contacting the first lower electrode 14 in the form of a spacer. Form. The dielectric layer 16 is formed on the second lower electrode 15 in the cell region A, and then the upper electrode 17 is formed on the dielectric layer 16. A second insulating planarization film 18 is formed over the cell region and the peripheral circuit region A and B. The first, second and third lower electrodes 14, 15 and 17 are made of polysilicon and the second lower electrode 15 is formed as high as possible to increase the capacitance. The capacitor structure thus formed increases the height of the second lower electrode 15 so as to increase the capacitance, so that the wide step difference between the cell region A and the peripheral circuit region B becomes severe.

However, the wide step between the cell area and the peripheral circuit area causes the following problems, making it difficult to form subsequent metal wiring.

First, a narrow line width is realized by reducing the process margin of the depth of focus due to the thickness difference between the cell region and the peripheral circuit region of the applied photoresist film during the post-deposition exposure process of the metal film for forming the subsequent lower metal wiring. This is difficult and the uniformity of the line width is also poor.

Second, in the subsequent etching of the lower metal wiring, the etching is poor in the stepped portions of the cell region and the peripheral circuit region, so that the metal film is not completely removed, which may cause a short circuit between the metal lines, which makes the etching process between the narrow metal lines difficult. .

Third, after the formation of the lower metal wiring, the insulation planarization process for the upper metal wiring becomes difficult, and various complicated methods have to be used to alleviate the wide area step.

Fourth, since the depth of the via contact in the peripheral circuit area for the connection of the subsequent upper metal wiring and the lower metal wiring becomes deeper, it is difficult to bury the contact of the aluminum alloy mainly used for the upper metal wiring, which may cause disconnection or voids. This phenomenon becomes more serious as the device becomes more integrated and the via contact size becomes smaller.

This problem degrades the yield and reliability of the device because the device is highly integrated and therefore more severe with the use of more multi-layered metal wiring.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of improving the yield and reliability of the device by eliminating the wide step in the cell area and the peripheral circuit area.

The semiconductor device fabrication method of the present invention for achieving the above object is to form a first insulating planarization film on a semiconductor substrate formed with a plurality of junctions in the cell region, and etching selected regions of the first insulation planarization film, respectively, Forming a contact hole in the first region; and forming a first polysilicon film on the first insulating planarization film including the contact holes, and then removing the first polysilicon film in a peripheral circuit region to remove the first polysilicon film in the cell region. Forming a sacrificial oxide film on the entire surface including the second polysilicon film pattern, and forming the sacrificial oxide film on the entire surface including the first polysilicon film pattern, and etching selected portions of the sacrificial oxide film and the first polysilicon film pattern, As a result, a plurality of first lower electrodes connected to junctions and sacrificial oxide patterns are formed on each of the first lower electrodes, respectively, in the cell region. A third step in which a sacrificial oxide pattern for wide-area step buffering is formed in the peripheral circuit area, and a second polysilicon film is formed over the entire area including the sacrificial oxide patterns and the sacrificial oxide pattern for wide-area step buffering, and then the cell region The second polysilicon layer is etched, and thus, a plurality of second lower electrodes connected to the first lower electrodes are formed on the sidewalls of the sacrificial oxide layer patterns in the form of spacers, and the first upper portion of the sacrificial oxide layer pattern for buffering the wide area difference is formed. A fourth step of forming a polysilicon film pattern, a fifth step of removing the sacrificial oxide film patterns of the cell region, and completing a lower electrode of the capacitor including the first and second lower electrodes, and a lower electrode of the capacitor. After the dielectric film and the third polysilicon film are sequentially formed on the whole including the sacrificial oxide A sixth step of sequentially removing the third polysilicon film, the dielectric film, and the second polysilicon film pattern on the pattern portion, thereby forming an upper electrode of a capacitor in the cell region; and an upper electrode of the capacitor And a seventh step of forming a second insulating planarization film over the entire area including the sacrificial oxide film pattern for wide-area step buffering.

1 is a cross-sectional view of a device for explaining a conventional semiconductor device manufacturing method.

2 (a) to 2 (j) are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention.

* Explanation of symbols for main parts of the drawings

A: cell area B: peripheral circuit area

11,21: semiconductor substrate 12,22: junction

13,23: first insulating planarization film 14,24: first lower electrode

24a: first polysilicon film 24b: first polysilicon film pattern

15,27: second lower electrode 27a: second polysilicon film

27b: second polysilicon film pattern 16, 29: dielectric film

17,30: upper electrode 30a: third polysilicon film

18,32 second insulating planarization film 26 sacrificial oxide film

26a and 26b: sacrificial oxide film pattern 31: first photosensitive film pattern

32: second photosensitive film pattern 33: third photosensitive film pattern

34: fourth photosensitive film pattern

The present invention will be described in detail with reference to the accompanying drawings.

2 (a) to 2 (j) are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention.

As shown in Fig. 2 (a), the junction 22 is formed in the selected region over the semiconductor substrate 21 in the cell region A, and the first portion is formed over the cell region and the peripheral circuit regions A and B. An insulating planarization film 23 is formed. The selected region of the first insulating planarization layer 23 of the cell region A is etched to form contact holes through which the junction 22 is exposed. A first polysilicon layer 24a is formed on the first insulating planarization layer 23 including the contact hole to be connected to the junction 22 through the contact hole.

As shown in FIG. 2 (b), a positive photoresist film is coated on the first polysilicon film 24a and the first photoresist pattern 31 is exposed and developed by using a reticle for forming an upper electrode of the capacitor. ). The first photoresist pattern 31 is formed such that the peripheral circuit region B is open. The first polysilicon film pattern 24b is formed in the cell region A by removing the first polysilicon film 24a in the peripheral circuit region B by performing an etching process using the first photoresist pattern 31 as a mask. do.

FIG. 2C is a cross-sectional view of the sacrificial oxide film 26 formed on the whole including the first polysilicon film pattern 24b after removing the first photoresist film pattern 31. In this case, the thickness of the sacrificial oxide layer 26 determines the height of the capacitor, and as the height of the capacitor increases, the capacitance increases.

As shown in FIG. 2 (d), after the relief photosensitive film is coated on the sacrificial oxide film 26, the second photosensitive film pattern 32 is formed by an exposure and development process using a reticle for forming a lower electrode of the capacitor. The sacrificial oxide layer 26 and the first polysilicon layer pattern 24b are etched using the second photoresist layer pattern 32 as a mask, and thus, a plurality of first lower electrodes connected to the junction 22 in the cell region A is thus etched. The sacrificial oxide patterns 26a for forming the second lower electrode are formed on the upper portion 24 and the upper portion of each of the first lower electrodes 24, respectively, and the sacrificial oxide patterns 26b for wide-area buffering are formed in the peripheral circuit area B. ) Is formed.

As shown in FIG. 2E, after the second photoresist layer pattern 32 is removed, the second polysilicon layer 27a is formed on the whole including the plurality of sacrificial oxide layer patterns 26a and 26b.

As shown in Fig. 2 (f), after applying the negative photoresist film, a third photoresist pattern 33 having only the cell region A is opened in the exposure and development process by using the upper electrode forming reticle of the capacitor again. do. The second polysilicon film 27a is etched by performing a polysilicon dry spacer etching process using the third photoresist pattern 33 as a mask, thereby forming a second silicon film 27a on the sidewalls of the sacrificial oxide pattern 26a of the cell region A. The second lower electrode 27 connected to the first lower electrode 24 is formed in a spacer shape, and a second polysilicon layer pattern 27b is formed on the sacrificial oxide pattern 26b of the peripheral circuit region B. .

As shown in FIG. 2 (g), after removing the third photoresist pattern 33, the sacrificial oxide pattern 26a of the cell region A is removed using an oxide wet etching solution such as BOE, HF, or the like to form the lower electrode of the capacitor. This is done. At this time, since the sacrificial oxide pattern 26b of the peripheral circuit region B is completely sealed by the second polysilicon layer pattern 27b, the sacrificial oxide pattern 26b is not removed during the oxide wet etching process and is preserved as it is.

As shown in Fig. 2 (h), the dielectric film 29 and the third polysilicon film 30a are sequentially formed on the entire upper part of the capacitor including the lower electrodes of the first and second lower electrodes 24 and 27. Is formed.

As shown in Fig. 2 (i), after the embossed photosensitive film is applied, the fourth photosensitive film pattern 34 is formed by an exposure and development process using the upper electrode forming reticle of the capacitor again. The fourth photoresist pattern 34 is formed only on the cell region A. FIG. In the etching process using the fourth photoresist pattern 34 as a mask, the third polysilicon layer 30a, the dielectric layer 29, and the second layer until the upper end of the sacrificial oxide pattern 26b in the peripheral circuit region B is exposed. The polysilicon layer pattern 27b is sequentially removed, and thus, the upper electrode 30 of the capacitor is formed in the cell region A, and the sacrificial oxide layer pattern 26b remains in the peripheral circuit region B. Since the sacrificial oxide pattern 26b remaining in the peripheral circuit region B acts as a wide-area stepped buffer gun, the cell region A in which the capacitor is formed and the peripheral circuit region B become similar in height to the cell region A ) And the wide area difference generated between the peripheral circuit area (B) is alleviated.

As shown in FIG. 2 (j), after the fourth photoresist pattern 34 is removed, a second insulating planarization film 32 is formed over the cell region A and the entire peripheral circuit region B. As shown in FIG. The second insulating planarization film 32 has a similar height between the cell region A and the peripheral circuit region B, so that the surface of the second insulating planarization film 32 is good. Therefore, deposition, patterning, etching, planarization, and the like for subsequent metal wirings can be facilitated, thereby increasing the reliability and yield of the device.

On the other hand, when the second polysilicon film 27a is formed by etching the second polysilicon film 27a by the polysilicon dry spacer etching process in the process described with reference to FIG. 2 (f), the second polysilicon film 27a ) Is used to form the second lower electrode 27, so that the second polysilicon layer 27a is overetched to generate a wide step between the cell region A and the peripheral circuit region B. Can be eliminated. Due to the excessive etching, the height of the second lower electrode 27 is lowered, which causes a problem of decreasing capacitance. To solve this problem, the sacrificial oxide film 26 is formed in the process of forming the sacrificial oxide film 26 described with reference to FIG. 1C. If the thickness is formed to be thicker than the thickness removed by overetching, the second lower electrode 27 having a desired height may be formed. In other words, it is possible to secure the required capacitance by adjusting the thickness of the sacrificial oxide film 26 and to eliminate the wide area difference between the cell region A and the peripheral circuit region B.

As described above, the present invention provides a wide-area step between the cell region and the peripheral circuit region generated by the height of the capacitor in the cell region without the need for new capacitor structure technology, deposition and etching techniques in the manufacture of DRAM devices using the stacked capacitor structure. It can be removed regardless of the height, it is possible to easily ensure the required capacitance according to the device grade, while facilitating the formation of the metal pattern. Therefore, it is possible to simultaneously reduce capacitance reduction and poor metal pattern formation, and as a result, the yield and reliability of the semiconductor device may be increased, thereby extending the life of the device. In addition, it is possible to develop more integrated devices, which can increase the number of chips in a wafer, thereby increasing productivity.

Claims (4)

Etching the selected region of the first insulating planarization layer to form a first polysilicon layer over the cell region and the peripheral circuit region where the contact hole is formed to be connected to the junction, and removing the first polysilicon layer in the peripheral circuit region to remove the first Forming a sacrificial oxide layer over the entire structure after forming the polysilicon layer pattern, etching selected portions of the sacrificial oxide layer and the first polysilicon pattern to etch a plurality of first lower electrodes and the sacrificial oxide pattern in the cell region; Forming a sacrificial oxide pattern for buffering a wide area step in the peripheral circuit area, forming a second polysilicon film on the cell area and the peripheral circuit area, and then etching the second polysilicon film in the cell area To form a second lower electrode on the sidewalls of the sacrificial oxide pattern of the cell region, and Forming a second polysilicon film pattern on an upper turn, removing a sacrificial oxide film pattern of the cell region to form a lower electrode of a capacitor including the first and second lower electrodes, and a lower electrode of the capacitor And sequentially forming a dielectric film and a third polysilicon film on the entire structure including the third structure, and sequentially removing the third polysilicon film, the dielectric film, and the second polysilicon film pattern on the sacrificial oxide pattern for buffering the wide-area step. Forming an upper electrode of the capacitor in the cell region, and forming a second insulating planarization film over the entire structure including the upper electrode of the capacitor and the sacrificial oxide pattern for buffering the wide step difference. Method of manufacturing the device. The method of claim 1, wherein the first polysilicon layer pattern and the upper electrode are formed by using a reticle for forming an upper electrode of the relief photosensitive film and the capacitor. The method of claim 1, wherein the first lower electrode, the sacrificial oxide film pattern, and the wide-area step buffer sacrificial oxide pattern are formed using a reticle for forming a lower electrode of a relief photosensitive film and a capacitor. . The method of claim 1, wherein the second lower electrode and the second polysilicon layer pattern are formed using a reticle for forming an upper electrode of the negative photoresist layer and the capacitor.

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