KR0179849B1 - Metal interconnector in semiconductor device and method therefor - Google Patents

Abstract

The present invention relates to a wiring structure of a semiconductor device and a method of manufacturing the same, comprising the steps of: forming an insulating film including a lower wiring on a semiconductor substrate on which an arbitrary conductive region is formed; Etching the insulating film to form a connection hole so that the surfaces of the conductive region and the lower wiring are exposed; Forming an auxiliary wiring layer on the insulating film including the connection hole; Etching and planarizing the auxiliary wiring layer; Forming a main wiring layer on the planarized auxiliary wiring layer; Comprising the step of forming the upper wiring by selectively etching the auxiliary wiring layer and the main wiring layer by completing the device manufacturing, 1) effectively reduce the step by using a conductive material to improve the flatness and at the same time The resistance can be lowered, and 2) the photolithography process can be applied while the substrate is flattened to completely eliminate the deterioration of the depth of focus, such as when a step exists, so that the wiring pattern can be accurately formed. Therefore, the reliability of the wiring can be improved.

Description

Wiring structure of semiconductor device and manufacturing method thereof

1 (a) to 1 (g) are process flowcharts showing a wiring manufacturing method of a semiconductor device according to a first embodiment of the present invention.

2 (a) to 2 (g) are process flowcharts showing a wiring manufacturing method of a semiconductor device according to a second embodiment of the present invention.

3 (a) to 3 (g) are process flowcharts showing a wiring manufacturing method of a semiconductor device according to a third embodiment of the present invention.

4 (a) to 4 (g) are process flowcharts showing the wiring manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

1 substrate 2 conductive region

3: lower wiring 4: interlayer insulating film

5 step 6: connection hole

7,7 ': auxiliary wiring layer 8: photosensitive film pattern

9,9 ': Main wiring layer 10: auxiliary pattern

12: upper wiring 14: dummy wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor integrated circuit and a manufacturing method thereof, and more particularly to a wiring structure of a semiconductor device designed for high integration and a manufacturing method thereof.

As the degree of integration of integrated circuits increases, the size of devices decreases and wiring becomes more miniaturized and multilayered. In particular, in memory devices, while the unit memory cell area decreases, a certain capacitor capacity must be secured for discriminating memory information. Therefore, the height of the capacitor storage electrode increases with the adoption of a high dielectric constant dielectric film. I can't help it.

Therefore, in the subsequent process, a step is generated between the memory cell area and other peripheral circuit areas, so that it is difficult to secure a margin of focus in the photolithography process, and also in the vicinity of the substrate having the step. When the pattern is etched, the remaining film of the pattern is formed.

In order to solve this process problem, the research results to date are a planarization method using an insulating film in order to reduce the step difference, using step coating glass (SOG) or high density plasma (HDP), which is an insulating coating film. and planarized by depositing a silicon oxide film having excellent coverage, or by chemical mechanical polishing (hereinafter referred to as CMP).

However, in the case of using a coating insulating film such as SOG, the reliability of the film quality becomes weak due to carbon or moisture contained in the coating film, and when applying HDP deposition or CMP, both of them must be applied at the same time. When polishing, it is difficult to capture the end point of the polishing, so that the thickness of the insulating film is not easily adjusted.

Accordingly, an object of the present invention is to provide a wiring structure of a semiconductor device and a method of manufacturing the same so that the flatness of a device can be improved by effectively reducing a step by using a conductive material. .

The wiring structure of the semiconductor device according to the first embodiment of the present invention for achieving the above object includes a semiconductor substrate having an arbitrary conductive region formed; An insulating film including a lower wiring and formed on the substrate with a step difference; It is characterized by comprising a flattened upper wiring pattern consisting of a laminated structure of the auxiliary pattern / main wiring pattern formed on the insulating film so as to have a thick thickness in the low topology region, and a thin thickness in the high topology region.

The wiring structure of the semiconductor device according to the second and third embodiments of the present invention for achieving the above object includes a semiconductor substrate having an arbitrary conductive region formed; An insulating film including a lower wiring and formed on the substrate with a step difference; The main wiring pattern / auxiliary pattern is stacked on the insulating layer in the low topology region, and the planarized upper wiring formed on the insulating layer in the high topology region has a main wiring pattern structure.

The wiring structure of the semiconductor device according to the fourth embodiment of the present invention for achieving the above object includes a semiconductor substrate having an arbitrary conductive region formed; An insulating film including a lower wiring and formed on the substrate with a step difference; An upper wiring formed of a main wiring pattern formed on an insulating film of a high topology region so as to be connected to the lower wiring; And a dummy wiring formed of a main wiring pattern / auxiliary pattern stacked structure formed on an insulating film in a low topology region.

On the other hand, the method for manufacturing a wiring structure of a semiconductor device according to the first embodiment of the present invention for achieving the above object comprises the steps of forming an insulating film including a lower wiring on a semiconductor substrate formed with an arbitrary conductive region; Etching the insulating film to form a connection hole so that the surfaces of the conductive region and the lower wiring are exposed; Forming an auxiliary wiring layer on the insulating film including the connection hole; Etching and planarizing the auxiliary wiring layer; And forming a top wiring by forming a main wiring layer on the planarized auxiliary wiring layer, and selectively etching the auxiliary wiring layer and the main wiring layer.

According to the second to fourth embodiments of the present invention, there is provided a method of manufacturing a wiring structure of a semiconductor device, the method including forming an insulating film including a lower wiring on a semiconductor substrate on which an arbitrary conductive region is formed; Etching the insulating film to form a connection hole so that the surfaces of the conductive region and the lower wiring are exposed; Forming a main wiring layer on the insulating film including the connection hole and forming an auxiliary wiring layer on the main wiring layer; Selectively etching and etching the auxiliary wiring layer; And etching the main wiring layer and the auxiliary wiring layer using the photoresist pattern as a mask to form the upper wiring.

As a result of the above process, the wiring reliability of the device can be improved.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The present invention focuses on improving the flatness of the device by reducing the step height while increasing the applicability of the process by using a conductive material that can lower the electrical resistance of the wiring.

In other words, the planarity is improved through a structure and a method of selectively forming a thick thickness of a wiring on a substrate having a relatively low topology in a substrate having a step difference compared to a portion having a high topology.

As a method for controlling the thickness of the wiring, there is a method of supplementing the thickness corresponding to the step by selectively depositing a conductive material to form an auxiliary conductive pattern, and another method is to selectively form a laminated film of the conductive material and the insulating material. There is a way to replenish the thickness.

1 and 2 show a wiring structure and a method of manufacturing the same, in which the first and second embodiments of the present invention selectively form a pattern of a conductive material to compensate for the height of the step.

First, as a first embodiment, the process shown in FIGS. 1 (a) to 1 (g) will be described. In the above embodiment, the auxiliary pattern is first formed, and then the process is performed in order of forming the main wiring layer.

First, as shown in FIG. 1 (a), the lower wiring 3 is formed on the insulating film on the silicon substrate 1 on which the conductive region 2 is formed, and the lower wiring and the upper wiring are electrically connected thereon. A silicon oxide film is formed as the interlayer insulating film 4 for insulating. At this time, the height of the stepped portion is denoted by T.

Thereafter, as shown in FIG. 1 (b), the interlayer insulating film 4 is selectively etched to expose the surface of the lower wiring 3 and the conductive region 2 using the photosensitive film pattern as a mask, thereby connecting the connection holes 6. ) And then the photoresist pattern is removed.

Then, sputtering the auxiliary wiring layer 7 made of the first conductive material on the entire surface of the interlayer insulating film 4 including the connection hole 6 to form the auxiliary pattern as shown in FIG. 1 (c). It is formed by a conformal method such as physical vapor deposition using a method such as) or chemical vapor deposition (hereinafter referred to as CVD).

Since the thickness is necessary to improve the flatness, it is determined and applied so as to be equal to or smaller than the step height T.

In this case, as the first conductive material constituting the auxiliary wiring layer 7, a relatively low resistivity metal such as W, Al, Cu, an alloy of the metal, or a semiconductor material such as a metal compound such as TiSi ₂ , WSi _2, or the like is used. do.

In the above embodiment, in the state in which the conductive plug is formed to fill the connection hole after the connection hole is formed, the process may be performed using an insulating material instead of the first conductive material as the auxiliary wiring layer 7 material. Examples of the auxiliary insulating film to be used include a silicon oxide film by the CVD method.

Subsequently, as shown in FIG. 1 (d), the auxiliary wiring layer 7 is etched back and planarized using CMP. As a result, the auxiliary pattern 10 of the type as shown in the figure is formed. At this time, since the interlayer insulating film 4 acts as an etching stopper, there is an advantage that it is easy to capture the end point.

The abrasive used in this process is a slurry containing abrasive particles such as silica and alumina, acids such as H ₃ PO ₄ , H ₂ SO ₄ , AgNO ₃ , and an oxidizing agent such as H ₂ O ₂ , HOCl, and the like.

Subsequently, as shown in FIG. 1 (e), the main wiring layer 9 is deposited by sputtering or CVD using a second conductive material made of a metal such as Al, Cu, or an alloy thereof, and the upper conductive line pattern As shown in FIG. 1 (f), a photoresist pattern 8 is formed on the main wiring layer 9. Forming the photoresist pattern in this way can apply the photolithography process in a state where the engine is planarized, thereby completely avoiding a weakening of the depth of focus as in the case where a step exists.

Next, as shown in FIG. 1 (g), the main wiring layer 9 is etched using the photosensitive film pattern 8 as a mask to form the upper conductive line pattern 12 having a partly thicker thickness, thereby completing the process. do. That is, a wiring structure having a substantially flattened surface is manufactured by using the auxiliary pattern 10.

Next, as a second embodiment, the process shown in FIGS. 2 (a) to 2 (g) will be described. In the above embodiment, the auxiliary pattern 10 is installed to compensate for the step height, and a material having a different etching selectivity from the main wiring layer is used as the auxiliary pattern forming material.

In the drawings, the processes shown in FIGS. 2A and 2B are the same as those shown in FIGS. 1A and 1B, and thus descriptions thereof will be omitted. (c) looks at the process shown in FIG.

That is, as shown in FIG. 2 (c), a physical vapor deposition method using sputtering or the like of a second conductive material on the entire surface of the interlayer insulating film 4 including the connection hole 6 to form a main wiring pattern, or CVD. The main wiring layer 9 is formed by depositing by a conformal vapor deposition method such as the method.

In this case, as the second conductive material, a relatively low resistivity metal such as W, Al, Cu, an alloy of the metal, or a metal compound such as TiSi ₂ , WSi _2, or the like is used.

Subsequently, as shown in FIG. 2 (d), the thickness of Al, Cu metal, or an alloy having a thickness equal to or smaller than T, which is the short wave height, is necessary for improving the flatness on the main wiring layer 9. The first conductive material of is deposited by sputtering or CVD to form the auxiliary wiring layer 7.

In this case, the first conductive material should be subjected to a deposition process by applying a material having a different etching selectivity from a material forming the main wiring layer, in consideration of a process progress that may be caused during the subsequent etching process of the auxiliary wiring gun. do.

For example, when tungsten is applied as the main wiring layer material, for example, a material having different etching selectivity, such as another Al or Cu material or an alloy of the metal, is applied as the auxiliary wiring layer material.

In this case, a process may be performed using an insulating film instead of the first conductive material as the auxiliary wiring layer 7, and the auxiliary insulating material used in this case may be a silicon oxide film by the CVD method.

Next, as shown in FIG. 2 (e), the photoresist pattern 8 is selectively formed only on the auxiliary wiring layer 7 having a relatively low topology, and then the auxiliary wiring layer 7 is etched using the mask. Then, the photosensitive film pattern 8 is removed and planarized, or the first conductive material is etched back using CMP to planarize immediately without forming the photosensitive film pattern 8.

At this time, when planarizing by applying CMP, a slurry containing abrasive particles such as silica and alumina, an acid such as H ₃ PO ₄ , H ₂ SO ₄ , AgNO ₃ , and an oxidizing agent such as H ₂ O ₂ , HOCl, etc. (slurry) is used.

Subsequently, as shown in FIG. 2 (f), the photosensitive film pattern 8 is formed on the main wiring layer 9 and the auxiliary pattern 10 again, and the main wiring layer 9 and the auxiliary layer below the mask are formed using the mask. The process is completed by etching the pattern 10 to form the upper wiring 12 having a shape as shown in FIG. 2 (g).

At this time, in forming the upper wiring 12 using the photosensitive film pattern 8, the auxiliary pattern 10 is composed of a material containing tungsten as a main component, and the main wiring layer 9 is composed of a material containing aluminum as a main component. In this case, the auxiliary pattern 10 performs an etching process using a plasma of a gas containing SF ₆ , whereas when etching the main wiring layer 9, the auxiliary pattern 10 performs an etching process using a plasma of a gas containing Cl ₂ . Do it.

In addition, when the materials of the auxiliary pattern and the main wiring layer are interchanged, for example, when aluminum is used as the auxiliary pattern 10 and tungsten is used as the main wiring layer 9, the etching process may be performed in the reverse order. In the case of an insulating film, the etching process is performed by applying CHF ₃ and CF ₄ .

When the photoresist pattern is formed in the above manner, the photodevelopment process can be applied while the substrate is flattened to completely avoid the deterioration of the depth of focus as in the case where the step is present.

Meanwhile, FIGS. 3 and 4 show the third and fourth embodiments of the present invention, wherein the auxiliary pattern made of an insulating material is used, or the height difference is compensated for by using a laminated film pattern made of a conductive material and an insulating material. How to do it.

First, the process shown in FIGS. 3 (a) to 3 (g) will be described as the third embodiment.

In the drawings, the processes shown in FIGS. 3A and 3B are the same as those shown in FIGS. 1A and 1B, and thus descriptions thereof will be omitted. (c) looks at the process shown in FIG.

That is, as shown in FIG. 3 (c), the second conductive material, which is the main wiring layer 9, is deposited on the entire surface of the interlayer insulating film 4 including the connection hole 6, and as shown in FIG. As described above, an insulating film material is deposited on the main wiring layer 9 as an auxiliary wiring layer 7 'capable of compensating for the height of the step.

At this time, the insulating film material constituting the auxiliary wiring layer 7 'is deposited to have a thickness equal to or smaller than the step T, and a silicon oxide film by the CVD method is used as the auxiliary insulating film material.

Thereafter, as shown in FIG. 3 (e), the auxiliary wiring layer 7 'is etched back by the CMP method. As a result, the auxiliary pattern 10 of the type as shown in the figure is formed. At this time, since the main wiring layer material 9 acts as an etching stopper when the silicon oxide film is etched back, the polishing end point can be more easily set. In applying the CMP method, an alkali solution such as silica and KOH is used as abrasive particles.

Subsequently, a photosensitive film pattern 8 is formed on the planarized main wiring layer 9 and the auxiliary pattern 10 as shown in FIG. 3 (f) through a photolithography process. As such, when the photoresist pattern 8 is formed, the photodevelopment process may be applied while the substrate is flattened during the subsequent process, thereby completely avoiding deterioration of the depth of focus, such as when a step exists.

Subsequently, as shown in FIG. 3 (g), the auxiliary pattern 10 and the main wiring layer 9 are selectively etched using the photoresist pattern 8 as a mask to form the auxiliary pattern 10 and the main wiring layer pattern 9. By forming the upper wiring 12 consisting of, the present process is completed.

Next, as a fourth embodiment, the process shown in FIGS. 4 (a) to 4 (g) will be described. Since the processes shown in FIGS. 4A and 4F are the same as those shown in FIGS. 3A and 3F, the description thereof is omitted here. Look at the process shown in (f).

That is, as shown in FIG. 4 (f), the photoresist pattern 8 is selectively formed on a predetermined portion on the main wiring layer 9 using a photolithography process, and then shown in FIG. 4 (g). As described above, the main wiring layer 9 around the photoresist pattern is etched.

As a result, the conductive material, which is the main wiring layer pattern connected to the lower wiring 3, acts as the upper wiring 12, and the stacked pattern of the auxiliary pattern 10 and the main wiring layer pattern 9 ′ on one side thereof (eg, The insulating layer pattern and the stacked pattern of the conductive material) serve as a dummy wiring 14 irrelevant to the direct wiring.

As described above, according to the present invention, it is possible to effectively reduce the step by using a conductive material to improve the flatness of the device and at the same time lower the electrical resistance of the wiring, and to perform the photo development process while the substrate is flattened. Since it can be applied, the deterioration of the depth of focus such as when there is a step can be completely eliminated, and as a result, the wiring pattern can be accurately formed, thereby improving the reliability of the wiring.

Claims (17)

A semiconductor substrate having an arbitrary conductive region formed thereon; An insulating film including a lower wiring and formed on the substrate with a step difference; A semiconductor device comprising a planarized upper wiring pattern formed of a stacked structure of an auxiliary pattern / main wiring pattern formed on the insulating layer to have a thick thickness in a low topology region and a thin thickness in a high topology region. Wiring structure. The wiring structure of a semiconductor device according to claim 1, wherein the auxiliary pattern is made of any one selected from a conductive material and an insulating material. The wiring structure of claim 1, wherein the main wiring pattern is made of a conductive material. The wiring structure of a semiconductor device according to claim 1, wherein the auxiliary pattern is made of a metal having low resistivity such as W, Al, Cu, an alloy of the metal, or any one selected from TiSi ₂ , WSi ₂ . The semiconductor device wiring structure according to claim 1, wherein the main wiring pattern is made of a metal such as Al, Cu, or an alloy thereof. A semiconductor substrate having an arbitrary conductive region formed thereon, and an insulating film including a lower wiring and formed on the substrate with a step difference; The wiring structure of the semiconductor device comprising a planarized upper wiring formed on the insulating film in the low topology region and having the main wiring pattern / auxiliary pattern stacked on the insulating film in the high topology region. . The wiring structure of claim 6, wherein the main wiring pattern and the auxiliary pattern are made of a material having different etching selectivity when both patterns are made of a conductive material. A semiconductor substrate having an arbitrary conductive region formed thereon; An insulating film formed on the substrate with a step to include a lower wiring; An upper wiring formed of a main wiring pattern formed on an insulating film of a high torsion region to be connected to the lower wiring; A wiring structure of a semiconductor device, comprising a dummy wiring comprising a main wiring pattern / auxiliary pattern stacked structure formed on an insulating film in a familiar topological region. Forming an insulating film including a lower wiring on the semiconductor substrate on which the conductive region is formed; Etching the insulating film to form a connection hole so that the surfaces of the conductive region and the lower wiring are exposed; Forming an auxiliary wiring layer on the insulating film including the connection hole; Etching and planarizing the auxiliary wiring layer; Forming a main wiring layer on the planarized auxiliary wiring layer; And forming a top wiring by selectively etching the auxiliary wiring layer and the main wiring layer. The method of claim 9, wherein the auxiliary wiring layer is formed to a thickness equal to or less than a step generated on the substrate. 10. The method of claim 9, wherein the auxiliary wiring layer is etched back by chemical mechanical polishing. 12. The slurry of claim 11, wherein the auxiliary wiring layer comprises abrasive particles such as silica and alumina, acids such as H ₃ PO ₄ , H ₂ SO ₄ , AgNO ₃ , and an oxidizing agent such as H ₂ O ₂ , HOCl, etc. as an abrasive. Method for manufacturing a wiring structure of a semiconductor device, characterized in that the etched back using. Forming an insulating film including a lower wiring on the semiconductor substrate on which the conductive region is formed; Forming a connection hole by etching the insulating film so that the surfaces of the conductive region and the lower wiring are exposed, forming a main wiring layer on the insulating film including the connection hole, and forming an auxiliary wiring layer on the main wiring layer; Selectively etching and etching the auxiliary wiring layer; And etching the main wiring layer and the auxiliary wiring layer using a photosensitive film pattern as a mask to form upper wirings. The method of claim 13, wherein the selective etching of the auxiliary wiring layer comprises: forming a photoresist pattern on the auxiliary wiring layer having a relatively low topology; And etching the auxiliary wiring layer using the photosensitive film pattern as a mask, and removing the photosensitive film pattern. The method of manufacturing a wiring structure of a semiconductor device according to claim 13, wherein an alkaline solution such as silica and KOH is applied when the auxiliary wiring layer is etched back by chemical mechanical polishing. The method of claim 13, wherein the auxiliary wiring layer is formed of a silicon oxide film. The method of claim 13, further comprising: forming a photoresist pattern on the main wiring layer on the lower wiring after the process of forming the upper wiring by etching the main wiring layer and the auxiliary wiring layer using the photosensitive film pattern as a mask; And etching the auxiliary wiring layer using the photosensitive film pattern as a mask to form a dummy wiring spaced apart from the main wiring layer, the dummy wiring having a laminated structure in which the auxiliary wiring layer is formed on the main wiring layer. Manufacturing method.