KR100334962B1 - Metal wiring formation method of semiconductor device_ - Google Patents
Metal wiring formation method of semiconductor device_ Download PDFInfo
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- KR100334962B1 KR100334962B1 KR1019980063683A KR19980063683A KR100334962B1 KR 100334962 B1 KR100334962 B1 KR 100334962B1 KR 1019980063683 A KR1019980063683 A KR 1019980063683A KR 19980063683 A KR19980063683 A KR 19980063683A KR 100334962 B1 KR100334962 B1 KR 100334962B1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 캐패시터의 플레이트전극 상부에 형성되는 층간절연막 두께를 얇게 형성하고 텅스텐-플러그(W-plug)를 형성하는 동시에 그 상부로 텅스텐-기둥(W-column)을 형성한 다음, 후속공정으로 이에 접속되는 금속배선을 형성함으로써 안정된 특성을 갖는 금속배선을 형성할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, wherein the thickness of an interlayer insulating film formed on the plate electrode of a capacitor is formed thin and a tungsten-plug (W-plug) is formed. After forming the column), a metal wiring connected to it is formed in a subsequent process so that a metal wiring having stable characteristics can be formed, thereby improving the characteristics and reliability of the semiconductor device.
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 복합 반도체(Merged Memory Logic)와 같이 깊으면서도 크기가 작은 금속배선 콘택을 형성할 필요가 있는 모든 반도체칩 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of semiconductor devices, and more particularly, to a method for manufacturing all semiconductor chips in which deep and small metal wiring contacts need to be formed, such as a composite memory logic (Merged Memory Logic).
현행 반도체 산업에서는 각각의 반도체 칩(chip)을 서로 다른 공정을 통해 제조한 후에, 이들을 기판 위에서 전기적으로 연결하여 특정한 기능을 갖는 장치를 만들지만, 가까운 미래에는 서로 다른 기능을 갖는 다양한 칩들을 동시에 동일한 공정을 통해 제조하는 방식으로 변화할 것으로 예상된다.In the current semiconductor industry, each semiconductor chip is manufactured by a different process, and then electrically connected to each other to form a device having a specific function, but in the near future, various chips having different functions may be simultaneously It is expected to change in the way it is manufactured through the process.
특히 DRAM과 로직을 결합한 복합 반도체(Merged Memory Logic)는 이러한 통합 장치(System-On-Chip)의 효시로서, 최근에 각광을 받는 반도체 칩 제조 산업의 한 분야로 부상하고 있다.In particular, integrated memory logic (MDI), which combines DRAM and logic, is the pioneer of such a system-on-chip, and has recently emerged as a part of the semiconductor chip manufacturing industry that is in the spotlight.
일반적으로 DRAM과 로직을 결합한 복합 반도체는, DRAM 셀 (cell) 부위에서 축전기를 형성하기 위해 플레이트전극을 형성하면, DRAM의 셀 부위와 플레이트전극을 형성하지 않는 지역, 예를 들면 DRAM의 센스앰프(Sense Amplifier), 디코더(Decoder), 주변회로부(Perphery) 그리고 로직(Logic) 지역 사이에 상당한 단차가 발생한다.In general, a composite semiconductor in which DRAM and logic are combined, when a plate electrode is formed to form a capacitor in a DRAM cell region, an area in which the cell region and a plate electrode of the DRAM are not formed, for example, a sense amplifier of the DRAM ( Significant steps occur between the Sense Amplifier, Decoder, Periphery, and Logic regions.
이러한 단차를 그대로 둔 상태에서는 로직에 필요한 다층 금속 배선을 제대로 형성할 수 없기 때문에, 결국 플레이트전극 위의 산화막을 평탄화 시켜 주어야 하는데 이러한 평탄한 작업을 진행할 경우는 트랜지스터의 활성영역과 제1금속배선을 연결하는 콘택홀(contact-hole)의 깊이가 커지게 되며, 이로 인해 제조 공정 상의 문제점이 많이 발생하게 된다.In this state, it is not possible to form the multi-layered metal wiring necessary for logic properly. Therefore, it is necessary to flatten the oxide film on the plate electrode. In the case of such a flat work, the active region of the transistor and the first metal wiring are connected. The depth of the contact hole (contact-hole) is increased, which causes a lot of problems in the manufacturing process.
도 1a 내지 도 1i는 종래기술에 따른 반도체소자의 금속배선 형성공정을 도시한 단면도들로서, 복합 반도체를 예로 하여 실시한 것이다.1A to 1I are cross-sectional views illustrating a metal wiring forming process of a semiconductor device according to the prior art, which is performed by using a composite semiconductor as an example.
먼저, 도 1a에 도시된 바와 같이 반도체기판 상부에 활성영역을 정의하는 소자분리막(11)을 형성하고, 상기 활성영역에 워드라인(13)을 형성한 다음, 그 상부를 평탄화시키는 하부절연층(15)을 형성한다. 이때, 상기 하부절연층(15)은 비.피.에스.지.(Boro Phospho Silicate Glass, 이하에서 BPSG 라 함)와 같이 유동성이 우수한 절연물질로 형성한다. 그리고, 상기 반도체기판에 접속되는 비트라인(17)을 형성하고 그 상부를 평탄화시키는 제1층간절연막(19)을 형성한 후에 순차적으로 상기 반도체기판에 접속되는 저장전극(21), 유전체막(23) 및 플레이트전극(25) 적층구조의 캐패시터를 형성한다.First, as shown in FIG. 1A, an isolation layer 11 defining an active region is formed on an upper portion of a semiconductor substrate, a word line 13 is formed on the active region, and then a lower insulating layer is formed to planarize an upper portion thereof. 15). In this case, the lower insulating layer 15 is formed of an insulating material having excellent fluidity, such as B.P.G. (Boro Phospho Silicate Glass, hereinafter referred to as BPSG). After forming the bit line 17 connected to the semiconductor substrate and forming the first interlayer insulating film 19 to planarize the upper portion thereof, the storage electrode 21 and the dielectric film 23 sequentially connected to the semiconductor substrate. And a plate electrode 25 stacked structure.
그 다음, 도 1b 및 도 1c에 도시된 바와 같이 전체표면상부에 제2층간절연막(27)을 형성한다. 이때, 상기 캐패시터가 형성되는 셀부와 그렇지 않은 주변회로부 및 로직부는 높은 단차를 가지게 된다. 후속공정으로 상기 캐패시터가 노출되지않도록 상기 제2층간절연막(27)을 평탄화식각한다.Next, as shown in FIGS. 1B and 1C, a second interlayer insulating film 27 is formed over the entire surface. At this time, the cell portion in which the capacitor is formed and the peripheral circuit portion and logic portion, which are not, have a high step. Subsequently, the second interlayer insulating layer 27 is planarized so as not to expose the capacitor.
그리고, 도 1d에 도시된 바와 같이 상기 반도체기판, 워드라인(13), 비트라인(17) 및 플레이트전극(25)을 노출시키는 콘택홀을 형성하기 위한 감광막패턴(29)을 금속배선 콘택마스크를 이용한 노광 및 현상공정으로 형성한다.As shown in FIG. 1D, the photoresist pattern 29 for forming a contact hole for exposing the semiconductor substrate, the word line 13, the bit line 17, and the plate electrode 25 may include a metal wiring contact mask. It forms by the exposure and image development process used.
그리고, 도 1e에 도시된 바와 같이 상기 감광막패턴(29)을 마스크로하여 상기 상기 반도체기판, 워드라인(13), 비트라인(17) 및 플레이트전극(25)을 노출시키는 콘택홀(37,35,33,31)을 각각 형성한다.1E, contact holes 37 and 35 exposing the semiconductor substrate, the word line 13, the bit line 17, and the plate electrode 25 using the photoresist pattern 29 as a mask. And 33 and 31, respectively.
그 다음, 도 1f에 도시된 바와 같이 상기 콘택홀(37,35,33,31)을 포함한 전체표면상부에 제1 Ti/TiN 적층구조(39)를 형성하고 그 상부에 상기 콘택홀(37,35,33,31)을 매립하는 텅스텐(41)을 형성한다.Next, as shown in FIG. 1F, a first Ti / TiN layer structure 39 is formed on the entire surface including the contact holes 37, 35, 33, and 31, and the contact hole 37, Tungsten 41 for embedding 35, 33, 31 is formed.
그리고, 도 1g에 도시된 바와 같이 상기 제2층간절연막(27)이 노출될때까지 평탄화식각하여 상기 콘택홀(37,35,33,31)을 매립하는 콘택플러그를 텅스텐(41)으로 형성한다. 이때, 상기 평탄화식각공정은 SF6가스를 활성화시킨 플라즈마를 이용하여 전면식각한 것이다.As shown in FIG. 1G, a contact plug for filling the contact holes 37, 35, 33, and 31 is formed of tungsten 41 by planarization etching until the second interlayer insulating layer 27 is exposed. In this case, the planarization etching process is the entire surface etching using the plasma activated the SF 6 gas.
그 다음에, 도 1h에 도시된 바와 같이 전체표면상부에 제2 Ti/TiN 적층구조(43)와 알루미늄합금(45) 및 제3 Ti/TiN 적층구조(47)를 형성한다.Next, as shown in FIG. 1H, the second Ti / TiN laminated structure 43, the aluminum alloy 45, and the third Ti / TiN laminated structure 47 are formed on the entire surface.
그리고, 도 1i에 도시된 바와 같이 제1금속배선 마스크(도시안됨)을 이용한 식각공정으로 상기 제3 Ti/TiN 적층구조(47)와 알루미늄합금(45) 및 제2 Ti/TiN 적층구조(43)를 패터닝함으로써 제1금속배선을 형성한다. 이때, 상기 제1금속배선 마스크를 이용한 식각공정은 Cl2와 BCl3가스를 활성화시킨 플라즈마를 이용하여 실시한 것이다. 여기서, 제1 Ti/TiN 적층구조는 접착층이고, 제2 Ti/TiN 적층구조는 확산장벽층이며, 제3 Ti/TiN 적층구조(47)는 반사방지막으로 사용된 것이다.In addition, as illustrated in FIG. 1I, the third Ti / TiN laminate structure 47, the aluminum alloy 45, and the second Ti / TiN laminate structure 43 may be formed by an etching process using a first metal wiring mask (not shown). ) Is formed to form a first metal wiring. In this case, the etching process using the first metal wiring mask is performed using a plasma activated with Cl 2 and BCl 3 gas. Here, the first Ti / TiN laminated structure is an adhesive layer, the second Ti / TiN laminated structure is a diffusion barrier layer, and the third Ti / TiN laminated structure 47 is used as an antireflection film.
상기한 바와 같이 종래기술에 따른 반도체소자의 금속배선 형성방법은 하기와 같은 문제점이 있다.As described above, the metal wiring forming method of the semiconductor device according to the related art has the following problems.
먼저, 플레이트전극 상부의 층간절연막을 두껍게 증착한 후에 평탄화 시키기 때문에 평탄화가 완료된 후에 형성하는 활성영역 위의 산화막이 두껍게 되며 따라서 플라즈마 식각을 이용하여 콘택홀(contact-hole)을 만들기가 어렵다.First, since the interlayer insulating layer on the plate electrode is thickly deposited and then planarized, the oxide layer on the active region formed after the planarization is thickened, thus making it difficult to form a contact hole using plasma etching.
또한, 식각을 해야 하는 산화막의 두께가 크기 때문에 감광막의 두께도 커야 하며, 이 경우 감광막을 미세하게 패턴닝하는데 문제를 유발한다.In addition, since the thickness of the oxide film to be etched is large, the thickness of the photoresist film must be large, which causes a problem in finely patterning the photoresist film.
그리고, 활성영역, 및 기판 상부에 형성된 도전체와 제1금속배선을 전기적으로 연결하기 위해서 콘택홀 내부에 티타늄/티타늄나이트라이드/텅스텐(Ti/TiN/W) 을 순차적으로 적층하는데 콘택홀이 깊으면서 좁을 경우 그 구멍의 바닥에 이러한 물질들이 제대로 적층하지 못하며 그 결과 콘택-저항(contact-resistance)이 커지는 문제점이 발생한다.Further, in order to electrically connect the active region, the conductor formed on the substrate, and the first metal wiring, titanium / titanium nitride / tungsten (Ti / TiN / W) is sequentially stacked in the contact hole, and the contact hole is deep. When narrow, these materials do not stack properly at the bottom of the hole, resulting in a high contact-resistance.
본 발명의 목적은 상기한 종래기술의 문제점을 해결하기 위하여, 캐패시터의 플레이트전극 상부에 형성되는 층간절연막 두께를 얇게 하고 텅스텐-플러그(W-plug)와 그 바로 위에 텅스텐-기둥(W-column)을 동시에 형성함으로써 콘택공정을 용이하게 실시할 수 있도록 하는 반도체소자의 금속배선 형성방법을 제공하는데 있다.An object of the present invention is to reduce the thickness of the interlayer insulating film formed on the plate electrode of the capacitor to solve the above-mentioned problems of the prior art, the tungsten-plug (W-plug) and the tungsten-column (W-column) immediately above it To provide a method for forming a metal wiring of a semiconductor device to facilitate the contact process by forming a simultaneous at the same time.
도 1a 내지 도 1i는 종래기술에 따른 반도체소자의 금속배선 형성공정을 도시한 단면도들,1A to 1I are cross-sectional views illustrating a metal wiring forming process of a semiconductor device according to the prior art;
도 2a 내지 도 2m는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성공정을 도시한 단면도들.2A to 2M are cross-sectional views illustrating a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11,51 : 소자분리막 13,53 : 워드라인11,51: device isolation layer 13,53: word line
15,55 : 하부절연층 17,57 : 비트라인15,55: lower insulating layer 17,57: bit line
19,59 : 제1층간절연막 21,61 : 저장전극19,59: first interlayer insulating film 21,61: storage electrode
23,63 : 유전체막 25,65 : 플레이트전극23,63 dielectric film 25,65 plate electrode
27,67 : 제2층간절연막 29,69 : 제1감광막패턴27,67: Second interlayer insulating film 29,69: First photosensitive film pattern
31,33,35,37,71,73,75,77 : 금속배선 콘택홀31,33,35,37,71,73,75,77: Metal wiring contact hole
39,79 : 제1 Ti/TiN 적층구조 41,81 : 텅스텐39,79: first Ti / TiN laminated structure 41,81: tungsten
43,83 : 제2 Ti/TiN 적층구조 45,91 : 알루미늄합금43,83: Second Ti / TiN laminated structure 45,91: Aluminum alloy
47,89 : 제3 Ti/TiN 적층구조 85 : 다른 감광막패턴47,89: Third Ti / TiN laminated structure 85: Another photoresist pattern
87 : 제3층간절연막 93 : 제4 Ti/TiN 적층구조87: third interlayer insulating film 93: fourth Ti / TiN laminated structure
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은 단차를 갖는 셀부와 주변회로부 및 로직부에 금속배선을 형성하는 방법에 있어서, 워드라인, 비트라인 및 캐패시터 등의 단위소자가 형성된 반도체기판 상부에 일정두께의 절연막을 형성하는 단계와, 금속배선 콘택마스크를 이용하여 상기 절연막을 식각함으로써 상기 반도체기판을 포함한 단위소자를 노출시키는 콘택홀을 형성하는 단계와, 상기 콘택홀을 매립하는 제1 Ti/TiN 적층구조과 텅스텐을 형성하는 단계와, 상기 텅스텐 상부에 제2 Ti/TiN 적층구조를 형성하는 단계와, 상기 제2 Ti/TiN 적층구조 상부에 음성 감광막을 이용하여 감광막패턴을 형성하되, 상기 금속배선 콘택 마스크를 이용하여 형성하는 단계와, 상기 감광막패턴을 마스크로하여 상기 제2Ti/TiN 적층구조를 식각하고 후속공정으로 상기 텅스텐을 식각함으로써 콘택홀을 매립하는 콘택플러그를 형성하는 동시에 콘택플러그 상측으로 돌출된 텅스텐 기둥을 형성하는 단계와, 전체표면상부에 평탄화절연막을 형성하되, 상기 텅스텐 상부를 노출시키는 단계와, 상기 텅스텐에 접속되는 제3 Ti/TiN 적층구조, 알루미늄합금 및 제4 Ti/TiN 적층구조로 금속배선을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to the present invention is a method of forming a metal wiring in a cell portion, a peripheral circuit portion, and a logic portion having a step, wherein a unit device such as a word line, a bit line, and a capacitor Forming an insulating film having a predetermined thickness on the formed semiconductor substrate, forming a contact hole exposing the unit device including the semiconductor substrate by etching the insulating film using a metal wiring contact mask, and filling the contact hole. Forming a first Ti / TiN stacked structure and tungsten, forming a second Ti / TiN stacked structure on the tungsten, and using a negative photoresist on the second Ti / TiN stacked structure. Forming a metal layer using the metallization contact mask; and forming the second Ti / TiN laminated sphere using the photoresist pattern as a mask. Forming a contact plug to bury the contact hole by etching the tungsten and etching the tungsten in a subsequent process, and simultaneously forming a tungsten column protruding upward from the contact plug, and forming a planarization insulating film on the entire surface, Exposing and forming a metal wiring with a third Ti / TiN laminated structure, an aluminum alloy, and a fourth Ti / TiN laminated structure connected to the tungsten.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2l은 본 발명의 실시예에 따른 반도체소자의 금속배선 형성공정을 도시한 단면도들이다.2A through 2L are cross-sectional views illustrating a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이 반도체기판 상부에 활성영역을 정의하는 소자분리막(51)을 형성하고, 상기 활성영역에 워드라인(53)을 형성한 다음, 그 상부를 평탄화시키는 하부절연층(55)을 형성한다. 이때, 상기 하부절연층(55)은 BPSG와 같이 유동성이 우수한 절연물질로 형성한다. 그리고, 상기 반도체기판에 접속되는 비트라인(57)을 형성하고 그 상부를 평탄화시키는 제1층간절연막(59)을 형성한 후에 순차적으로 상기 반도체기판에 접속되는 저장전극(61), 유전체막(63) 및 플레이트전극(65) 적층구조의 캐패시터를 형성한다.First, as shown in FIG. 2A, a device isolation layer 51 defining an active region is formed on the semiconductor substrate, and a word line 53 is formed on the active region, and then the lower insulating layer is planarized. 55). In this case, the lower insulating layer 55 is formed of an insulating material having excellent fluidity, such as BPSG. After forming the bit line 57 connected to the semiconductor substrate and forming the first interlayer insulating layer 59 to planarize the upper portion thereof, the storage electrode 61 and the dielectric film 63 sequentially connected to the semiconductor substrate. ) And a plate electrode 65 stacked structure.
그 다음, 도 2b에 도시된 바와 같이 전체표면상부에 얇은 산화막으로 제2층간절연막(67)을 형성한다. 그리고 이를 고온에서 가열하여 제2층간절연막(67)의 표면을 매끄럽게 만든다.Then, as shown in Fig. 2B, a second interlayer insulating film 67 is formed of a thin oxide film on the entire surface. Then, it is heated at a high temperature to smooth the surface of the second interlayer insulating film 67.
그리고, 도 2c에 도시된 바와 같이 상기 제2층간절연막(67) 상부에 제1금속배선 콘택홀을 형성할 수 있는 금속배선 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(69)을 형성한다.As illustrated in FIG. 2C, the photoresist pattern 69 may be exposed and developed using a metal wiring contact mask (not shown) capable of forming a first metal wiring contact hole on the second interlayer insulating layer 67. To form.
그리고, 도 2d에 도시된 바와 같이 상기 감광막패턴(69)을 마스크로하여 상기 플레이트전극(65), 비트라인(57), 워드라인(53) 및 반도체기판을 노출시키는 콘택식각공정을 실시함으로써 제1,2,3,4콘택홀(71,73,75,77)을 형성한다.As shown in FIG. 2D, the contact etching process of exposing the plate electrode 65, the bit line 57, the word line 53, and the semiconductor substrate is performed by using the photoresist pattern 69 as a mask. 1,2,3,4 contact holes 71,73,75,77 are formed.
그리고, 도 2e에 도시된 바와 같이 전체표면상부에 제1 Ti/TiN 적층구조(79)와 텅스텐(W)(81)을 전면 증착하여 콘택홀을 채운 후 그 상부에 제2 Ti/TiN 적층구조(83)를 두껍게 증착한다.As shown in FIG. 2E, the first Ti / TiN layered structure 79 and tungsten (W) 81 are deposited on the entire surface to fill contact holes, and the second Ti / TiN layered structure is formed thereon. Thick (83) is deposited.
이때, 상기 제1 Ti/TiN 적층구조는 기존의 공정에서 최적화 시킨 두께를 선택하며, 상기 텅스텐(81) 상부의 제2 Ti/TiN 적층구조(83)는 다음의 공식에 준하여 두께를 결정한다.In this case, the first Ti / TiN laminated structure selects the thickness optimized in the existing process, and the second Ti / TiN laminated structure 83 on the tungsten 81 is determined according to the following formula.
제2 Ti/TiN 적층구조(83)의 두께 = (W의 두께)Thickness of the second Ti / TiN laminated structure 83 = (thickness of W)
x (SF6플라즈마에 대한 TiN의 식각 속도)x (etch rate of TiN for SF 6 plasma)
÷ (SF6플라즈마에 대한 W의 식각 속도)÷ (etch rate of W for SF 6 plasma)
+ (공정 여유를 확보하기 위한 추가 두께)+ (Additional thickness to secure process clearance)
여기서, 기존의 공법에 비해 형성된 콘택홀의 깊이가 작기 때문에 콘택홀 내부에 '티타늄/티타늄나이트라이드/텅스텐' 층이 양호하게 채워지게 된다.Here, since the depth of the contact hole formed is smaller than that of the conventional method, the 'titanium / titanium nitride / tungsten' layer is well filled in the contact hole.
그 다음, 도 2f에 도시된 바와 같이 음성 감광막(negative photo resist)을 증착 시킨 후에 금속배선 콘택마스크를 이용한 노광 및 현상공정으로 다른 감광막패턴(85)을 형성한다. 이때, 상기 다른 감광막패턴(85)은 콘택홀의 크기보다 약간 되, 그 두께는 (상부 Ti/TiN의 두께) × (Cl2+ BCl3플라즈마에 대한 음성 감광막의 식각 속도) ÷ (Cl2+ BCl3플라즈마에 대한 상부 Ti/TiN의 식각속도) + (공정 여유를 확보하기 위한 추가 두께)의 공식으로 계산된 만큼 형성한다.Next, as shown in FIG. 2F, another photoresist pattern 85 is formed by an exposure and development process using a metallization contact mask after depositing a negative photoresist. At this time, the other photoresist pattern 85 is slightly smaller than the size of the contact hole, and the thickness thereof is (thickness of the upper Ti / TiN) × (etch rate of the negative photoresist film with respect to the plasma of Cl 2 + BCl 3 ) ÷ (Cl 2 + BCl 3 Form as calculated by the formula of the etching rate of the upper Ti / TiN to the plasma) + (additional thickness to secure the process margin).
그 다음, 도 2g에 도시된 바와 같이 Cl2+ BCl3를 활성화시킨 플라즈마를 이용하여 상기 제2 Ti/TiN 적층구조(83)를 식각한다.Next, as shown in FIG. 2G, the second Ti / TiN layered structure 83 is etched using a plasma activated with Cl 2 + BCl 3 .
그리고, 도 2h에 도시된 바와 같이 SF6를 활성화시킨 플라즈마를 이용하여 텅스텐(81)을 식각하되, 상기 제2 Ti/TiN 적층구조(83)를 마스크로하고 상기 제1 Ti/TiN 적층구조(79)를 식각장벽으로 하여 실시한다.As shown in FIG. 2H, tungsten 81 is etched using a plasma activated with SF 6 , using the second Ti / TiN layer 83 as a mask, and the first Ti / TiN layer ( 79) is used as an etch barrier.
그 다음, 도 2i에 도시된 바와 같이 Cl2+ BCl3를 활성화시킨 플라즈마를 이용하여 상기 제2 Ti/TiN 적층구조(83)와 제1 Ti/TiN 적층구조(79)를 식각함으로써 상기 텅스텐(81)을 노출시킨다.Next, as illustrated in FIG. 2I, the tungsten (E) is etched by etching the second Ti / TiN stack 83 and the first Ti / TiN stack 79 using a plasma activated with Cl 2 + BCl 3 . 81).
그 다음에, 도 2j 및 도 2k에 도시된 바와 같이 상기 텅스텐(81)을 포함한 전체표면상부를 평탄화시키는 제3층간절연막(87)을 형성하고 상기 텅스텐(81)이 노출될때까지 CMP하여 평탄화시킨다.Next, as shown in FIGS. 2J and 2K, a third interlayer insulating film 87 is formed to planarize the entire upper surface including the tungsten 81, and then planarized by CMP until the tungsten 81 is exposed. .
그리고, 도 2l 및 2m에 도시된 바와 같이 전체표면상부에 제3 Ti/TiN 적층구조(89), 알루미늄합금(91) 및 제4 Ti/TiN 적층구조(93)를 상기 텅스텐(81)에 접속되도록 형성하고, 제1금속배선 마스크(도시안됨)를 이용한 식각공정으로 패터닝하여 금속배선을 형성한다. 이때, 상기 제1금속배선 마스크를 이용한 식각공정은 상기 제4 Ti/TiN 적층구조(93) 상부에 감광막을 도포하고 이를 제1금속배선 마스크를 이용한 노광 및 현상공정으로 패터닝하여 감광막패턴을 형성한 다음, 이를 마스크로하여 상기 제3 Ti/TiN 적층구조(89), 알루미늄합금(91) 및 제4 Ti/TiN 적층구조(93)를 식각하되, Cl2+ BCl3를 활성화시킨 플라즈마로 식각하는 것이다.As shown in FIGS. 2L and 2M, the third Ti / TiN laminated structure 89, the aluminum alloy 91 and the fourth Ti / TiN laminated structure 93 are connected to the tungsten 81 on the entire surface. It is formed so as to form a metal wiring by patterning by an etching process using a first metal wiring mask (not shown). In this case, in the etching process using the first metal wiring mask, a photosensitive film is coated on the fourth Ti / TiN layered structure 93 and patterned by an exposure and developing process using a first metal wiring mask to form a photosensitive film pattern. Next, the third Ti / TiN layered structure 89, the aluminum alloy 91 and the fourth Ti / TiN layered structure 93 are etched using the mask, and the second Ti / TiN layered structure 93 is etched by plasma activated with Cl 2 + BCl 3 . will be.
상기에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 플라즈마식각에 의한 콘택홀 형성시 층간절연막 감소에 따른 식각공정이 용이하고, 콘택홀의 깊이가 작아져 식각이 용이하여 미세 콘택홀을 용이하게 형성할 수 있다. 그리고, 식각해야 하는 층간절연막의 두께가 작기 때문에 감광막의 두께를 낮출 수 있어 동일한 장리로 더 미세한 패턴을 구현할 수 있다. 또한, 콘택홀의 깊문에 콘택홀 내늄/티타늄나이트라이드/텅스텐의 적층구조로 채우기 용이하며 콘택홀 저부에 형성되는 박막의 성질이 양호하여 활성영역과 제1금속배선 사이를 연결하는 콘택의 전기 저항이 줄어든다.As described above, in the method of forming the metal wiring of the semiconductor device according to the present invention, the etching process is easy due to the reduction of the interlayer insulating layer when the contact hole is formed by plasma etching, and the depth of the contact hole is small, so that the etching is easy. Can be easily formed. In addition, since the thickness of the interlayer insulating layer to be etched is small, the thickness of the photoresist layer can be reduced, and thus a finer pattern can be realized with the same length. In addition, it is easy to fill with a stacked structure of contact hole indium / titanium nitride / tungsten at the deep side of the contact hole. Decreases.
그러므로, 반도체소자의 특성 및 신뢰성이 향상되며 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과가 있다.Therefore, the characteristics and reliability of the semiconductor device are improved, and accordingly, there is an effect of enabling high integration of the semiconductor device.
Claims (5)
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| JPH10200065A (en) * | 1996-12-29 | 1998-07-31 | Sony Corp | Semiconductor device and its manufacturing method |
| JPH10256505A (en) * | 1997-03-17 | 1998-09-25 | Sony Corp | Manufacture of dram |
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| US5748521A (en) * | 1996-11-06 | 1998-05-05 | Samsung Electronics Co., Ltd. | Metal plug capacitor structures for integrated circuit devices and related methods |
| JPH10200065A (en) * | 1996-12-29 | 1998-07-31 | Sony Corp | Semiconductor device and its manufacturing method |
| JPH10256186A (en) * | 1997-03-06 | 1998-09-25 | Sony Corp | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100835463B1 (en) * | 2002-06-29 | 2008-06-04 | 주식회사 하이닉스반도체 | A method for forming a metal line of semiconductor device |
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