CN115116944A - Semiconductor structure forming method and semiconductor structure - Google Patents

Abstract

The present disclosure provides a semiconductor structure forming method and a semiconductor structure, and relates to the technical field of semiconductors, wherein the semiconductor structure forming method comprises the following steps: providing a substrate; forming a first dielectric layer on the substrate to cover the surface of the substrate; forming a barrier layer on the surface of the first dielectric layer, and forming a second dielectric layer on the surface of the barrier layer; and sequentially etching the second dielectric layer, the barrier layer and the first dielectric layer based on the patterned mask layer to form a contact hole, wherein the etching rate of the barrier layer is less than that of the second dielectric layer in the etching process. According to the forming method of the semiconductor structure, the problem that the critical dimension of the bottom of the contact hole is enlarged is solved, and therefore the contact hole with the critical dimension which is relatively in accordance with the design requirement is formed.

Description

Semiconductor structure forming method and semiconductor structure

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for forming a semiconductor structure and a semiconductor structure.

Background

Contact hole etching is a critical technique for very large scale integrated circuits, where aspect ratio is one of the important parameters of device structures in semiconductor structures. Many device structures in a semiconductor structure have high aspect ratios, and since the aspect ratios of the device structures are large, the process is complicated, and the etching process and the filling of holes with high aspect ratios have great influence on the yield of the devices. For example, in the opening (open) process of a hole with a high aspect ratio (for example, 12:1 or more), the problem that the bottom cannot be sufficiently etched easily occurs due to the excessively large aspect ratio, so that the bottom opening is insufficient; meanwhile, the bottom over-etching condition is easy to occur, metal bridging (bridge) is easy to form between the metal pads on two sides of the bottom of the contact hole, and the contact plug is caused to form short circuit between the two metal pads, so that the device is failed.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The disclosure provides a semiconductor structure and a forming method thereof.

A first aspect of the present disclosure provides a method of forming a semiconductor structure, the method comprising:

providing a substrate;

forming a first dielectric layer to cover the surface of the substrate;

forming a barrier layer to cover the surface of the first dielectric layer;

forming a second dielectric layer to cover the surface of the barrier layer;

etching the second dielectric layer, the barrier layer and the first dielectric layer in sequence based on the patterned mask layer to form a contact hole;

and in the etching process, the etching rate of the barrier layer is less than that of the second dielectric layer.

In one embodiment of the present disclosure, the thickness of the first dielectric layer is greater than one fifth of the thickness of the second dielectric layer and less than or equal to one half of the thickness of the second dielectric layer.

In one embodiment of the present disclosure, the thickness of the barrier layer ranges from 10nm to 30 nm.

In one embodiment of the present disclosure, forming the second dielectric layer includes:

forming an interlayer dielectric layer on the surface of the barrier layer, and flattening the interlayer dielectric layer;

forming a repairing layer on the surface of the flattened interlayer dielectric layer; the second dielectric layer comprises the interlayer dielectric layer and the repair layer.

In one embodiment of the present disclosure, the substrate includes a plurality of contact pads, the contact pads being located at a target surface of the substrate;

the second dielectric layer, the barrier layer and the first dielectric layer are sequentially etched based on the patterned mask layer to form a contact hole, and the method comprises the following steps:

the mask layer defines a first pattern, the second dielectric layer, the barrier layer and the first dielectric layer are etched in sequence based on the first pattern, a plurality of first contact holes are formed, and each first contact hole exposes the top surface of the contact pad; wherein the contact hole includes a plurality of the first contact holes.

In one embodiment of the present disclosure, the method for forming the semiconductor structure further includes:

and filling a first conductive material in each first contact hole to form a plurality of first contact plugs.

In one embodiment of the present disclosure, the substrate includes a peripheral circuit region where a first contact hole is formed and an active device region disposed adjacent to the peripheral circuit region, and the method of forming a semiconductor structure further includes:

forming the first dielectric layer, the barrier layer, the second dielectric layer and the mask layer on the top surface of the active device area; the mask layer positioned on the top surface of the active device area is provided with a second pattern;

sequentially etching the second dielectric layer, the barrier layer and the first dielectric layer based on the second pattern to form at least one second contact hole, wherein each second contact hole exposes part of the active device region; wherein the contact holes include the first contact hole and the second contact hole.

In one embodiment of the present disclosure, the method for forming the semiconductor structure further includes:

and filling a second conductive material in the second contact hole to form a second contact plug.

A second aspect of the present disclosure provides a semiconductor structure comprising:

a substrate;

the first dielectric layer is positioned on the surface of the substrate;

the barrier layer is positioned on the surface of the first dielectric layer;

the second dielectric layer is positioned on the surface of the barrier layer;

and each contact hole penetrates through the second dielectric layer, the barrier layer and the first dielectric layer.

In one embodiment of the present disclosure, the target surface of the substrate is provided with a plurality of contact pads, and the contact holes include a plurality of first contact holes, each of which penetrates through the second dielectric layer, the barrier layer and the first dielectric layer and exposes a top surface of the contact pad.

In one embodiment of the present disclosure, the semiconductor structure further comprises:

and a first contact plug in the first contact hole, the first contact plug connecting top surfaces of the contact pads.

In one embodiment of the present disclosure, the semiconductor structure further comprises:

a peripheral circuit region disposed on the substrate, the plurality of first contact holes being formed in the peripheral circuit region;

the active device area is arranged on the substrate and is adjacent to the peripheral circuit area, and the first dielectric layer, the barrier layer and the second dielectric layer are sequentially stacked on the top surface of the active device area from bottom to top;

at least one second contact hole penetrating through the second dielectric layer, the barrier layer and the first dielectric layer to expose part of the active device region; wherein the contact holes include the first contact hole and the second contact hole.

In one embodiment of the present disclosure, the semiconductor structure further comprises:

and the second contact plug is positioned in the second contact hole, and the bottom of the second contact plug is connected with the active device area.

In one embodiment of the present disclosure, the second dielectric layer includes:

the interlayer dielectric layer is positioned on the surface of the barrier layer, and the surface of the interlayer dielectric layer above the active device area is flush with the surface of the interlayer dielectric layer above the peripheral circuit area;

and the repairing layer is positioned on the surface of the interlayer dielectric layer.

In one embodiment of the present disclosure, the opening size of the contact hole in the barrier layer is smaller than the opening size of the contact hole in the second dielectric layer.

In the forming method of the semiconductor structure and the semiconductor structure provided by the disclosure, in the etching process, the etching rate of the barrier layer is smaller than that of the second medium layer, so that the barrier layer and the second medium layer have a certain etching selection ratio to reduce the size of the opening formed by the contact hole in the barrier layer, and further adjust the size of the opening of the subsequent contact hole in the first medium layer, thereby solving the problem that the critical dimension of the bottom of the contact hole is enlarged, and forming the contact hole with the critical dimension which is more in line with the design requirement.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. For a person skilled in the art, other figures can be derived from these figures without inventive effort.

Fig. 1 is a schematic diagram of a semiconductor structure in the related art.

Fig. 2 is a schematic diagram of a semiconductor structure in the related art.

FIG. 3 is a flow chart illustrating a method of forming a semiconductor structure according to an exemplary embodiment.

Fig. 4 is a flowchart illustrating a method of forming a semiconductor structure, in accordance with another exemplary embodiment.

Fig. 5 is a schematic diagram illustrating a method of forming a semiconductor structure after forming a substrate and a first dielectric layer in accordance with an exemplary embodiment.

Fig. 6 is a schematic diagram illustrating a method of forming a semiconductor structure after forming a barrier layer according to an example embodiment.

Fig. 7 is a schematic diagram illustrating a method of forming a semiconductor structure after forming a second dielectric layer, according to an example embodiment.

Fig. 8 is a schematic diagram illustrating a method of forming a semiconductor structure after forming a patterned mask layer according to an example embodiment.

Fig. 9 is a schematic view illustrating formation of a first contact hole in a method of forming a semiconductor structure according to an exemplary embodiment.

Fig. 10 is a schematic view illustrating a method of forming a semiconductor structure after forming a first contact plug according to an exemplary embodiment.

FIG. 11 is a flow chart illustrating a method of forming a semiconductor structure in accordance with another exemplary embodiment.

Fig. 12 is a schematic structural view of a substrate provided in a method of forming a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 13 is a schematic diagram illustrating a method of forming a semiconductor structure after forming a first dielectric layer, according to an example embodiment.

Fig. 14 is a schematic diagram illustrating a barrier layer after being formed in a method of forming a semiconductor structure according to an example embodiment.

Fig. 15 is a schematic diagram illustrating a method of forming a semiconductor structure after forming an interlayer dielectric layer according to an example embodiment.

Fig. 16 is a schematic diagram illustrating the formation of a second dielectric layer in a method of forming a semiconductor structure according to an example embodiment.

Fig. 17 is a schematic diagram illustrating a method of forming a semiconductor structure after forming a patterned mask layer according to an example embodiment.

Fig. 18 is a schematic diagram illustrating a method of forming a semiconductor structure after forming a first contact hole and a second contact hole according to an example embodiment.

Fig. 19 is a schematic view illustrating a method of forming a semiconductor structure after forming a first contact plug and a second contact plug according to an exemplary embodiment.

Reference numerals:

10. a substrate; 100. a substrate; 110. a contact pad; 120. a storage structure; 130. a semiconductor layer; 21. a first contact hole; 22. a second contact hole; 200. a first dielectric layer; 30. a metal pad; 300. a barrier layer; 41. a first contact plug; 42. a second contact plug; 400. a second dielectric layer; 410. an interlayer dielectric layer; 420. repairing the layer; 500. a mask layer; 510. a hard mask layer; 520. an anti-reflective coating; 530. a photoresist layer; 540. a first pattern; 550. a second pattern; 600. a contact hole; 610. a first contact hole; 620. a second contact hole; 700. a first contact plug; 800. a second contact plug; A. an active device region; B. a peripheral circuit region.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

As shown in fig. 1, a schematic view of a contact hole in a related art semiconductor structure is illustrated, and as shown in fig. 2, a schematic view of a contact plug in a related art semiconductor structure is illustrated. In the related art, in the process of forming the contact hole with a high aspect ratio, as shown in fig. 1, since the aspect ratio is high, the critical dimension (bottom CD) at the bottom of the first contact hole 21 becomes smaller and smaller as the etching process proceeds, as shown in fig. 1, the first contact hole 21 is under-etched (not-open), so that the first contact hole 21 cannot reach the surface of the substrate 10, and the first contact plug 41 formed subsequently cannot be electrically connected to the metal pad 30. The critical dimension (bottom CD) of the bottom of the second contact hole 22 may also be deviated, such that the critical dimension of the bottom of the second contact hole 22 is too large, and the metal pads 30 located at the left and right sides (referring to the orientation shown in fig. 1) of the second contact hole 22 are exposed, as shown in fig. 2, the second contact plug 42 formed in the subsequent process is prone to form a metal bridge (bridge) between two adjacent metal pads 30, and a short circuit may be formed between the metal pads 30, thereby causing the device to fail.

In order to solve the above technical problem, in an exemplary embodiment of the present disclosure, a method for forming a semiconductor structure and a semiconductor structure are provided, as shown in fig. 3, and fig. 3 shows a flowchart of a method for forming a semiconductor structure provided according to an exemplary embodiment of the present disclosure.

The present embodiment is not limited to the semiconductor structure, and the following description will take the case of forming a contact hole with a high aspect ratio in the semiconductor structure as an example, but the present embodiment is not limited thereto, and the semiconductor structure in the present embodiment may also be other structures. Fig. 5-10 are schematic diagrams of various stages in a method of forming a semiconductor structure, which is described below in conjunction with fig. 5-10.

As shown in fig. 3, an exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure, including the following steps:

step S310: a substrate is provided.

Illustratively, as shown in fig. 5, the substrate 100 serves as a supporting component of the memory for supporting other components disposed thereon, and the substrate 100 may be made of a semiconductor material, which may be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound. For application to large scale digital integrated circuit fabrication, the substrate 100 may be made of silicon material. The substrate 100 may further include a word line (Wordline) and a bit line (Bitline), a plurality of shallow trench isolation structures, and the like (not shown in the drawings), and the substrate 100 may further include a lower interconnect, for example, a lower interconnect in a multi-layer interconnect.

Step S320: and forming a first dielectric layer to cover the surface of the substrate.

As shown in fig. 5, a first dielectric layer 200 may be formed on the surface of the substrate 100 by a deposition process such as chemical vapor deposition, low pressure chemical vapor deposition, physical vapor deposition, etc., and the first dielectric layer 200 covers the surface of the substrate 100. Illustratively, the material of the first dielectric layer 200 may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbonitride. The first dielectric layer 200 may be a single-layer film structure or a multi-layer film composite structure. The thickness H1 of the deposited first dielectric layer 200 can be controlled according to the height of a contact hole formed in a subsequent process or the height of other film layers (based on the orientation shown in the figure), and the thickness H1 of the first dielectric layer 200 can be controlled at a depth position where insufficient etching is likely to occur according to the aspect ratio of the contact hole, so as to improve the problem of insufficient etching in the subsequent process. For example, the thickness H1 of the first dielectric layer 200 is controlled to be in the range of 100nm to 500 nm. Illustratively, the thickness H1 of the first dielectric layer 200 is 200nm, or 300nm, or 500 nm.

Step S330: and forming a barrier layer to cover the surface of the first dielectric layer.

As shown in fig. 6, a barrier layer 300 may be formed on a surface of the first dielectric layer 200, the barrier layer 300 continuously covers the surface of the first dielectric layer 200, and in order to improve the effect of the barrier layer 300 on adjusting the opening of the contact hole on the surface of the first dielectric layer 200 in the process of forming the contact hole subsequently, a material having a density and hardness higher than those of the subsequently formed second dielectric layer may be selected to prepare the barrier layer 300, in an example, the material of the barrier layer 300 is, for example, a nitride, such as silicon nitride.

Step S340: and forming a second dielectric layer to cover the surface of the barrier layer.

As shown in fig. 7, in order to form the high aspect ratio hole, a second dielectric layer 400 is deposited on the surface of the barrier layer 300, and the second dielectric layer 400 continuously covers the surface of the barrier layer 300 to prepare for the subsequent formation of the high aspect ratio hole. Illustratively, the second dielectric layer 400 may be prepared using commonly used oxide materials and deposition processes. The Deposition process may be Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or the like. The material of the second dielectric layer 400 may be the same as the material of the first dielectric layer 200. the material of the second dielectric layer 400 is, for example, an oxide, such as silicon oxide.

As shown in fig. 7, a thickness H3 of the second dielectric layer 400 (based on the orientation shown in the figure) may be deposited according to the height of the finally formed contact hole and/or the thickness of the first dielectric layer 200, and in order to ensure that a contact hole with a high aspect ratio (above 12: 1), for example, a contact hole with an aspect ratio of 18:1, is formed in the subsequent process, a thickness H3 of the deposited second dielectric layer 400 may be controlled, for example, the thickness of the second dielectric layer 400 is controlled within a range of 1000nm to 1500nm, and for example, the thickness H3 of the second dielectric layer 400 is 1000nm, or 1250nm, or 1300nm, or 1400nm, or 1500, and the like, which is not limited herein.

For example, the second dielectric layer may be a single-layer film structure, or may be a multi-layer film composite structure.

Step S350: and sequentially etching the second dielectric layer, the barrier layer and the first dielectric layer based on the patterned mask layer to form a contact hole, wherein the etching rate of the barrier layer is less than that of the second dielectric layer in the etching process.

As shown in fig. 8, a patterned mask layer 500 may be formed on the surface of the second dielectric layer 400 by a conventional spin-coating, exposing, developing, etc. process, where the patterned mask layer 500 has a plurality of openings. The positions defined by the plurality of openings correspond to target positions of contact holes formed subsequently. Illustratively, as shown in fig. 8 and 9, a plasma etching process may be used to sequentially etch the second dielectric layer 400, the barrier layer 300, and the first dielectric layer 200 based on a plurality of openings to form contact holes 600, wherein each contact hole 600 penetrates through the thickness of the second dielectric layer 400, the barrier layer 300, and the first dielectric layer 200, thereby forming a plurality of contact holes with a high aspect ratio on the substrate. Finally, the mask layer 500 is removed.

Illustratively, when the second dielectric layer 400, the barrier layer 300 and the first dielectric layer 200 are sequentially etched, the same etching process, for example, the same plasma concentration, may be used for etching.

As shown in fig. 9, in the selection of the preparation material of the barrier layer 300, a material having a density and hardness higher than those of the second dielectric layer 400 may be selected, so that during the etching process, the etching rate of the barrier layer 300 may be properly lower than that of the second dielectric layer 400, so that during the formation of the contact hole 600, the removal rate of the barrier layer 300 is lower than that of the second dielectric layer 400, thereby naturally reducing the opening dimension D1 of the contact hole 600 formed in the barrier layer 300, further adjusting the opening dimension D2 of the subsequent contact hole in the first dielectric layer 200, so as to limit the size of the bottom critical dimension of the contact hole 600 to meet the design requirement, prevent the bottom dimension of the contact hole from becoming larger, and further effectively prevent the bridging problem of the subsequently formed contact plug.

An exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure, which is the same as the above embodiments in most aspects, and the difference between the embodiment and the above embodiments is that in the method for forming a semiconductor structure, the thickness of the first dielectric layer is greater than one fifth of the thickness of the second dielectric layer, and is less than or equal to one half of the thickness of the second dielectric layer.

In this embodiment, as shown in fig. 7, the relationship between the thickness H1 of the first dielectric layer 200 (in the orientation shown in the figure) and the thickness H3 of the second dielectric layer 400 (in the orientation shown in the figure) can be used to improve or eliminate the problem of insufficient etching of the contact hole in the subsequent process, and the thickness H1 of the deposited first dielectric layer 200 and the thickness H3 of the second dielectric layer 400 can be controlled respectively, so that the thickness H1 of the first dielectric layer 200 is greater than one fifth of the thickness H3 of the second dielectric layer 400 and is less than or equal to one half of the thickness H3 of the second dielectric layer 400, that is, H3 1/5 < H1 ≦ H3 × 1/2.

In this embodiment, the thickness H1 of the first dielectric layer 200 may be deposited according to the thickness H3 of the second dielectric layer 400, the thickness H3 of the second dielectric layer 400 may also be deposited according to the thickness H1 of the first dielectric layer 200, and the relationship between the thicknesses of the two may affect the etching of the contact hole, for example, the thickness H1 of the first dielectric layer 200 is too thin, and a portion of the contact hole formed in the second dielectric layer 400 may be etched insufficiently; if the thickness H1 of the first dielectric layer 200 is too thick, the contact hole formed in the first dielectric layer 200 may be under-etched, so the thickness relationship between the contact hole and the first dielectric layer needs to be controlled to avoid the under-etched problem.

An exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure, which is the same as the above embodiments in most aspects, and is different from the above embodiments in that the thickness of a barrier layer in the method for forming a semiconductor structure can be controlled to be in a range of 10nm to 30 nm.

As shown in fig. 9, the thickness H2 of barrier layer 300 (depending on the orientation shown in the figure) should not be too thick nor too thin. If the thickness H2 of the barrier layer 300 is too thick, the opening dimension D1 of the contact hole 600 formed in the barrier layer 300 is too small, and the opening dimension D2 of the first dielectric layer 200 may be too small, so that the contact hole 600 is under-etched; if the thickness H2 of the barrier layer 300 is too thin, the barrier layer 300 is consumed too quickly in the subsequent process of forming the contact hole 600, so that the purpose of adjusting the opening size D2 of the first dielectric layer 200 cannot be achieved, and the problem that the critical size of the bottom of the contact hole becomes large cannot be solved. Therefore, in the present embodiment, the thickness H2 of the barrier layer 300 may be controlled to be in a range of 10nm to 30nm, and for example, the thickness H2 of the barrier layer 300 may be 10nm, or 15nm, or 18nm, or 30nm, which is not limited herein.

As shown in fig. 4, fig. 4 illustrates a flow chart of a method of forming a semiconductor structure provided according to an exemplary embodiment of the present disclosure. Fig. 5-10 are schematic diagrams of various stages in a method of forming a semiconductor structure, which is described below in conjunction with fig. 5-10.

As shown in fig. 4, an exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure, including the following steps:

step S410: a substrate is provided, the substrate including contact pads, the contact pads being located at a target surface of the substrate.

In this embodiment, as shown in fig. 5, a plurality of contact pads 110 are further disposed on the surface of the substrate 100, and the contact pads 110 may be corresponding contacts of a memory device structure electrically coupled to an active region (not shown) thereunder through the contact pads. Illustratively, the plurality of contact pads 110 are spaced apart, and the contact pads are located on a target surface of the substrate 100, which may be a contact window region of a target structure formed in a subsequent process, for example, a region corresponding to a bottom critical dimension of a contact hole to be formed.

Step S420: a first dielectric layer is formed to cover the substrate and the surface of the contact pad.

As shown in fig. 5, the top surface of the contact pad 110 may be flush with the surface of the substrate 100, and the surface of the substrate 100 may be formed with a first dielectric layer 200 on the surface of the substrate 100 and the top surface of the contact pad 110 through a chemical vapor deposition process, where the process of forming the first dielectric layer 200 is the same as the implementation manner of step S220 in the foregoing embodiment, and is not repeated herein.

Step S430: and forming a barrier layer to cover the surface of the first dielectric layer.

Step S430 of this embodiment is the same as the step S330 of the above embodiment, and is not described herein again.

Step S440: and forming a second dielectric layer to cover the surface of the barrier layer.

As shown in fig. 7, the second dielectric layer 400 is, for example, a multilayer film structure, and may include an interlayer dielectric layer 410 and a repair layer 420, where the interlayer dielectric layer 410 may be deposited to a predetermined thickness, and the thickness of the interlayer dielectric layer 410 is, for example, 1000 nm. The surface of the interlayer dielectric layer 410 may be uneven, and the surface of the interlayer dielectric layer 410 may be removed by planarization operations such as chemical mechanical polishing or mechanical polishing, so as to improve the flatness of the surface of the interlayer dielectric layer 410; and, a repair layer 420 is deposited on the planarized surface of the interlayer dielectric layer 410 to repair scratches on the surface of the interlayer dielectric layer 410 caused by the previous process. Illustratively, the repair layer 420 may have a thickness of, for example, 350 nm.

Step S450: the mask layer defines a first pattern, the second dielectric layer, the barrier layer and the first dielectric layer are sequentially etched based on the first pattern, a plurality of first contact holes are formed, and each first contact hole exposes the target surface of the substrate; wherein the contact hole includes a plurality of first contact holes.

As shown in fig. 8, the step of forming the patterned mask layer 500 is as follows: a hard mask layer 510 with a certain thickness may be formed on the surface of the repair layer 420, and then an anti-reflective coating 520 may be coated on the surface of the hard mask layer 510 to increase the lithography effect; next, a photoresist layer 530 is formed on the surface of the anti-reflective coating 520 by a spin coating process; then, a plurality of openings are formed in the photoresist layer 530 by using processes such as exposure and development to form a first pattern 540, wherein the patterned mask layer 500 is formed by a hard mask layer 510, an anti-reflection coating 520, the photoresist layer 530 and the first pattern 540, and as shown in fig. 8 and 9, the repair layer 420, the interlayer dielectric layer 410, the barrier layer 300 and the first dielectric layer 200 are sequentially etched along the first pattern 540 to expose the top surface of the contact pad 110 on the target surface of the substrate 100, so that a plurality of first contact holes 610 are formed on the substrate 100, wherein the contact holes 600 include a plurality of first contact holes 610, and each first contact hole 610 exposes a part of or all the top surface of the contact pad 110. Then, the mask layer 500 is removed.

As shown in fig. 9, the opening size of the first contact hole 610 at the bottom of the second dielectric layer 400 is denoted as D3, the opening size of the first contact hole 610 in the barrier layer 300 is denoted as D1, and the removal rate of the barrier layer 300 is smaller than that of the second dielectric layer 400 during the process of etching the first contact hole 610, so that in the etching process, as the etching process proceeds, the first contact hole 610 naturally forms an opening smaller than the opening size D3 in the barrier layer 300.

As shown in fig. 9, the opening of the first contact hole 610 in the barrier layer 300 has an inclined sidewall, so that the bottom critical dimension of the first contact hole 610 in the second dielectric layer 400 is reduced, the etching is continued along the opening in the barrier layer 300, and the opening (i.e., opening dimension D2) formed by the first contact hole 610 on the surface of the first dielectric layer 200 is reduced, so that the opening dimension D2 is smaller than the opening dimension D1, thereby controlling the critical dimension of the bottom of the finally formed first contact hole 610, and solving the problem that the bottom critical dimension of the contact hole becomes large.

In this embodiment, as shown in fig. 9, in the process of forming the first contact hole 610, the size of the opening formed on the surface of the first dielectric layer 200 by the first contact hole 610 is reduced by using the barrier layer 300, so as to prevent the bottom size of the contact hole formed subsequently from being too large, thereby effectively preventing the contact plug formed subsequently from having a bridging problem.

Step S460: and filling a first conductive material in each first contact hole to form a plurality of first contact plugs.

In this step, as shown in fig. 9 and 10, a first conductive material may be deposited in the first contact hole 610 by chemical vapor deposition or other suitable deposition method until the first contact hole 610 is filled. In one example, the first conductive material is a metal material, such as metal tungsten, titanium nitride, titanium, and the like. Subsequently, a planarization operation, such as a chemical mechanical polishing or a mechanical polishing, may be performed to remove the excess first conductive material, thereby forming a first contact plug 700 flush with the top of the first contact hole 610, as shown in fig. 9 and 10, the first contact plug 700 is formed in each of the plurality of first contact holes 610, the first contact plug 700 having a high aspect ratio is formed due to the high aspect ratio of the first contact hole 610, and the first contact plug 700 is connected to the contact pad 110, and may be used to connect to the source and drain regions and the gate of the transistor.

As shown in fig. 11, fig. 11 illustrates a flow chart of a method of forming a semiconductor structure provided in accordance with another exemplary embodiment of the present disclosure. Fig. 12-19 are schematic diagrams of various stages in a method of forming a semiconductor structure, which is described below in conjunction with fig. 12-19.

As shown in fig. 11, the method of forming a semiconductor structure may include the steps of:

step S510: a substrate is provided, the substrate is provided with a peripheral circuit area and an active device area arranged adjacent to the peripheral circuit area.

As shown in fig. 12, the substrate 100 may be divided into an active device area a and a peripheral circuit area B, wherein the active device area a may be used for storing data, the peripheral circuit area B is used for controlling input and output of the stored data, the active device area a is located in an adjacent area beside the peripheral circuit area B, and the active device area a and the peripheral circuit area B are connected to form an electrical interconnection.

In this embodiment, as shown in fig. 12, the active device region a includes a memory structure 120 on the substrate 100, and a semiconductor layer 130 on a surface of the memory structure 120, while the plurality of contact pads 110 are disposed in the peripheral circuit region B. As shown in fig. 12, the semiconductor layer 130 may entirely cover the surface of the memory structures 120 and fill the gaps between the memory structures 120, and the memory structures 120 may be, for example, a capacitor structure, where the capacitor structure includes a lower electrode, a dielectric, and an upper electrode structure. The material of the semiconductor layer 130 includes, for example, a semiconductor material such as polysilicon or silicon germanium. In one example, the upper electrode of the capacitor structure may be extended upward to form a semiconductor layer.

Step S520: a first dielectric layer is formed on a top surface of the peripheral circuit region and a top surface of the peripheral circuit region.

As shown in fig. 13, a first dielectric layer 200 is formed on the entire surface of the substrate 100, the first dielectric layer 200 covering the surface of the semiconductor layer 130 of the active device region a, the side surface of the semiconductor layer 130, and the top surface of the peripheral circuit region B, and the first dielectric layer 200 also covering the top surface of the contact pad 110. The first dielectric layer 200 may be formed to the same or different thickness on the top surface of the active device region a and the top surface of the peripheral circuit region B. For example, referring to fig. 13, the thickness of the first dielectric layer 200 overlying the active device region a is less than or equal to the thickness of the first dielectric layer 200 overlying the peripheral circuit region B.

Step S530: and forming a barrier layer covering the surfaces of the first dielectric layers on the top surfaces of the active device area and the peripheral circuit area.

As shown in fig. 14, the barrier layer 300 continuously covers the surface of the first dielectric layer 200 on the top surface of the active device region a and the side surfaces of the active device region a, and also covers the surface of the first dielectric layer 200 on the peripheral circuit region B, so as to reduce the size of the opening formed on the surface of the first dielectric layer 200 by the contact hole in the subsequent process.

Step S540: and forming a second dielectric layer covering the top surfaces of the active device area and the barrier layer on the top surface of the peripheral circuit area.

As shown in fig. 15, an interlayer dielectric layer 410 may be deposited on the surface of the barrier layer 300, the interlayer dielectric layer 410 covers the surface of the barrier layer 300 on the top surface of the active device region a, the interlayer dielectric layer 410 also covers the surface of the barrier layer 300 in the peripheral circuit region B and extends upward to a predetermined thickness, and the thickness of the interlayer dielectric layer 410 deposited on the peripheral circuit region B is greater than the thickness of the interlayer dielectric layer 410 on the active device region a. In an example, the thickness of the interlayer dielectric layer on the peripheral circuit region B is in a range of 1000 to 1500nm, and for example, the thickness of the interlayer dielectric layer on the peripheral circuit region B is 1000nm, or 1200nm, or 1300nm, or 1500nm, which is not limited herein. The material of the interlayer dielectric layer is, for example, oxide.

As shown in fig. 15, the surface of the interlayer dielectric layer 410 in the peripheral circuit region B and the surface of the interlayer dielectric layer 410 in the active device region a may have a rugged phenomenon, then, the interlayer dielectric layer 410 may be planarized by Chemical Mechanical Polishing (CMP) so that the surface of the interlayer dielectric layer 410 in the peripheral circuit region B is flush with the surface of the interlayer dielectric layer 410 in the active device region a, as shown in fig. 16, and then, a repair layer 420 is deposited on the surface of the planarized interlayer dielectric layer 410 to repair and eliminate scratches on the surface of the interlayer dielectric layer 410 caused by the previous CMP process, so that the interlayer dielectric layer 410 and the repair layer 420 together form the second dielectric layer 400.

In an example, the material of the repair layer is, for example, an oxide, the thickness of the repair layer is, for example, 300 to 400nm, and the thickness of the repair layer is, for example, 300nm, or 350nm, or 400nm, which is not particularly limited herein.

Step S550: and forming a patterned mask layer covering the surfaces of the barrier layers on the active device area and the peripheral circuit area, wherein the mask layer defines a first pattern and a second pattern.

As shown in fig. 17, a patterned mask layer 500 may be simultaneously formed on the top surface of the active device region a and the top surface of the peripheral circuit region B, that is, on the repair layer 420 on the peripheral circuit region B and the active device region a, the patterned mask layer 500 being composed of a hard mask layer 510, an anti-reflective coating layer 520, a photoresist layer 530, a first pattern 540, and a second pattern 550. Wherein the first pattern 540 is on the top surface of the peripheral circuit region B, and the second pattern 550 is on the top surface of the active device region a. The first pattern 540 and the second pattern 550 are both a plurality of openings, and are not particularly limited herein. Illustratively, as shown in fig. 17, the first pattern 540 is illustratively shown to have three openings, and the second pattern 550 has one opening, so as to form contact holes on the active device region a and the peripheral circuit region B, respectively, in the subsequent process.

Step S560: a plurality of first contact holes are formed on the peripheral circuit region based on the first pattern, and at least one second contact hole is formed on the active device region based on the second pattern, the contact holes including the first contact hole and the second contact hole.

Referring to fig. 17 and 18, the repair layer 420, the interlayer dielectric layer 410, the barrier layer 300, and the first dielectric layer 200 are sequentially etched from top to bottom based on the first pattern 540 over the peripheral circuit region B until the top surface of the contact pad 110 is exposed, so that a plurality of first contact holes 610 with a high aspect ratio are formed in the peripheral circuit region B, and each first contact hole 610 exposes the top surface of the contact pad 110. While the first contact hole 610 is etched, the repair layer 420, the interlayer dielectric layer 410, the barrier layer 300 and the first dielectric layer 200 are sequentially etched from top to bottom based on the second pattern 550, and a portion of the semiconductor layer 130 of the active device region a is exposed, so that a second contact hole 620 is formed in the active device region a. Then, the mask layer 500 on the active device region a and the peripheral circuit region B is removed. The contact hole 600 includes a first contact hole 610 and a second contact hole 620. In the step, a plurality of contact holes can be synchronously formed on the active device area A and the peripheral circuit area B respectively, so that the manufacturing process steps and the time cost of the semiconductor structure are saved.

Step S570: and filling a first conductive material in each first contact hole to form a plurality of first contact plugs, and filling a second conductive material in each second contact hole to form a second contact plug.

As shown in fig. 18 and 19, after removing the mask layer, a first conductive material may be filled in the plurality of first contact holes 610 through a deposition process to form a plurality of first contact plugs 700 on the peripheral circuit region B, and the first contact plugs 700 are connected to the contact pads 110. And simultaneously, the second contact hole 620 located on the active device region a is filled with a second conductive material to form a second contact plug 800, and the second contact plug 800 is connected with the active device to form an electrical interconnection with other structures in a subsequent process. The first conductive material and the second conductive material may be the same metal material, for example, the first conductive material and the second conductive material are both metal tungsten.

As shown in fig. 9, an exemplary embodiment of the present disclosure provides a semiconductor structure, which includes:

a substrate 100;

a first dielectric layer 200 on the surface of the substrate 100;

the barrier layer 300 is positioned on the surface of the first dielectric layer 200;

a second dielectric layer 400 on the surface of the barrier layer 300;

and a plurality of contact holes 600, wherein each contact hole 600 penetrates through the second dielectric layer, the barrier layer and the first dielectric layer.

In an exemplary embodiment, as shown in fig. 9, a plurality of contact pads 110 are disposed on a surface of the substrate, and the contact holes 600 include a plurality of first contact holes 610, each of the first contact holes 610 penetrating the second dielectric layer 400, the barrier layer 300, and the first dielectric layer 200 exposing top surfaces of the contact pads 110 of the substrate 100. Illustratively, the first contact hole 610 exposes a portion of the top surface or the entire top surface of the contact pad 110.

As shown in fig. 10, an exemplary embodiment of the present disclosure provides a semiconductor structure, which has the same contents as the above embodiments in most parts, and the difference between the embodiment and the above embodiments is that the semiconductor structure further includes: the first contact plug 700. As shown in fig. 9 and 10, the first contact plug 700 is positioned in the first contact hole 610, and the first contact plug 700 is connected to the top surface of the contact pad 110.

As shown in fig. 18, an exemplary embodiment of the present disclosure provides a semiconductor structure, most of the contents of the semiconductor structure of this embodiment are the same as those of the above embodiment, and the difference between this embodiment and the above embodiment is that the semiconductor structure further includes: a peripheral circuit region B disposed on the substrate 100, wherein a plurality of first contact holes 610 are formed in the peripheral circuit region B; an active device area A is further arranged on the substrate 100 at a position adjacent to the peripheral circuit area B, and a first dielectric layer 200, a barrier layer 300 and a second dielectric layer 400 are sequentially stacked from bottom to top on the top surface of the active device area A; at least one second contact hole 620 is formed on the active device region a, the second contact hole 620 penetrates through the second dielectric layer 400, the barrier layer 300 and the first dielectric layer 200, exposing a portion of the active device region a, and the contact hole 600 includes a plurality of first contact holes 610 and at least one second contact hole 620.

As shown in fig. 19, an exemplary embodiment of the present disclosure provides a semiconductor structure, which has the same contents as the above embodiments, and the difference between the above embodiments is that the semiconductor structure further includes: and a second contact plug 800. As shown in fig. 18 and 19, a second contact plug 800 is located in the second contact hole 620, and the bottom of the second contact plug 800 is connected to the active device on the active device region a to form an electrical interconnection with other structures in a subsequent process.

In an exemplary embodiment, as shown in fig. 18, the second dielectric layer 400 includes an interlayer dielectric layer 410 and a repair layer 420: wherein the interlayer dielectric layer 410 is located on the surface of the barrier layer 300. As shown in fig. 18, the surface of the interlayer dielectric layer 410 located above the active device region a is flush with the surface of the interlayer dielectric layer 410 located above the peripheral circuit region B. A repair layer 420 is disposed on the surface of the interlayer dielectric layer 410 to improve the flatness of the surface of the second dielectric layer 400.

In an exemplary embodiment, as shown in fig. 9, the opening size of the contact hole 600 in the barrier layer 300 is smaller than the opening size of the contact hole 600 in the second dielectric layer 400. Referring to fig. 9, the opening size of contact hole 600 in barrier layer 300 is D1, the opening size of contact hole 600 in second dielectric layer 400 is D3, and D1 is smaller than D3, so that the size of the critical dimension of the bottom of finally formed contact hole 600 is controlled, the problem that the critical dimension of the bottom of the contact hole becomes large is solved, and the bridging problem of subsequently formed contact plugs is effectively prevented.

The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

In the description herein, references to the terms "embodiment," "exemplary embodiment," "some embodiments," "illustrative embodiments," "example" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing and simplifying the present disclosure, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like as used in this disclosure may be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

Like elements in one or more of the drawings are represented by like reference numerals. For purposes of clarity, the various features in the drawings are not drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Numerous specific details of the present disclosure, such as structure, materials, dimensions, processing techniques and techniques of the devices, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; while the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims (15)

1. A method for forming a semiconductor structure, the method comprising:

providing a substrate;

forming a first dielectric layer to cover the surface of the substrate;

forming a barrier layer to cover the surface of the first dielectric layer;

forming a second dielectric layer to cover the surface of the barrier layer;

etching the second dielectric layer, the barrier layer and the first dielectric layer in sequence based on the patterned mask layer to form a contact hole;

and in the etching process, the etching rate of the barrier layer is less than that of the second dielectric layer.

2. The method of claim 1, wherein the thickness of the first dielectric layer is greater than one fifth of the thickness of the second dielectric layer and less than or equal to one half of the thickness of the second dielectric layer.

3. The method of claim 1 or 2, wherein the barrier layer has a thickness in a range of 10nm to 30 nm.

4. The method of claim 1, wherein forming the second dielectric layer comprises:

forming an interlayer dielectric layer on the surface of the barrier layer, and flattening the interlayer dielectric layer;

forming a repairing layer on the surface of the flattened interlayer dielectric layer; the second dielectric layer comprises the interlayer dielectric layer and the repair layer.

5. The method of claim 1, wherein the substrate comprises a plurality of contact pads, the contact pads being located at a target surface of the substrate;

the second dielectric layer, the barrier layer and the first dielectric layer are sequentially etched based on the patterned mask layer to form a contact hole, and the method comprises the following steps:

the mask layer defines a first pattern, the second dielectric layer, the barrier layer and the first dielectric layer are sequentially etched based on the first pattern, a plurality of first contact holes are formed, and each first contact hole exposes the top surface of the contact pad; wherein the contact hole includes a plurality of the first contact holes.

6. The method of claim 5, further comprising:

and filling a first conductive material in each first contact hole to form a plurality of first contact plugs.

7. The method of claim 1, wherein the substrate includes a peripheral circuit region where the first contact hole is formed and an active device region disposed adjacent to the peripheral circuit region, the method further comprising:

forming the first dielectric layer, the barrier layer, the second dielectric layer and the mask layer on the top surface of the active device area; the mask layer positioned on the top surface of the active device area is provided with a second pattern;

sequentially etching the second dielectric layer, the barrier layer and the first dielectric layer based on the second pattern to form at least one second contact hole, wherein each second contact hole exposes part of the active device region; wherein the contact holes include the first contact hole and the second contact hole.

8. The method of claim 7, further comprising:

and filling a second conductive material in the second contact hole to form a second contact plug.

9. A semiconductor structure, comprising:

a substrate;

the first dielectric layer is positioned on the surface of the substrate;

the barrier layer is positioned on the surface of the first dielectric layer;

the second dielectric layer is positioned on the surface of the barrier layer;

and each contact hole penetrates through the second dielectric layer, the barrier layer and the first dielectric layer.

10. The semiconductor structure of claim 9, wherein the target surface of the substrate is provided with a plurality of contact pads, the contact holes comprising a plurality of first contact holes, each of the first contact holes penetrating the second dielectric layer, the barrier layer, and the first dielectric layer, exposing a top surface of the contact pad.

11. The semiconductor structure of claim 10, further comprising:

and a first contact plug in the first contact hole, the first contact plug connecting top surfaces of the contact pads.

12. The semiconductor structure of claim 10, further comprising:

a peripheral circuit region disposed on the substrate, the plurality of first contact holes being formed in the peripheral circuit region;

the active device area is arranged on the substrate and is adjacent to the peripheral circuit area, and the first dielectric layer, the barrier layer and the second dielectric layer are sequentially stacked on the top surface of the active device area from bottom to top;

at least one second contact hole penetrating through the second dielectric layer, the barrier layer and the first dielectric layer to expose part of the active device region;

wherein the contact holes include the first contact hole and the second contact hole.

13. The semiconductor structure of claim 12, further comprising:

and the second contact plug is positioned in the second contact hole, and the bottom of the second contact plug is connected with the active device area.

14. The semiconductor structure of claim 13, wherein the second dielectric layer comprises:

the interlayer dielectric layer is positioned on the surface of the barrier layer, and the surface of the interlayer dielectric layer above the active device area is flush with the surface of the interlayer dielectric layer above the peripheral circuit area;

and the repairing layer is positioned on the surface of the interlayer dielectric layer.

15. The semiconductor structure of claim 9, wherein an opening size of the contact hole in the barrier layer is smaller than an opening size of the contact hole in the second dielectric layer.

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