KR100327580B1 - Method for forming metal line of a semiconductor device - Google Patents
Method for forming metal line of a semiconductor device Download PDFInfo
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- KR100327580B1 KR100327580B1 KR1019990025522A KR19990025522A KR100327580B1 KR 100327580 B1 KR100327580 B1 KR 100327580B1 KR 1019990025522 A KR1019990025522 A KR 1019990025522A KR 19990025522 A KR19990025522 A KR 19990025522A KR 100327580 B1 KR100327580 B1 KR 100327580B1
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- Prior art keywords
- titanium
- tungsten
- etching
- titanium nitride
- metal wiring
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 56
- 239000002184 metal Substances 0.000 title claims abstract description 56
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000010936 titanium Substances 0.000 claims abstract description 71
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 64
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 62
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 53
- 239000010937 tungsten Substances 0.000 claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 43
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 27
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 27
- 230000000694 effects Effects 0.000 claims abstract description 8
- 238000001465 metallisation Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 239000010408 film Substances 0.000 description 38
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XOUPWBJVJFQSLK-UHFFFAOYSA-J titanium(4+);tetranitrite Chemical compound [Ti+4].[O-]N=O.[O-]N=O.[O-]N=O.[O-]N=O XOUPWBJVJFQSLK-UHFFFAOYSA-J 0.000 description 2
- 239000003082 abrasive agent Substances 0.000 description 1
- JYJXGCDOQVBMQY-UHFFFAOYSA-N aluminum tungsten Chemical compound [Al].[W] JYJXGCDOQVBMQY-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 하부 금속배선을 노출시키는 비아콘택홀이 구비되는 하부산화막을 형성하고 상기 비아콘택홀 표면에 제1 티타늄/티타늄나이트라이드를 형성하고 상기 비아콘택홀을 매립하는 텅스텐을 매립한 다음, 상기 텅스텐을 일정두께 식각하여 평탄화시키되, 상기 하부산화막 상측에 상기 텅스텐을 일정두께 남기고 상기 텅스텐 상부에 제2 티타늄/티타늄나이트라이드, 알루미늄 및 제3 티타늄/티타늄나이트라이드 적층구조를 형성한 다음, 후속공정으로 상기 적층구조와 텅스텐의 식각선택비 차이를 이용하여 상기 적층구조를 상부 금속배선 마스크를 이용해 Cl2+ BCl3를활성화시킨 플라즈마, SF6를 활성화시킨 플라즈마 및 Cl2+ BCl3를활성화시킨 플라즈마로 식각함으로써 마이크로-로딩 효과를 최소화시키며 상기 하부금속배선에 접속되는 상부 금속배선을 형성하는 공정으로 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal interconnection of a semiconductor device, to form a lower oxide film having a via contact hole exposing a lower metal interconnection, and to form a first titanium / titanium nitride on the via contact hole surface and the via contact After filling the tungsten to fill the hole, the planarized by etching the tungsten to a certain thickness, leaving the tungsten on the upper side of the lower oxide layer, and the second titanium / titanium nitride, aluminum and the third titanium / titanium on the tungsten After forming the nitride stacked structure, a plasma, SF 6 activated with Cl 2 + BCl 3 using the upper metal wiring mask by using the upper metal wiring mask by using the difference in the etching selectivity between the laminated structure and tungsten in a subsequent process. Micro-loading effects are maximized by etching with plasma and plasma activated with Cl 2 + BCl 3 It is a technology that enables high integration of semiconductor devices in a process of forming an upper metal wiring connected to the lower metal wiring by extinguishing.
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 반도체 칩 (chip) 제조시, 금속 배선의 선폭(linewidth) 이나 금속 배선간의 간격(space)은 작으면서 금속 배선의 높이는 큰 고집적도의 금속 배선을 형성하기 위해 알루미늄 식각을 진행할 때 발생하는 식각율 마이크로-로딩 현상을 개선하는데 응용될 수 있다. 또한 텅스텐 평탄화 공정을 화학적-기계적-연마(CMP : chemical mechanical polishing)방식으로 진행할 때, 비아 홀(via hole) 내부에 형성되어 있는 비아콘택 플러그가 세정 공정(cleaning process)에서 손상되는 현상을 방지하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices. In particular, in the manufacture of semiconductor chips, high-density metals having a small linewidth or space between metal wirings and high metal wirings It can be applied to improve the etch rate micro-loading phenomenon that occurs when the aluminum etching to form a wiring. In addition, when the tungsten planarization process is performed by chemical mechanical polishing (CMP), the via contact plug formed in the via hole is prevented from being damaged during the cleaning process. It's about technology.
반도체 칩(chip)의 집적도가 높아질수록 금속 배선의 선폭(linewidth) 이나 간격(space)은 작아지는 반면 금속 배선의 높이는 커진다.As the degree of integration of semiconductor chips increases, the linewidth or space of the metal wires becomes smaller while the height of the metal wires increases.
이러한 금속 배선을 형성하기위해 플라즈마(plasma) 식각을 진행하면, 금속배선 간의 간격이 넓은 지역에 비해 금속 배선 간의 간격이 넓은 지역에 비해 금속 배선 간의 간격이 좁은 지역의 알루미늄 식각이 늦게 이루어지는 식각율 마이크로-로딩(etch rate micro-loading)현상이 발생한다.When plasma etching is performed to form such a metal interconnection, an etching rate micro is formed in which the aluminum etching is delayed in the region where the metal interconnection is narrower than the region where the metal interconnection is wider than the region where the metal interconnection is wider. Etch rate micro-loading occurs.
현행 반도체 칩 제조에 일반적으로 채용되고 있는 기존의 공정 방식은 이러한 식각율 마이크로-로딩 현상이 심하게 발생하여 후속공정에 여러 가지 악 영향을 끼치는데, 그 공정 방식을 설명하면 다음과 같다Existing process methods generally employed in the manufacture of current semiconductor chips have such an etch rate micro-loading phenomenon, which adversely affects subsequent processes. The process methods are as follows.
도 1a 내지 도 1h 는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1A to 1H are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.
도 1a를 참조하면, 제1금속배선(도시안됨)을 형성하고 그 상부에 하부 산화막(11)을 평탄화시킨 후, 비아콘택마스크(도시안됨)를 이용한 식각공정으로 비아 홀(13)을 형성한다.Referring to FIG. 1A, after forming the first metal wiring (not shown) and planarizing the lower oxide layer 11 thereon, the via hole 13 is formed by an etching process using a via contact mask (not shown). .
도 1b를 참조하면, 전체표면상부에 제1 티타늄/티타늄나이트라이드 (Ti/TiN)(15)을 얇게 전면 증착 시킨다. 상기 제1 티티늄/티타늄나이트라이드(15)는 후속공정에서 형성되는 텅스텐 플러그의 접착성(adhesion)을 좋게 하면서 동시에 텅스텐이 주변의 산화막이나 또는 하부의 접촉 부위에 침투해 들어가는 것을 막는 역할을 한다.Referring to FIG. 1B, the first titanium / titanium nitride (Ti / TiN) 15 is thinly deposited on the entire surface. The first titanium / titanium nitride 15 serves to improve the adhesion of the tungsten plug formed in a subsequent process and at the same time prevent tungsten from penetrating into the surrounding oxide film or the lower contact portion. .
도 1c를 참조하면, 상기 비아홀(13)을 매립하는 텅스텐(17)을 전체표면상부에 형성하되, 화학기상증착(chemical vapor deposition, 이하에서 CVD 라 함)에 의해 형성한다.Referring to FIG. 1C, tungsten 17 filling the via hole 13 is formed on the entire surface, and is formed by chemical vapor deposition (hereinafter, referred to as CVD).
도 1d를 참조하면, 상기 비아 홀(13) 이외의 부위에 존재하는 상기 텅스텐(17) 및 제1 티타늄/티타늄나이트라이드(15)를 화학적-기계적-연마(CMP : chemical mechanical polishing)방식으로 제거하여 텅스텐으로 비아 콘택플러그를 형성한다.Referring to FIG. 1D, the tungsten 17 and the first titanium / titanium nitride 15 which are present in portions other than the via hole 13 are removed by chemical mechanical polishing (CMP). To form a via contact plug with tungsten.
이때, 상기 텅스텐(17) 층의 상부에 나타나는 표면 굴곡 (surface topology_)도 함께 평탄화한다.At this time, the surface topology (surface topology) appearing on top of the tungsten (17) layer is also planarized.
일반적으로, 화학적-기계적-연마 공정이 완료된 대개의 경우 텅스텐 플러그와 주변의 산화막 사이에는 약간의 단차가 존재한다.In general, there are some steps between the tungsten plug and the surrounding oxide film in most cases when the chemical-mechanical-polishing process is complete.
도 1e를 참조하면, 금속 배선 형성에 필요한 높이만큼 제2 티타늄/티타늄나이트라이드(19) / 알루미늄(21) / 제3 티타늄나이트라이드(23)를 전면 증착시킨다.Referring to FIG. 1E, the second titanium / titanium nitride 19 / aluminum 21 / third titanium nitride 23 is entirely deposited to a height necessary for forming a metal wiring.
이때, 상기 알루미늄(21) 하부의 제2 티타늄/티타늄나이트라이드(19)는 상기 비아홀(13) 표면에 형성되는 제1 티타늄/티타늄나이트라이드(15)와 동일한 역할을 수행하며, 상기 알루미늄(21) 상부의 제3티타늄/티타늄나이트라이드(23)는 차후에 이루어지는 감광막 패턴닝 공정에서 빛의 반사 방지막(ARC: anti-reflective coating) 역할을 담당한다.In this case, the second titanium / titanium nitride 19 under the aluminum 21 plays the same role as the first titanium / titanium nitride 15 formed on the surface of the via hole 13, and the aluminum 21 The third titanium / titanium nitride 23 on the upper part of the upper part serves as an anti-reflective coating (ARC) in a subsequent photoresist patterning process.
도 1f를 참조하면, 감광막을 필요한 높이만큼 증착시킨 후에 패턴닝하여 감광막패턴(25)을 형성한다.Referring to FIG. 1F, the photoresist film is deposited to a required height and then patterned to form the photoresist pattern 25.
이때, 상기 감광막패턴(25)은 제2금속배선 마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다.In this case, the photoresist pattern 25 is formed by an exposure and development process using a second metal wiring mask (not shown).
도 1g를 참조하면, Cl2+ BCl3를 활성화 시킨 플라즈마를 이용하여 제2 티타늄/티타늄나이트라이드(19) / 알루미늄(21) / 제3 티타늄나이트라이드(23) 적층구조를 식각한다.Referring to FIG. 1G, the second titanium / titanium nitride 19 / aluminum 21 / third titanium nitride 23 stacked structure is etched using a plasma in which Cl 2 + BCl 3 is activated.
여기서, 상기 식각공정시 마이크로-로딩(etch rate micro-loading)현상이 발생한다. 즉, 금속 배선 간의 간격이 좁은 부위의 식각율이 금속 배선 간의 간격이 넓은 부위의 식각율 보다 작기 때문에, 결과적으로 금속 배선간의 간격이 넓은 부위의 금속 식각이 완료되었을 때 간격이 좁은 부위에는 δA1만큼의 금속 층이 여전히 남아 있다.Here, etch rate micro-loading phenomenon occurs during the etching process. That is, since the etching rate of the portion where the spacing between the metal wirings is narrow is smaller than the etching rate of the portion where the spacing between the metal wirings is wide, consequently, when the metal etching of the portion having the spacing between the metal wirings is completed, δ A1 As many metal layers remain.
도 1h를 참조하면, 금속 배선 식각이 완료된 상태로서, 식각율 마이크로-로딩 현상 때문에 금속배선간의 간격이 넓은 부위의 산화막(11)과 좁은 부위 사이에는 산화막(11)의 두께는 δo 만큼의 차이가 발생한다.Referring to FIG. 1H, the etching of the metal wiring is completed, and the thickness of the oxide film 11 varies between the oxide film 11 and the narrow portion of the wide gap between the metal lines due to the etch rate micro-loading phenomenon. Occurs.
이때, δA1과 δo 과 δo 사이에는 δoδA1/Sci Al/Ox(Cl2+ BCl3를 활성화 시킨 플라즈마에서 알루미늄의 산화막에 대한 식각비)의 관계가 성립한다.At this time, δo between δ A1 and δo and δo The relationship between δ A1 / S ci Al / Ox (the etching ratio of aluminum to the oxide film in the plasma activated with Cl 2 + BCl 3 ) is established.
상기한 바와같이 종래기술에 따른 반도체소자의 금속배선 형성방법은,As described above, the metal wiring forming method of the semiconductor device according to the prior art,
먼저, 금속배선간의 간격이 좁은 지역에서 알루미늄 하부의 티타늄/티타늄나이트라이드 막까지 완전히 식각하면, 식각율 마이크로-로딩 현상 때문에 완료된 금속 배선간의 간격이 넓은 지역에서는 하부 산화막의 손실이 심하게 발생한다.First, if the gap between the metal interconnections is completely etched from the region of the aluminum to the titanium / titanium nitride film under the aluminum, the loss of the lower oxide film occurs severely in the region between the completed interconnects due to the etch rate micro-loading phenomenon.
그리고, 상기 하부 산화막의 손실이 심하게 발생하면 이후에 이루어지는 상부 산화막의 증착 및 평탄화 공정이 어려워져 공정 비용이 많이 들고 제조된 반도체 칩(chip)의 수율(yield)에 악 영향을 끼친다.In addition, if the loss of the lower oxide film occurs severely, the subsequent deposition and planarization of the upper oxide film becomes difficult, which causes a high process cost and adversely affects the yield of the manufactured semiconductor chip.
그리고, 식각율 마이크로-로딩 현상 때문에 플라즈마에 의한 식각 시간이 길어지며, 그 결과 이미 패턴닝된 금속 배선의 측벽(sidewall)이 플라즈마에 노출되는 시간이 길어지게 되어 측벽이 손상될 가능성이 높아진다.In addition, the etching time by the plasma is increased due to the etching rate micro-loading phenomenon, and as a result, the sidewall of the already patterned metal wiring is exposed to the plasma, thereby increasing the possibility of damaging the sidewall.
그리고, 증착된 텅스텐의 제거 및 평탄화 공정이 완료되면 비아 홀을 매립하는 비아콘택 플러그가 외부에 노출된다. CMP 공정이 완료되면, 연마 공정에서 사용된 연마제 및 공정 부산물(byproduct)을 제거하기 위한 세정 공정(cleaning process)시 비아콘택플러그가 손상될 가능성이 높다.When the removal and planarization of the deposited tungsten is completed, the via contact plug filling the via hole is exposed to the outside. Once the CMP process is complete, the via contact plug is likely to be damaged during the cleaning process to remove abrasives and byproducts used in the polishing process.
특히 세정제가 비아콘택 플러그와 산화막 측벽 사이에 존재하는 제1티타늄/티타늄나이트라이드와 지속적으로 반응하며 들어가 비아콘택 플러그 바닥 부위의 기계적 결합과 전기적인 접촉을 취약하게 만드는 경우도 있다.In particular, the cleaning agent may continuously react with the first titanium / titanium nitride present between the via contact plug and the oxide sidewall to weaken the mechanical bonding and electrical contact at the bottom of the via contact plug.
또한, 화학적-기계적-연마 공정이 완료된 대개의 경우 텅스텐 플러그와 주변의 산화막 사이에는 약간의 단차가 존재한다. 이와 같이 단차가 발생하면 이후의 공정에서 증착된 제2티타늄/티타늄나이트라이드 / 알루미늄 / 제3티타늄/티타늄나이트라이드 층과 하부 층 사이의 접착력이 떨어진다. 그리고, 상기 알루미늄 증착 이전에 티타늄/티타늄나이트라이드 막을 증착시켜 접착성을 보완한다 할지라도, 텅스텐 플러그가 다수 모여 있는 지역에서는 제2티타늄/티타늄나이트라이드 / 알루미늄 / 제3티타늄/티타늄나이트라이드 층이 하부 층과 떨어지는 경우가 발생한다.Also, in most cases when the chemical-mechanical-polishing process is completed, there is a slight step between the tungsten plug and the surrounding oxide film. When the step occurs as described above, the adhesion between the second titanium / titanium nitride / aluminum / third titanium / titanium nitride layer and the lower layer deposited in a later process is reduced. In addition, although the titanium / titanium nitride film is deposited prior to the aluminum deposition to improve adhesion, the second titanium / titanium nitride / aluminum / third titanium / titanium nitride layer is formed in a region where a large number of tungsten plugs are collected. Falling with the underlying layer occurs.
결론적으로 고집적도의 금속 배선을 효과적으로 구현하기 위해서는 식각 과정에서 발생하는 마이크로-로딩 현상의 문제점 및 텅스텐 플러그의 외부 노출에 따른 훼손의 문제점을 해결할 수 있는 새로운 공정 방식을 개발할 필요가 있다.In conclusion, in order to effectively implement high-density metal wiring, it is necessary to develop a new process method to solve the problem of micro-loading phenomenon occurring during the etching process and the damage caused by the external exposure of the tungsten plug.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 금속배선을 형성하기 위한 식각공정시 하부에 형성되는 절연막의 두께를 유지할 수 있도록 하여 소자의 특성 열화를 방지할 수 있는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, to maintain the thickness of the insulating film formed on the lower portion during the etching process for forming the metal wiring to form a metal wiring of the semiconductor device that can prevent deterioration of device characteristics The purpose is to provide a method.
도 1a 내지 도 1h는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1A to 1H are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2l는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.2A to 2L are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11,31 : 하부산화막 13,33 : 비아홀11,31: Lower oxide film 13,33: Via hole
15,35 : 제1 티타늄/티타늄나이트라이드15,35: first titanium / titanium nitride
17,37 : 텅스텐 19,39 : 제2 티타늄/티타늄나이트라이드17,37 tungsten 19,39: second titanium / titanium nitride
21,41 : 알루미늄 23,43 : 제3 티타늄/티타늄나이트라이드21,41: aluminum 23,43: third titanium / titanium nitride
25,45 : 감광막패턴25,45 photosensitive film pattern
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은, 하부 금속배선을 노출시키는 비아콘택홀이 구비되는 하부산화막을 형성하는 공정과, 비아콘택홀 표면에 제1 티타늄/티타늄나이트라이드를 형성하고 상기 비아콘택홀을 매립하는 텅스텐을 매립하는 공정과, 텅스텐을 일정두께 식각하여 평탄화시키되, 하부산화막 상측에 상기 텅스텐을 일정두께 남기는 공정과, 텅스텐 상부에 제2 티타늄/티타늄나이트라이드, 알루미늄 및 제3 티타늄/티타늄나이트라이드 적층구조를 형성하는 공정과, 후속공정으로 적층구조와 텅스텐의 식각선택비 차이를 이용하여 상기 적층구조를 상부 금속배선 마스크를 이용해 Cl2+ BCl3를활성화시킨 플라즈마, SF6를 활성화시킨 플라즈마 및 Cl2+ BCl3를활성화시킨 플라즈마로 식각함으로써 마이크로-로딩 효과를 최소화시키며 하부금속배선에 접속되는 상부 금속배선을 형성하는 공정을 포함하는 것을 특징으로한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to the present invention includes forming a lower oxide film having a via contact hole exposing a lower metal wiring, and first titanium / titanium nitride on the surface of the via contact hole. Forming a ride and embedding the tungsten to fill the via contact hole, etching the tungsten to a predetermined thickness to planarize, leaving the tungsten at a predetermined thickness above the lower oxide layer, and a second titanium / titanium nitride on the tungsten To form a layer of aluminum and a third titanium / titanium nitride layer, and to subsequently use the upper metallization mask to activate Cl 2 + BCl 3 using the difference between the layer structure and the tungsten etching selectivity. plasma was Matt that activated by a SF 6 plasma, and the plasma to activate the etching Cl 2 + BCl 3 Chroman-minimizes the loading effect is characterized in that it comprises a step of forming an upper metal wiring connected to the lower metal wiring.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는 다음과 같다.On the other hand, the principle of the present invention for achieving the above object is as follows.
먼저, 현재 반도체 제조 공정에서, 알루미늄, 티타늄/티타늄나이트라이드 및 텅스텐의 식각에 일반적으로 사용되는 Cl2+ BCl3플라즈마와 SF6플라즈마의 선택비(selectivity)에 대해 살펴보자.First, the selectivity of the Cl 2 + BCl 3 plasma and the SF 6 plasma, which are generally used for etching aluminum, titanium / titanium nitride and tungsten in the semiconductor manufacturing process, will be described.
SCl Al/ox(Cl2+ BCl3를 활성화 시킨 플라즈마에서 알루미늄 산화막에 대한 식각비),S Cl Al / ox (etch ratio for aluminum oxide in plasma with Cl 2 + BCl 3 activated),
SCl Al/w(Cl2+ BCl3를 활성화 시킨 플라즈마에서 알루미늄 텅스텐에 대한 식각비),S Cl Al / w (etch ratio for aluminum tungsten in plasma activated with Cl 2 + BCl 3 ),
SCl Ti/Ox(Cl2+ BCl3를 활성화 시킨 플라즈마에서 티타늄/티타늄나이트라이드의 산화막에 대한 식각비),S Cl Ti / Ox (etch ratio of titanium / titanium nitride to the oxide film in a plasma activated with Cl 2 + BCl 3 ),
Ssf w/Ti(SF6를 활성화 시킨 플라즈마에서 텅스텐의 티타늄/티타늄나이트라이드에 대한 식각비),S sf w / Ti (etch ratio of tungsten to titanium / titanium nitride in a plasma activated with SF 6 ),
SCl Al/ox∼10,SCl Al/w∼10, SCl Ti/Ox∼5,Ssf w/Ti∼15S Cl Al / ox- 10, S Cl Al / w- 10, S Cl Ti / Ox- 5, S sf w / Ti- 15
본 발명에서는 텅스텐 플러그의 평탄화 공정에서 비아-구멍 이외의 부위에 일정 두께의 텅스텐 박막을 남긴 후에 그 위에 티타늄/티타늄나이트라이드 / 알루미늄 / 티타늄/티타늄나이트라이드 층을 증착 시킨다.In the present invention, in the planarization process of the tungsten plug, a thin film of tungsten is deposited on portions other than the via-holes, and then a titanium / titanium nitride / aluminum / titanium / titanium nitride layer is deposited thereon.
이와 같이하여 형성된 다중 금속층 티타늄/티타늄나이트라이트 / 알루미늄 / 티타늄/티타늄나이트라이드를 Cl2+ BCl3를 활성화시킨 플라즈마로 식각하면, 식각비 SCl Al/w∼10 때문에 텅스텐 막이 식각-정지 막(etch stopppiong layer)처럼 작용하고, 그 결과 티타늄/티타늄나이트라이드 / 알루미늄 / 티타늄/티타늄나이트라이드 층이 식각되는 과정에서 식각율 마이크로-로딩이 현상 때문에 발생한 단차가 텅스텐 층에서는 1/SCl Al/w의 비율로 줄어든다.When the thus formed multi-metal layer titanium / titanium nitrite / aluminum / titanium / titanium nitride is etched with a plasma activated with Cl 2 + BCl 3 , the tungsten film is etch-stopped due to the etching ratio S Cl Al / w˜10. etch stopppiong layer, and as a result, the step difference caused by the etch rate micro-loading during the etching of the titanium / titanium nitride / aluminum / titanium / titanium nitride layer is 1 / S Cl Al / w in the tungsten layer. Decreases at the rate of.
남아 있는 텅스텐 층을 SF6를 활성화 시킨 플라즈마로 식각하면 텅스텐 층으 아래에 존재하는 티타늄/티타늄나이트라이드 층이 식각-정지-막으로 작용하기 때문에 텅스텐 층이 식각되는 과정에서 발생한 단차가 티타늄/티타늄나이트라이드 층에서는 1/Ssf w/Ti의 비율로 줄어든다.When the remaining tungsten layer is etched with SF 6 activated plasma, the titanium / titanium nitride layer under the tungsten layer acts as an etch-stop-film. In the ride layer it is reduced at the rate of 1 / S sf w / Ti .
마지막으로 남아 있는 티타늄/티타늄나이트라이드 층을 Cl2+ BCl3를 활성화 시킨 플라즈마로 식각하면, 동일한 이유로 티타늄/티타늄나이트라이드 층에서 발생한 단차가 산화막 층에서는 SCl Ti/Ox의 비율로 줄어든다.Finally, when the remaining titanium / titanium nitride layer is etched with Cl 2 + BCl 3 activated plasma, the step difference generated in the titanium / titanium nitride layer is reduced to the ratio of S Cl Ti / Ox in the oxide layer for the same reason.
결론적으로 본발명에서 제시한 방식으로 공정을 진행할 경우 식각이 완료 되었을 때 하부 산화막에 발생하는 단차는SCl Al/ox/(SCl Al/w∼10 Ssf w/Ti∼15SCl Ti/Ox∼5)의 비율로 줄어들어 기존의 공정 방식에 비해 무시할 수 있을 정도로 작아진다.In conclusion, if the process is carried out in the manner suggested in the present invention, the step difference generated in the lower oxide layer after etching is S Cl Al / ox / (S Cl Al / w ~ 10 S sf w / Ti ~ 15S Cl Ti / Ox ~ 5) is reduced to a negligible size compared to the conventional process method.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2l 은 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A through 2L are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 기존의 공정 방식과 동일한 방식으로 하부산화막(31)에 비아홀(33)을 형성한다.Referring to FIG. 2A, the via hole 33 is formed in the lower oxide layer 31 in the same manner as the conventional process method.
도 2b를 참조하면, 기존의 공정 방식으로 상기 비아홀(33)을 포함한 전체표면상부에 동일한 방식으로 제1 티타늄/티타늄나이트라이드 (Ti/TIN)(35)를 얇게 전면 층착 시킨다.Referring to FIG. 2B, the first titanium / titanium nitride (Ti / TIN) 35 is thinly deposited on the entire surface including the via hole 33 in a conventional process manner.
도 2c를 참조하면, 기존의 공정 방식과 동일한 방식으로 텅스텐(37)을 전면 증착시켜 비아 구멍을 채운다.Referring to FIG. 2C, tungsten 37 is completely deposited in the same manner as the conventional process method to fill the via hole.
도 2d를 참조하면, 상기 비아홀(33) 구멍 이외의 부위에 존재하는 텅스텐(37) 및 제1티타늄/티타늄나이트라이드(35)를 CMP 하여 평탄화 시킨다. 이때, 상기 비아홀(33) 이외의 부위에 일정 두께의 텅스텐(37) 박막이 남아 잇을 정도로 연마량을 조절한다.Referring to FIG. 2D, the tungsten 37 and the first titanium / titanium nitride 35 present in portions other than the via hole 33 are CMP to planarize. At this time, the amount of polishing is adjusted to the extent that a thin film of tungsten 37 having a predetermined thickness remains in portions other than the via hole 33.
도 2e를 참조하면, 금속 배선 형성에 필요한 높이만큼 제2 티타늄/티타늄나이트라이드(39) / 알루미늄(41) / 제3 티타늄/티타늄나이트라이드(43)를 전면 증착 시킨다.Referring to FIG. 2E, the second titanium / titanium nitride 39 / aluminum 41 / third titanium / titanium nitride 43 is entirely deposited to a height necessary for forming a metal wiring.
이때, 상기 제2 티타늄/티타늄나이트라이드(39) / 알루미늄(41) / 제3 티타늄/티타늄나이트라이드(43)의 두께는 기존의 공정 방식에서 증착되는 두께에 비해 약간 작아도 된다.In this case, the thickness of the second titanium / titanium nitride 39 / aluminum 41 / third titanium / titanium nitride 43 may be slightly smaller than the thickness deposited in the conventional process method.
도 2f를 참조하면, 필요한 높이만큼 감광막패턴(45)을 형성한다. 이때, 상기 감광막패턴(45) 제2금속배선 마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다.Referring to FIG. 2F, the photoresist pattern 45 is formed to a required height. In this case, the photosensitive film pattern 45 is formed by an exposure and development process using a second metal wiring mask (not shown).
도 2g를 참조하면, Cl2+ BCl3를활성화시킨 플라즈마를 이용하여 제2 티타늄/티타늄나이트라이드(39) / 알루미늄(41) / 제3 티타늄/티타늄나이트라이드(43)를 상부로부터 식각한다.Referring to FIG. 2G, the second titanium / titanium nitride 39 / aluminum 41 / third titanium / titanium nitride 43 is etched from the top using a plasma activated with Cl 2 + BCl 3 .
기존 공정 방식과 마찬가지로 식각율 마이크로-로딩 효과 때문에 금속 배선 간의 간격이 넓은 부위의 금속 식각이 완료되었을 때 간격이 좁은 부위에는 εAl만큼의 금속 층이 남아 있게 된다.As with the conventional process method, due to the etch rate micro-loading effect, when the metal etching of the large gap between the metal lines is completed, the metal layer of ε Al remains in the narrow gap.
상기 제2 티타늄/티타늄나이트라이드(39) / 알루미늄(41) / 제3 티타늄/티타늄나이트라이드(43) 적층구조가 기존의 공정 방식에서 증착되는 두께에 비해 약간 작기 때문에 εAl은 Al에 비해 약간 작다.Since the second titanium / titanium nitride (39) / aluminum (41) / third titanium / titanium nitride (43) stack structure is slightly smaller than the thickness deposited in the conventional process method, ε Al is Slightly smaller than Al
도 2h를 참조하면, 제2 티타늄/티타늄나이트라이드(39) / 알루미늄(41) / 제3 티타늄/티타늄나이트라이드(43) 적층구조의 식각이 완료된 상태로서, 식각율 마이크로-로딩 현상 때문에 금속 배선 간의 간격이 넓은 부위의 텅스텐 막과 좁은 부위 사이에는 텅스텐 막의 두께는 εW만큼의 차이가 발생한다. 이때, εW와 εAl사이에는 εW εAl/ (SCl Al/w) 의 관계가 성립한다.Referring to FIG. 2H, the etching of the second titanium / titanium nitride 39 / aluminum 41 / third titanium / titanium nitride 43 stacked structure is completed, and the metal wiring due to the etch rate micro-loading phenomenon. The thickness of the tungsten film differs as much as ε W between the tungsten film and the narrow part of the wide spaced portion. At this time, ε W W between ε and ε Al The relationship of ε Al / (S Cl Al / w ) holds.
도 2i를 참조하면, SF6를 활성화시킨 플라즈마를 이용하여 남아 있는 텅스텍(37) 막을 식각한다.Referring to FIG. 2I, the remaining tungsten film 37 is etched using the plasma activated with SF 6 .
도 2j를 참조하면, SF6를 활성화시킨 플라즈마에 의한 텅스텐(37)막의 식각이 완료된 상태로서, 식각이 시작될 때 텅스텐 막에 이미 존재하던 단차 εW와 텅스텐 막 식각 시 새롭게 부가되는 마이크로-로딩 효과 때문에 텅스텐 하부의 제1 티타늄/티타늄나이트라이드(35) 막에는 εti만큼의 단차가 발생한다. 그리고, SF6플라즈마에서 텅스텐(37)의 제1 티타늄/티타늄나이트라이트(35)에 대한 식각비를 고려하여 εti의 값을 계산하면 다음과 같다.Referring to FIG. 2J, the etching of the tungsten 37 film by the SF 6- activated plasma is completed, and the micro-loading effect newly added during the etching of the tungsten film and the step ε W already present in the tungsten film at the start of etching is completed. since the first and titanium / titanium nitride (35) of the tungsten film the lower is generated in a step of ε by ti. In addition, when calculating the value of ε ti in consideration of an etching ratio of the tungsten 37 to the first titanium / titanium nitrite 35 in the SF 6 plasma, the value of ε ti is as follows.
εti εW/(SSF w/Ti)+ ε(SSF w/Ti)ε ti ε W / (S SF w / Ti) + ε (S SF w / Ti )
상기 텅스텐(37) 막의 두께가 제2 티타늄/티타늄나이트라이드(39) / 알루미늄(41) / 제3 티타늄/티타늄나이트라이드(43) 적층구조에 비하여 얇을 경우 εWε 의 조건을 언제나 만족시킨다. 따라서 제1 티타늄/티타늄나이트라이트(35) 막에서 발생하는 단차 εti는When the thickness of the tungsten (37) film is thinner than the second titanium / titanium nitride (39) / aluminum (41) / third titanium / titanium nitride (43) layered structure, the condition of ε W ε is always satisfied. Therefore, the step ε ti generated in the film of the first titanium / titanium nitride 35 is
εti< 2εW/(SSF w/Ti)2εW(SSF Al/WSSF w/Ti)ε ti <2ε W / (S SF w / Ti ) 2ε W (S SF Al / W S SF w / Ti )
의 조건을 만족 시킨다. 여기서 ε은 텅스텐막 식각시 새롭게 부과되는 마이크로 로딩 효과를 나타내는 것이다.Satisfies the conditions. Ε represents a micro loading effect imposed upon the tungsten film etching.
도 2k를 참조하면, Cl2+ BCl3를활성화시킨 플라즈마를 이용하여 상기 텅스텐(37) 막 하부에 존재하는 제1 티타늄/티타늄나이트라이드(35) 막을 식각한다.Referring to FIG. 2K, the first titanium / titanium nitride 35 film under the tungsten 37 film is etched using a plasma activated with Cl 2 + BCl 3 .
도 2l를 참조하면, Cl2+ BCl3를활성화시킨 플라즈마를 이용하여 상기 텅스텐(37) 막 하부에 존재하는 제1 티타늄/티타늄나이트라이드(35) 막의 식각을 완료한 상태로서, 제1 티타늄/티타늄나이트라이드(35) 막에 이미 존재하던 단차 εti와 식각시 추가로 발생하는 마이크로-로딩 효과 때문에 하부산화막(31)에서 발생하는 단차는Referring to FIG. 2L, the etching of the first titanium / titanium nitride 35 film under the tungsten 37 film is completed using the plasma activated with Cl 2 + BCl 3 . Due to the step ε ti already present in the titanium nitride film 35 and the micro-loading effect generated during etching, the step generated in the lower oxide film 31 is
εox εti/(SDl Ti/ox)+ ε'(SDl Ti/ox)ε ox ε ti / (S Dl Ti / ox) + ε '(S Dl Ti / ox )
로 주어진다. 대개의 경우 εtiε 조건을 만족하므로 결국 하부 산화막(31)에 최종적으로 발생하는 단차는Is given by In most cases, since the ε ti ε condition is satisfied, the step that finally occurs in the lower oxide film 31 is
εox 2εti/(SDl Ti/ox)+ 4εAl(SDl TAl/WSSF W/TiSDl Ti/ox)ε ox 2ε ti / (S Dl Ti / ox) + 4ε Al (S Dl TAl / W S SF W / Ti S Dl Ti / ox )
의 조건을 만족한다.Satisfies the conditions.
한편, 본 발명의 다른 실시예는 평탄화식각공정을 CMP 대신 전면 식각(blanket etch)방식을 채용하는 것이다.On the other hand, another embodiment of the present invention is to employ a planar etching (blanket etch) method instead of the CMP planarization etching process.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은 다음과 같은 효과가 있다.As described above, the metal wiring forming method of the semiconductor device according to the present invention has the following effects.
먼저, 금속 배선의 식각이 완료되었을 때 발생하는 하부산화막의 단차를 줄이고, CMP 공정시 비아콘택플러그의 노출 및 손상을 억제하며 비아콘택플러그와 상부금속배선인 제2금속배선과의 접착력을 증가시키고, CMP 량을 감소시켜 공정 비용을 절감하여 반도체소자의 생산성, 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.First, it reduces the step of the lower oxide film generated when the etching of the metal wiring is completed, suppresses the exposure and damage of the via contact plug during the CMP process, increases the adhesion between the via contact plug and the second metal wiring, the upper metal wiring. By reducing the amount of CMP, the process cost can be reduced, thereby improving the productivity, characteristics, and reliability of the semiconductor device, thereby providing high integration of the semiconductor device.
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| KR100668960B1 (en) * | 2004-12-23 | 2007-01-12 | 동부일렉트로닉스 주식회사 | Metal line in semiconductor device and fabricating method threof |
| KR100811663B1 (en) * | 2006-07-24 | 2008-03-11 | 재단법인서울대학교산학협력재단 | A Planar Applicator radiator using resonance |
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