KR20020081798A - Method for manufacturing of mml semiconductor device of capacitor - Google Patents

Abstract

PURPOSE: A capacitor fabrication method of an MML(Merged Memory Logic) device is provided to minimize area of capacitor and to increase a capacitance by forming a lower electrode using a plug processing. CONSTITUTION: An isolation layer(102) is formed at a field region of a semiconductor substrate(101) having a cell and a logic regions. A transistor having gate electrodes(104a,104b), and source and drain regions is then formed at an active region. After forming a first interlayer dielectric(106) on the resultant structure, a plurality of via holes are formed to expose the source and drain regions. A lower electrode(109a) is formed in the via hole of the logic region, and plugs(109b) are simultaneously formed in the via holes of the cell region. After forming an insulating layer(110) on the resultant structure, a contact hole is formed to expose the surface of the plug(109b). Then, an upper electrode(113a) is formed in the contact hole and a bit line(113b) is simultaneously formed on the logic region.

Description

METHODS FOR MANUFACTURING OF MML SEMICONDUCTOR DEVICE OF CAPACITOR}

The present invention relates to a method of manufacturing a capacitor of an MML semiconductor device, and more particularly, to a method of manufacturing a capacitor of an MML semiconductor device capable of minimizing an area of a capacitor and increasing a capacity thereof.

Recently, the MML device is a device in which a memory cell array unit such as a DRAM (Dynamic Random Access Memory) and an analog or peripheral circuit are integrated together in one chip. Therefore, not only digital devices but also various analog devices are configured at the same time. That is, when manufacturing MML devices, bipolar devices and analog capacitors, as well as MOS devices, must be considered.

Hereinafter, a capacitor manufacturing method of a conventional MML semiconductor device will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional MML semiconductor device.

As shown in FIG. 1A, an active region and a field region are defined in the semiconductor substrate 11 in which a cell region and a logic region are defined. The field region is selectively removed to form a trench having a predetermined depth, and a first insulating layer is formed on the semiconductor substrate 11 including the trench.

Subsequently, an isolation layer 12 having a shallow trench isolation (STI) structure is formed by performing an etch back or CMP process on the entire surface of the semiconductor substrate 11 so that the first insulating layer remains only inside the trench.

Subsequently, after forming the plurality of gate electrodes 14a and 14b having the gate insulating layer 13 on the semiconductor substrate 11, the second insulating layer is formed on the entire surface of the substrate 11 including the gate electrodes 14a and 14b. The second insulating film spacers 15 are formed on both sidewalls of the gate electrodes 14a and 14b using the etch back process.

Subsequently, a source / drain region is formed on a surface of the semiconductor substrate 11 on both sides of the gate electrode 14a and 14b using the gate electrodes 14a and 14b as a mask, and then a first interlayer is formed on the entire surface of the substrate 11. The insulating film 16 is formed.

As shown in FIG. 1B, a first photoresist 17 is deposited on the first interlayer insulating layer 16, and the first photoresist 17 is patterned using an exposure and development process.

Next, the via hole 18 is formed by selectively removing the first interlayer insulating layer 16 to expose the source / drain regions of the cell region using the patterned first photoresist 17 as a mask.

After removing the patterned first photoresist 17 as shown in FIG. 1C, a first polysilicon 19 is deposited on the first interlayer insulating layer 16 including the via holes 18. The first polysilicon 19 is selectively removed through an etching process to form a lower electrode 19a in the logic region, and a plurality of plugs 19b are formed in the via hole 18 of the cell region.

Subsequently, a third insulating film 20 is formed on the first interlayer insulating film 16 including the lower electrode 19a and the plug 19b.

As shown in FIG. 1D, the second photoresist 21 is deposited on the third insulating film 20, and the second photoresist 21 is patterned by using an exposure and development process.

Next, the contact hole 22 is formed using the patterned second photoresist 21 as a mask to expose a predetermined portion of the plug 19b of the portion where the bit line of the cell region is to be formed.

After removing the patterned second photoresist 20 as shown in FIG. 1E, a second polysilicon 23 is deposited on the third insulating film 20 including the contact hole 22 and selectively patterned. As a result, an upper electrode 23a is formed on the lower electrode 19a of the logic region, and a bit line 23b connected to the plug 19b is formed in the contact hole 22 of the cell region.

In the conventional capacitor manufacturing method of the MML device as described above has the following problems.

In the logic chip manufacturing process, the first electrode and the second polysilicon are usually formed to form the lower electrode and the upper electrode of the analog capacitor, in which case the second polysilicon is used only to manufacture the analog capacitor, except in special cases. do.

However, in the case of the MML device, since the bit line is formed by using the second polysilicon in DRAM manufacturing, the second polysilicon is necessary. Therefore, there is a difficulty in design rules of the high integration device.

The present invention has been made to solve the above problems to form a lower electrode of the analog capacitor by using a plug process to provide a capacitor manufacturing method of the MML device that can minimize the area of the analog capacitor and increase the capacity. The purpose is.

1A to 1E are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional MML semiconductor device.

2A through 2E are cross-sectional views illustrating a method of manufacturing a capacitor in an MML semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101 semiconductor substrate 102 device isolation film

103: gate insulating film 104a, 104b: gate electrode

105: second insulating film spacer 106: first interlayer insulating film

107: first photoresist 108a, 108b: via hole

109a: lower electrode 109b: plug

110: third insulating film 111: second photoresist

112: contact hole 113a: upper electrode

113b: bitline

In the method of manufacturing a capacitor of the MML device of the present invention for achieving the above object, in the MML device, after forming an active region and a field region on a semiconductor substrate having a cell region and a logic region, forming an isolation layer in the field region Forming a transistor having a gate electrode and a source / drain impurity region in the active region, forming a first interlayer insulating film on the entire surface including the transistor, and selectively selecting a source / drain impurity region of the transistor Forming a plurality of via holes to partially expose, forming a plurality of plugs in the via holes of the cell region, and simultaneously forming a lower electrode in the via holes of the logic region, forming an insulating film on the front surface, and forming a bit line in the cell region Forming a contact hole so that the plug surface to be formed is partially exposed; A bit line connected to the contact hole on the reverse at the same time as forming characterized by including the step of forming the upper electrode in the logic region.

Further, in the capacitor manufacturing method of the MML semiconductor device of the present invention, the transistor comprises the steps of forming a plurality of gate electrodes having a gate insulating film on the substrate, forming an insulating film spacer on both side walls of the gate electrode, the gate electrode Preferably, the method further includes forming source / drain impurity regions on the substrate surfaces on both sides.

In addition, the via hole may be formed by selectively removing the first interlayer insulating layer through a dry etching process.

The plug and lower electrode may further include forming a first polysilicon layer on the first interlayer insulating layer, and selectively removing the first conductive layer on the first polysilicon using a CMP process. It is preferable.

In addition, it is preferable that the insulating film is SiO ₂ / SiN, Ta ₂ O ₅ , BST.

In addition, the upper electrode preferably uses a second polysilicon layer and a metal layer.

In addition, after forming the first polysilicon layer, it is preferable to further include forming a buried metal layer.

Hereinafter, a capacitor manufacturing method of an MML semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor of an MML semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, an active region and a field region are defined in the semiconductor substrate 101 in which a cell region and a logic region are defined. The field region is selectively removed to form a trench having a predetermined depth, and a first insulating layer is formed on the semiconductor substrate 101 including the trench.

Subsequently, an isolation layer 102 having a shallow trench isolation (STI) structure is formed by performing an etch back or CMP process on the entire surface of the semiconductor substrate 101 so that the first insulating layer remains only inside the trench.

Subsequently, after forming the plurality of gate electrodes 104a and 104b having the gate insulating film 103 on the semiconductor substrate 101, the second insulating film is formed on the entire surface of the substrate 101 including the gate electrodes 104a and 104b. The second insulating film spacers 105 are formed on both sidewalls of the gate electrodes 104a and 104b using the etch back process.

Subsequently, a source / drain region is formed on a surface of the semiconductor substrate 101 on both sides of the gate electrode 104a and 104b using the gate electrodes 104a and 104b as a mask, and then a first interlayer is formed on the entire surface of the substrate 101. The insulating film 106 is formed.

As shown in FIG. 2B, a first photoresist 107 is deposited on the first interlayer insulating layer 106, and the first photoresist 107 is patterned using an exposure and development process.

Subsequently, the source / drain regions of the cell region are exposed using the patterned first photoresist 107 as a mask, and the first interlayer insulating layer 106 of the portion where the capacitor of the logic region is to be formed is selectively removed. As a result, a plurality of via holes 108a and 108b are formed. In this case, the first interlayer insulating layer 106 is removed using a dry etching process. An area of the via hole 108a in the portion where the capacitor of the logic region is to be formed is larger than that of the via hole 108b of the cell region.

As shown in FIG. 2C, after the first polysilicon 109 is formed on the first interlayer insulating layer 106 including the via holes 108a and 108b, the first polysilicon may be selectively formed using a CMP process. Since 109 is removed, the lower electrode 109a of the analog capacitor is formed in the logic region and a plurality of plugs 109b connected to the source / drain regions are formed in the cell region.

Next, although not shown, a buried metal layer is formed on the lower electrode 109a and the plug 109b.

As shown in FIG. 2D, after the third insulating layer 110 is formed on the first interlayer insulating layer 106 including the lower electrode 109a of the logic region and the plug 109b of the cell region, the third insulating layer 110 is formed. A second photoresist 111 is deposited on 110 and selectively patterned using an exposure and development process. In this case, the third insulating layer 110 uses SiO ₂ / SiN, Ta ₂ O ₅ , and BST.

Subsequently, the third insulating layer 110 is removed by using the patterned second photoresist 111 as a mask so that the plug 109b of the region where the bit line of the cell region is to be formed is exposed. And form 112.

After removing the patterned second photoresist 111 as shown in FIG. 2E, a second polysilicon 113 is formed on the third insulating layer 110 including the contact hole 112. Selectively etching away the second polysilicon 113 using the photolithography process on the second polysilicon 113 to form the upper electrode 113a of the analog capacitor on the lower electrode 109a of the logic region; The bit line 113b is formed in the cell region. In this case, the upper electrode 113a may use a metal layer.

Accordingly, the analog capacitor in the logic region may form a capacitor having a poly-insulator-poly (PIP) structure and a capacitor having a poly-insulator-metal (PIM) structure.

As described above, according to the method of manufacturing a capacitor of the MML semiconductor device of the present invention, a three-dimensional analog capacitor is formed using a plug process used in a DRAM manufacturing process of 0.25 µm or less. Capacitor capacity can be secured.

Claims (8)

In the MML device, Defining an active region and a field region in a semiconductor substrate having a cell region and a logic region, and forming an isolation layer in the field region; Forming a transistor having a gate electrode and a source / drain impurity region in the active region; Forming a first interlayer insulating film on the entire surface including the transistor; Forming a plurality of via holes to selectively expose predetermined portions of the source / drain impurity regions of the transistor; Forming a plurality of plugs in the via holes of the cell region and forming a lower electrode in the via holes of the logic region; Forming an insulating film on the front surface and forming a contact hole to selectively expose a predetermined portion of the plug surface; And forming a bit line connected to the contact hole in the cell region and forming an upper electrode in the logic region. The method of claim 1, The transistor forming step may include forming a plurality of gate electrodes having a gate insulating layer on a substrate; Forming insulating film spacers on both sidewalls of the gate electrode; And forming a source / drain impurity region on the surface of the substrate on both sides of the gate electrode. The method of claim 1, The via hole may be formed by selectively removing the first interlayer insulating layer by using a dry etching process. The method of claim 1, The forming of the plug and the lower electrode may include forming a first conductive layer on the first interlayer insulating layer; And selectively removing the first conductive layer from the first conductive layer using a CMP process. The method of claim 4, wherein And the first conductive layer is polysilicon. The method of claim 4, wherein After forming the first conductive layer, the method of manufacturing a capacitor of the MML semiconductor device, further comprising the step of forming a buried metal layer. The method of claim 1, The insulating film is a capacitor manufacturing method of the MML semiconductor device, characterized in that using any one of SiO ₂ / SiN, Ta ₂ O ₅ , BST. The method of claim 1, The upper electrode is a capacitor manufacturing method of the MML semiconductor device, characterized in that using a polysilicon layer and a metal layer.