KR100480905B1 - Method for manufacturing of semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate having a bit line contact plug and a lower electrode contact plug; Forming an interlayer insulating film on the substrate resultant; Etching the interlayer insulating layer to form a contact hole exposing a lower electrode contact plug; Sequentially forming a lower electrode and a dielectric film on the contact hole surface; Depositing a conductive film on a dielectric film and an interlayer insulating film to fill the contact hole; Forming an insulating film having an etching selectivity greater than that of the interlayer insulating film on the conductive film; Etching the conductive layer and the insulating layer to expose the interlayer insulating layer to form an upper electrode; Forming spacers on both side walls of the upper electrode; Forming a bit line contact hole by etching the interlayer insulating layer to expose the bit line contact hole; And depositing a conductive film to fill the bit line contact hole.

Description

Method for manufacturing of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, by forming an insulating film on an upper electrode of a capacitor and forming spacers on both side walls of the upper electrode to self-align contact holes exposing bit line contact plugs to thereby have a critical dimension. The present invention relates to a method for forming a bit line in a semiconductor device, which simplifies the process by securing a forming process margin to prevent short circuit between the capacitor and the bit line and to form an interlayer insulating layer only once.

In the process of manufacturing a semiconductor memory cell having a capacitor under bitline (CUB) structure in which a capacitor is located below a bit line, a second contact hole forming process of forming a capacitor and then exposing the bit line contact plug is required. In the process of forming an etch mask in the second contact hole forming process, if an error occurs in alignment, a short circuit occurs between the upper electrode of the capacitor and the bit line.

Therefore, in order to prevent such a short circuit phenomenon, the margin of the second contact hole forming process is very poor.

1A to 1B are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

Referring to FIG. 1A, a field oxide film 11 is formed on a P-type semiconductor substrate 10 by a local oxide of silicon (LOCOS) method to define an active region and a field region in which an element is to be formed. The DRAM insulating layer 100, the gate 12, or the gate line 12, the cap nitride layer 13, the nitride side wall 14, and the source / drain (not shown) are patterned in the active region by a photolithography process. To manufacture transistors. In this case, the capsillation layer 13 serves as a mask when the gate 12 is formed and suppresses the polymeric particles. The nitride film side wall 14 serves as an insulating film sidewall for forming a self-aligned contact hole when forming a contact plug in a subsequent process.

Next, an insulating layer (not shown) is deposited on the entire surface of the substrate 10 including the gate 12, and then a photolithography process is performed to form a first electrode contact plug and a bit line contact plug. Form a hole.

In addition, a polysilicon layer doped with a conductive layer to fill the first contact hole is deposited on the insulating layer by CVD, and then patterned to form the bit line contact plug 15 and the lower electrode contact plug 16 of the capacitor. .

Next, an interlayer insulating layer 17 is deposited on the entire surface of the substrate using boronphospho silicate glass (BPSG), and then a second contact hole exposing the upper surface of the lower electrode contact plug 16 is formed by a photolithography process.

The lower electrode 18 and the dielectric layer 19 are sequentially formed of a conductive material in the second contact hole, and then a polysilicon layer doped with a conductive material is deposited on the dielectric layer and the interlayer insulating layer 17 to fill the second contact hole. To form.

The doped polysilicon film is patterned so that the doped polysilicon film remains on the surface of the interlayer insulating film 17 to form the upper electrode 20 of the capacitor.

Next, a second interlayer insulating film 21 is formed on the surface of the interlayer insulating film 17 including the exposed upper electrode 20 surface using BPSG or the like.

Referring to FIG. 1B, a photoresist is applied on the second interlayer insulating film 20 to expose the upper surface of the bit line contact plug 15, followed by exposure and development to form a photoresist pattern, and then a photoresist. The third contact hole is formed by removing the second interlayer insulating film 210 and the first interlayer insulating film 170 of the portion not protected by the pattern. Thus, the surface of the bit line contact plug 15 is exposed.

Next, a polysilicon layer doped with a conductive layer is deposited on the second interlayer insulating layer 210 to fill the second contact hole, and then patterned to form a bit line 22.

However, in the above-described conventional semiconductor device, when the capacitor has a structure under the bit line in the highly integrated DRAM cell, the capacitor may be misaligned in the process of forming the etch mask in the process of forming the second contact hole. A short circuit between the upper electrode and the bit line occurs, and an additional interlayer insulating film must be formed after the completion of the capacitor, which causes a complicated process.

Therefore, the present invention forms an insulating film on the upper electrode of the capacitor, forms a spacer on both side walls of the upper electrode, and self-aligns the contact holes exposing the bit line contact plugs, thereby securing a line width forming process margin to short-circuit the capacitor and the bit line. It is an object of the present invention to provide a method for manufacturing a semiconductor device which simplifies the process by preventing the phenomenon and forming the interlayer insulating film only once.

According to an aspect of the present invention, there is provided a semiconductor substrate including a bit line contact plug and a lower electrode contact plug. Forming an interlayer insulating film on the substrate resultant; Etching the interlayer insulating layer to form a contact hole exposing a lower electrode contact plug; Sequentially forming a lower electrode and a dielectric film on the contact hole surface; Depositing a conductive film on a dielectric layer and an interlayer insulating layer to fill the contact hole; Forming an insulating film having an etching selectivity greater than that of the interlayer insulating film on the conductive film; Etching the conductive layer and the insulating layer to expose the interlayer insulating layer to form an upper electrode; Forming spacers on both side walls of the upper electrode; Forming a bit line contact hole by etching the interlayer insulating layer to expose the bit line contact hole; And depositing a conductive film to fill the bit line contact hole.

As the area occupied by capacitors per unit area decreases with increasing integration of semiconductor memory devices, capacitors having a capacitor over bitline (COB) structure are advantageous in terms of securing capacitor capacity. However, semiconductors having a CUB structure have been developed by developing dielectric films having high dielectric constants such as Ta2O5 or BST and increasing the surface area of the lower electrode within a small area such as HSG (hemispherical grain) or surface area enhanced silicon (SAES). Since the memory device can be manufactured, the CUB structure has an advantage that one wiring layer can be omitted compared to the COB structure.

In addition, when a bit line contact plug exposure contact hole is formed in a semiconductor memory device having a CUB structure, a short circuit problem occurs between the capacitor and the bit line. Therefore, the process hole formation process is very small.

According to the present invention, an insulating film having an etching selectivity greater than that of an interlayer insulating film is formed on the upper electrode of the capacitor, spacers are formed on both side walls of the upper electrode, and then the self-aligned bit line contacts are covered with the peripheral area covered with an etching mask. A contact hole for plug exposure is formed. Therefore, it is advantageous to prevent short circuit between the bit line and the capacitor and to secure the line width of the bit line contact hole.

2A to 2D are cross-sectional views of a manufacturing process of a semiconductor device according to the present invention.

Referring to FIG. 2A, a field oxide layer 31 is formed on a silicon substrate 30, which is a P-type semiconductor substrate, by a method such as LOCOS (Local Oxidation of Silicon) to define an active region and a field region in which an element is to be formed. do. The DRAM insulating film 300, the gate 32 or the gate line 32, the cap nitride film 33, the nitride film side wall 34, and the source / drain (not shown) are patterned in the active region by a photolithography process. To manufacture transistors. In this case, the cap nitride layer 33 serves as a mask when the gate 32 is formed and suppresses polymeric particles. The nitride film side wall 34 serves as an insulating film sidewall for forming a self-aligned contact hole when forming a contact plug in a subsequent process.

Next, an insulating film (not shown) is deposited on the entire surface of the substrate 30 including the gate 32, and then a photolithography process is performed to form a first contact hole for forming a lower electrode contact plug and a bit line contact plug. To form.

A polysilicon film doped with a conductive layer to fill the first contact hole is deposited by CVD on the insulating film, and then patterned to form a bit line contact plug 35 and a lower electrode contact plug 36 of the capacitor.

Next, an interlayer insulating layer 37 is deposited on the entire surface of the substrate using boronphospho silicate glass (BPSG), and then a second contact hole exposing the upper surface of the lower electrode contact plug 36 is formed by a photolithography process.

Then, the lower electrode 38 and the dielectric layer 39 are sequentially formed of the conductive material in the second contact hole, and then the polysilicon layer doped with the conductive material on the dielectric layer and the interlayer insulating layer 37 to fill the second contact hole ( 40).

Next, the first nitride film 41 is deposited on the doped polysilicon film 40 by CVD.

Referring to FIG. 2B, the first nitride film and the doped polysilicon film are patterned by dry etching such that the doped polysilicon film 400 and the first nitride film 410 partially remain on the surface of the interlayer insulating film 37. The upper electrode 400 of the capacitor is formed.

Then, the second nitride film is deposited by the CVD method on the surface of the interlayer insulating film 37 including the remaining first nitride film 410, and then etched back to the second nitride film to retain the remaining first nitride film 410. The spacer 42 including the second nitride film 42 remaining on the side surface and the exposed upper electrode 400 is formed. The first nitride layer 410 remaining with the spacer 42 becomes a part of the etching mask of the second contact hole, which is formed in a self-aligning manner.

Referring to FIG. 2C, a photoresist is coated on the entire surface of the substrate, followed by exposure and development to form a photoresist pattern (not shown) for exposing the upper surface of the bit line contact plug 35. In this case, the photoresist pattern is formed to cover the peripheral area.

Dry etching is performed to remove the interlayer insulating film in a portion not protected by the photoresist pattern, thereby forming a second contact hole exposing the surface of the bit line contact plug. In this case, the second contact hole forming process is performed in a self-aligning manner using the spacers 42 and the remaining first nitride film 410 to prevent short circuits between the bit lines and the capacitors formed later, and also the line width of the second contact holes ( CD) Secure a large margin.

Referring to FIG. 2D, a polysilicon layer doped with a conductive layer is deposited on the remaining interlayer insulating layer 370 including the spacers 42 and the first nitride layer 410 to fill the second contact hole, and then patterned. The bit line 43 is formed.

As described above, the present invention secures a critical dimension formation process by forming an insulating film on the upper electrode of the capacitor and forming a spacer on both side walls of the upper electrode to self-align contact holes exposing the bit line contact plugs. Therefore, the short circuit between the capacitor and the bit line is prevented and the interlayer insulating film is formed only once, thereby simplifying the process.

1A to 1B are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

2A to 2D are sectional views of the manufacturing process of the semiconductor device according to the present invention;

Claims (3)

Providing a semiconductor substrate having a bit line contact plug and a lower electrode contact plug; Forming an interlayer insulating film on the substrate resultant; Etching the interlayer insulating layer to form a contact hole exposing a lower electrode contact plug; Sequentially forming a lower electrode and a dielectric film on the contact hole surface; Depositing a conductive film on a dielectric film and an interlayer insulating film to fill the contact hole; Forming an insulating film having an etching selectivity greater than that of the interlayer insulating film on the conductive film; Etching the conductive layer and the insulating layer to expose the interlayer insulating layer to form an upper electrode; Forming spacers on both side walls of the upper electrode; Forming a bit line contact hole by etching the interlayer insulating layer to expose the bit line contact hole; And And depositing a conductive film to fill the bit line contact holes. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed of a nitride film and the interlayer insulating film is formed of an oxide film. The method of claim 1, wherein the forming of the bit line contact hole is performed while the peripheral area of the substrate is covered with an etching mask layer.