KR100353561B1 - Method of forming interconnections in semiconductor devices - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring connection part of a semiconductor device. In particular, the contact pads of impurity diffusion regions or wirings formed in different layers are formed in an annular shape when the base layer plug is formed so that the base layer plug and the upper wiring connection plug overlap. The present invention relates to a method for forming a wiring connection part using a plug of a semiconductor device suitable for high aspect ratio and preventing misalignment of the wiring connection part through a plug and reducing the layout of the chip size. The method of forming a wire connection part of a semiconductor device according to the present invention includes forming a first insulating layer on a semiconductor substrate, forming a second insulating layer of a material having an etching rate lower than that of the first insulating layer, and Forming an etching mask exposing predetermined portions of the insulating layer, and removing the predetermined portions of the second insulating layer and the first insulating layer by isotropic etching using the etching mask to form first openings; Forming a second opening exposing the surface of the semiconductor substrate by removing the first insulating layer exposed by the first opening by an anisotropic etching using the etching mask; Forming a sidewall of a conductive material on a side of the first contact plug and filling the second opening, the first opening and the first contact plug; Forming a third insulating layer on the second insulating layer, forming a third opening to expose a surface of the first contact plug by removing a predetermined portion of the third insulating layer; Filling the third opening with a material and forming a second contact plug in contact with the first contact plug.

Description

Method of forming interconnections in semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring connection part of a semiconductor device. In particular, the contact pads of impurity diffusion regions or wirings formed in different layers are formed in an annular shape when the base layer plug is formed so that the base layer plug and the upper wiring connection plug overlap. The present invention relates to a method for forming a wiring connection part using a plug of a semiconductor device suitable for high aspect ratio and preventing misalignment of the wiring connection part through a plug and reducing the layout of the chip size.

The wiring connection part for electrically connecting the contact portion of the semiconductor device with the device or the wiring connection part for connecting the interlayer wirings formed on different insulating layers is formed in the structure and then interconnected with each other as a medium.

That is, the pad part is formed on the upper part of the plug connected to the lower layer wiring or the contact part and is electrically connected to the plug of the upper layer wiring to form the wiring connection part. The area occupied by the pad portion must be sufficiently secured to secure the overlap alignment margin between the pad portion and the upper layer wiring plug. Filling the via hole is difficult to fill sufficiently, and if the capacitor storage electrode is not planarized after forming the capacitor storage electrode in the DRAM cell, it is difficult to form a wiring due to a step with a peripheral portion.

1A to 1E are cross-sectional views illustrating a method of forming a wiring connection part of a semiconductor device according to the prior art.

Referring to FIG. 1A, a trench type field oxide film 11 defining a device isolation region and an active region is formed, and a silicon substrate 10 is a semiconductor substrate on which a cell portion CE1 and a ferry / core portion PC1 are defined. It is formed by growing a thermal oxide film for a gate insulating film.

Then, a doped polysilicon layer for gate formation is formed on the thermal oxide film by chemical vapor deposition, and then a nitride film is formed by chemical vapor deposition on a polysilicon layer with a capping insulating film. In this case, the silicide layer may be formed of tungsten or the like on the polysilicon layer.

Then, photolithography is performed on the nitride film, the polysilicon layer, and the thermal oxide film to form a cap insulating film 14 formed of a nitride film on the cell portion CE1 and a gate insulating film 12 interposed therebetween. The gate 13, which is a word line, is patterned. At this time. Although not shown, a ferry / core portion PC1 is formed with a cap insulating film made of a nitride film remaining thereon and a gate having a gate insulating film interposed therebetween.

Accordingly, the active region, which is a portion where the source / drain of the substrate 10 is to be formed, is exposed.

Then, a lightly doped drain (LDD) -implanted impurity ion implantation using the gate 13 or the like as an ion implantation mask is applied to the substrate at a low concentration, and then a material such as a capping insulating film is formed on the entire surface of the substrate 10 on which the patterns are formed. A nitride film is deposited by chemical vapor deposition to form a nitride film for sidewall formation.

Next, the nitride film is etched back to form a sidewall spacer 15 made of the nitride film remaining on the side surface of the gate 13 pattern.

Thus, the active region of the substrate on which the high concentration impurity diffusion region is to be formed is exposed.

Next, a high concentration impurity doped region is formed on the entire surface of the exposed substrate by high concentration impurity ion implantation to form a source / drain (not shown) of the transistor.

After completing the conductive transistors suitable for the cell portion CE1 and the ferry / core portion PC1, the first interlayer insulating layer 16 is thickly deposited on the entire surface of the substrate to fill the valleys between the gate patterns. In this case, BPSG, PETEOS, USG, or the like may be used as the first interlayer insulating layer 16.

Referring to FIG. 1B, a photoresist pattern (not shown) is formed to expose a predetermined portion of the first interlayer insulating layer 16 by exposure and development after coating the photoresist on the first interlayer insulating layer 16. do. At this time, the exposed portion of the first interlayer insulating layer 16 by the photoresist pattern is a portion defining the bit line contact plug forming portion of the cell portion CE1 and the doped region of the substrate on which the storage node contact plug of the capacitor is to be formed. to be.

The first interlayer insulating layer 16 made of an oxide film of a portion not protected by the photoresist pattern is removed to form contact holes exposing the impurity doped region. In this case, the nitride film 15 for forming sidewall spacers is used for automatic alignment to form contact holes.

Then, a conductive layer is formed on the first interlayer insulating layer 16 to a thickness that sufficiently fills the contact holes. In this case, the conductive layer may form the doped polysilicon by chemical vapor deposition.

Then, the conductive layer is etched back or chemical mechanical polishing so as to expose the surface of the first interlayer insulating layer 16 so that the conductive layer remains only inside the contact hole. Accordingly, the bit line contact plug 170 and the storage node contact plug 171 formed of the remaining conductive layers are formed.

Next, a second interlayer insulating layer 18 is formed by depositing an oxide film on the first interlayer insulating layer 16 including the surfaces of the plugs 170 and 171.

Referring to FIG. 1C, a gate or an impurity diffusion of the surface of the second interlayer insulating layer 18 on the bit line contact plug 170 and the ferry / core portion PC1 is formed by photoresist on the second interlayer insulating layer 18. A photoresist pattern (not shown) is formed to expose the surface of the second interlayer insulating layer 18 over the region. At this time, the portion exposed by the photoresist pattern should be formed so as to be within the range of the upper surface of the bit line contact plug 170 and the surface area of the impurity diffusion region.

Next, the surface of the bit line contact plug 170 and the impurity diffusion region are removed by removing the second interlayer insulating layer 18 and the first interlayer insulating layer 16 of the ferry / core portion PC1 which are not protected by the photoresist pattern. A first hole and a second hole are formed to expose the surface, respectively.

Then, the photoresist pattern is removed by a method such as oxygen ashing.

In addition, the empty spaces of the first and second holes are filled with a conductive material, and bit lines 190 and interconnection pads 191 are formed, respectively. At this time, the upper portion of the wiring connection pad 191 is formed after the capacitor is formed wider than the upper area of the second hole in order to secure an electrical contact margin with the upper wiring.

Next, a third interlayer insulating layer 20 is formed of an insulating material such as an oxide film on the second interlayer insulating layer 18 including the bit line 190 and the wiring connection pad 191.

Referring to FIG. 1D, anisotropic etching, such as dry etching, is performed to remove the predetermined portion of the third interlayer insulating layer 20 by photolithography to expose the surface of the storage node contact plug 171 of the capacitor. To form.

The third hole is filled with a conductive material such as doped polysilicon and then patterned to form the storage support electrode 21 on the third interlayer insulating layer 20. Subsequently, although not shown, a dielectric film and an upper electrode are formed on the surface of the storage electrode 21 to complete the capacitor.

Next, the fourth interlayer insulating layer 22 is formed on the third interlayer insulating layer 20 including the capacitor to a sufficient thickness using an oxide film or the like.

Referring to FIG. 1E, predetermined portions of the fourth interlayer insulating layer 22 and the third interlayer insulating layer 20 are removed by photolithography using anisotropic etching such as dry etching to remove the wiring connection pads 191. A fourth hole for exposing is formed.

After depositing a conductive material such as polysilicon or tungsten doped with impurities to sufficiently fill the fourth hole, a planarization process such as etch back or chemical mechanical polishing is performed so that the surface of the fourth interlayer insulating layer 22 is exposed. The connecting plug 23 is formed. At this time, the aspect ratio of the fourth hole becomes high due to the height of the capacitor or the like, making it difficult to sufficiently fill the hole.

Then, the upper wiring 24 is formed of a conductor such as aluminum or doped polysilicon so as to contact the wiring connection plug 23, and then the fifth interlayer insulating layer 25 covering the wiring 23 is formed of an oxide film or the like.

However, in the above-described method for forming a wiring connection part of a semiconductor device according to the related art, the area occupied by the pad part in order to secure the overlap alignment margin of the plug of the pad part and the upper layer wiring when the wiring connection part is indirectly formed with the substrate through the lower layer wiring. This is disadvantageous in terms of reducing chip size, and it is difficult to sufficiently fill such contact holes or via holes when the aspect ratio required by the plug of the wiring connection is high, and also to form a capacitor storage electrode in the DRAM cell. If it is not subjected to the planarization process, there is a problem in that wiring formation is difficult due to a step with a peripheral portion.

Accordingly, an object of the present invention is to form a ring-shaped contact pad of impurity diffusion regions or wirings formed in different layers to form an annular layer when the base layer plug is formed so that the base layer plug and the upper wiring connection plug overlap each other in a high aspect ratio. The present invention provides a method for forming a wiring connection portion using a plug of a semiconductor device, which is suitable and prevents misalignment of the wiring connection portion through a plug and reduces the layout of the chip size.

According to an aspect of the present invention, there is provided a method of forming a wiring connection part of a semiconductor device, the method including forming a first insulating layer on a semiconductor substrate, and using a material having a lower etching rate than that of the first insulating layer. Forming an insulating layer, forming an etching mask exposing predetermined portions of the second insulating layer, and isotropically etching the predetermined portions of the second insulating layer and the first insulating layer using the etching mask. A first etching step of removing the first opening to form a first opening, and a second opening exposing the surface of the semiconductor substrate by removing the first insulating layer exposed by the first opening by anisotropic etching using the etching mask. Forming a sidewall with a conductive material on the side of the first opening and forming a first contact plug filling the second opening; And forming a third insulating layer on the second insulating layer including the first opening and the first contact plug, and removing a predetermined portion of the third insulating layer to expose a surface of the first contact plug. And forming a second contact plug to fill the third opening with a conductive material and to contact the first contact plug.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor memory device, including a transistor including an impurity diffusion region, a gate insulating layer, and a gate in a cell portion of a semiconductor substrate in which a cell portion and a peripheral portion are defined. Forming a first insulating layer, a bit line contact plug, and a capacitor lower electrode node plug, forming a second insulating layer on the first insulating layer using an insulating material having an etching rate lower than that of the first insulating layer; Forming an etching mask exposing a predetermined portion of the second insulating layer in a periphery, and removing the exposed second insulating layer and a portion of the first insulating layer below the same by isotropic etching using the etching mask. Forming an opening and removing the first insulating layer by anisotropic etching using the etching mask Forming a second opening exposing the surface of the semiconductor substrate, removing the etching mask, and removing a predetermined portion of the second insulating layer to expose the bit line contact plug surface of the cell portion; Forming an opening, filling a third opening with a conductive material and forming a bit line to be positioned on the second insulating layer, while forming sidewalls on the side of the first opening and filling the second opening; Forming a first contact plug, and forming a third insulating layer on the second insulating layer including the bit line, the sidewall, and the first contact plug, and forming a predetermined number of the third insulating layer and the second insulating layer. Removing a portion to form a capacitor on the third insulating layer in contact with the lower electrode node contact plug, and forming a fourth insulating layer covering the capacitor. Forming on the third insulating layer, forming a fourth opening to expose the surface of the first contact plug by removing predetermined portions of the fourth and third insulating layers, and filling the fourth opening. And forming a contact plug.

1A to 1E are cross-sectional views illustrating a method of forming a wiring connection part of a semiconductor device according to the prior art.

2A through 2H are cross-sectional views illustrating a method of forming a wiring connection part including a plug of a semiconductor device according to the present invention.

Figure 3 is an enlarged cross-sectional view of the annular wiring connecting pad portion (M) of the wiring connection portion manufactured in accordance with the present invention of FIG.

In the present invention, when forming a contact for the electrical connection between the first wiring and the underlying layer formed on a predetermined layer, the contact of the region other than the cell portion is first wet-etched and then dry-etched the site where the pad of the wiring connection portion is to be formed. The cross section of the contact hole is formed to have a stepped profile, and then a side wall is formed on the stepped portion together with the contact plug to form a pad, thereby preventing misalignment when wiring to the upper layer wiring.

Therefore, the present invention is suitable for manufacturing a high-density device by reducing the size of the layout by forming an annular plug pad to lower the high aspect ratio when forming the wiring connection for the electrical connection between the wiring.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are cross-sectional views illustrating a method of forming a wiring connection part including a plug of a semiconductor device according to the present invention.

Referring to FIG. 2A, a trench type field oxide layer 31 defining a device isolation region and an active region is formed, and is formed on a silicon substrate 30, which is a semiconductor substrate on which a cell portion CE2 and a ferry / core portion PC2 are defined. It is formed by growing a thermal oxide film for a gate insulating film.

Then, a doped polysilicon layer for gate formation is formed on the thermal oxide film by chemical vapor deposition, and then a nitride film is formed by chemical vapor deposition on a polysilicon layer with a capping insulating film. In this case, the silicide layer may be formed of tungsten or the like on the polysilicon layer.

Then, photolithography is performed on the nitride film, the polysilicon layer, and the thermal oxide film to form a cap insulating film 34 formed of a nitride film on the cell portion CE2 and a gate insulating film 32 interposed therebetween. The gate 33, which is a word line, is patterned. At this time. Although not shown, the ferry / core portion PC2 is formed with a cap insulating film formed of a nitride film remaining on the upper portion and a gate having a gate insulating film interposed therebetween.

Accordingly, the active region, which is a portion where the source / drain of the substrate 30 is to be formed, is exposed.

Then, a lightly doped drain (LDD) formation impurity ion implantation using the gate 33 or the like as an ion implantation mask is applied to the substrate at a low concentration, and then a material such as a capping insulating film is formed on the entire surface of the substrate 30 on which the patterns are formed. A nitride film is deposited by chemical vapor deposition to form a nitride film for sidewall formation.

Next, the nitride film is etched back to form a sidewall spacer 35 made of the nitride film remaining on the side surface of the gate 33 pattern.

Thus, the active region of the substrate on which the high concentration impurity diffusion region is to be formed is exposed.

Next, a high concentration impurity doped region is formed by implanting high concentration impurity ions onto the exposed substrate to complete the source / drain (not shown) of the transistor.

After completing the conductive transistors suitable for the cell portion CE2 and the ferry / core portion PC2, the first interlayer insulating layer 36 is thickly deposited on the entire surface of the substrate 30 to fill the valleys between the gate patterns. In this case, BPSG, PETEOS, USG, or the like may be used as the first interlayer insulating layer 36.

Referring to FIG. 3B, after the photoresist is applied on the first interlayer insulating layer 36, the first interlayer insulating layer is formed by exposure and development using an exposure mask defining a bit line contact plug and a storage node contact plug forming portion. A photoresist pattern (not shown) that exposes a predetermined portion of 36 is formed. At this time, the exposed portion of the first interlayer insulating layer 36 by the photoresist pattern is a portion defining the bit line contact plug forming portion of the cell portion CE2 and the doped region of the substrate on which the storage node contact plug of the capacitor is to be formed. to be.

The first interlayer insulating layer 36 made of an oxide film of a portion not protected by the photoresist pattern is removed by anisotropic etching such as a dry time to form contact holes exposing impurity doped regions. At this time, the sidewall spacers 35 formed of a nitride film formed on the side of the gate 33 are used to form self-aligned contact holes. In other words, the first interlayer insulating layer 36 made of an oxide film and the sidewall spacer 35 made of a nitride film are used for self-alignment.

Then, a conductive layer is formed on the first interlayer insulating layer 16 to a thickness that sufficiently fills the contact holes to form the bit line contact plug and the storage node contact plug. In this case, the conductive layer may be formed by depositing doped polysilicon by chemical vapor deposition.

Then, the conductive layer is etched back or chemical mechanical polishing to expose the surface of the first interlayer insulating layer 36 so that the conductive layer remains only in the contact hole and the first interlayer insulating layer 36 Level the surface. Accordingly, the bit line contact plug 370 and the storage node contact plug 371 formed of the remaining conductive layers are formed.

Next, a second interlayer dielectric 38 is deposited on the first interlayer insulating layer 36 including the surfaces of the plugs 370 and 371 with an oxide film to form a predetermined thickness. The insulating layer 38 is formed of an insulating layer having a smaller etching ratio to wet etching than the first interlayer insulating layer 36.

Referring to FIG. 2C, a photoresist pattern exposing the gate of the ferry / core portion PC2 or the surface of the second interlayer insulating layer 38 on the impurity diffusion region with photoresist on the second interlayer insulating layer 38 ( 39). At this time, the photoresist pattern 39 is coated with a photoresist on the planarized second interlayer insulating layer 38 and then subjected to exposure and development using an exposure mask defining a contact hole formation region of the ferry / core portion PE2. In this case, a predetermined portion of the interlayer insulating layer 38 positioned on the impurity diffusion region of the second substrate 30 is exposed. That is, the portion exposed by the photoresist pattern 39 should be formed to be within the upper region range of the impurity diffusion region.

Referring to FIG. 2D, wet etching is performed on the second interlayer insulating layer 38 of the ferry / core part PE2 which is not protected by the photoresist pattern 39 and a portion of the first interlayer insulating layer 36 disposed under the ferrite / core part PE2. Removal to form the first opening H1. At this time, since the wet etch rate of the second interlayer insulating layer 38 is smaller than the wet etch rate of the first interlayer insulating layer 36, the second interlayer insulating layer 38 during wet etching under such etching conditions. ) Is etched first and the etching progresses to a certain degree so that the first interlayer insulating layer 36 is exposed and starts to be etched, the etching rate of the first interlayer insulating layer 36 is higher than that of the second interlayer insulating layer 38. Since it is fast, the amount of etching in the vertical direction increases.

Accordingly, a first opening H1 having a puddle shape under-etched under the photoresist pattern 39 is formed, which is an area in which a pad of the wiring connection part is to be formed.

Then, anisotropic etching such as dry etching using the photoresist pattern 39 as an etching mask is performed on the exposed first interlayer insulating layer 36 to expose the impurity diffusion region (not shown) of the substrate 30. The second opening portion H2 is formed.

As a result, in the embodiment of the present invention, a first plug to be connected to the wiring connecting pad is formed in the first opening H1 by a subsequent process, and the lower end and the wiring of the second plug to be connected to the upper wiring in the second opening H2. The connection pad is formed. That is, since the cross section of the portion where the first opening portion H1 and the second opening portion H2 meet has a stepped profile, the step portion provides a space for the side wall to be formed, and the first opening portion H1 is wet. It is formed as is because the area of the upper portion is lowered the aspect ratio.

Referring to FIG. 2E, after removing the photoresist pattern by a method such as oxygen ashing (O ₂ ashing), the photoresist is coated on the entire surface of the substrate 30, and then exposed and developed to expose the bit line of the cell portion CE2. A photoresist pattern exposing the second interlayer insulating layer 38 on the plug 370 is formed.

Next, the second interlayer insulating layer 38 of the portion not protected by the photoresist pattern is removed to form a third opening that exposes the surface of the bit line contact plug 370, and then the photoresist pattern is removed.

The conductive layer 40 is formed on the surface of the second interlayer insulating layer 38 with a conductive material such as polysilicon doped to fill the empty spaces of the first and second openings H1 and H2 and the third opening. Form. At this time, in the case of using polysilicon is formed by vapor deposition by chemical vapor deposition.

Referring to FIG. 2F, a photoresist is applied on the conductive layer, and then a photoresist pattern 41 covering the conductive layer portion of the bit line forming portion is formed by exposure and development using an exposure mask for forming a bit line. At this time, the surface of the conductive layer positioned on the first and second openings formed in the ferry / core portion PE2 is exposed as it is.

The bit line 400 is formed by removing the conductive layer of the portion not protected by the photoresist pattern 41 by anisotropic etching such as dry etching. At this time, the conductive layers formed in the first and second openings of the ferry / core portion PE2 are etched back by anisotropic etching to partially remain in the stepped portions of the first opening H10 to form an annular sidewall 401. At the same time, most of the second openings remain to form the first contact plug 402.

Accordingly, the side wall 401 made of the conductive layer remaining in the first opening H10 becomes an interconnection pad 401, which is formed by interconnecting the first contact plug and the first contact plug during interconnection of the wiring fabricated after the formation of the storage electrode. 2 It increases the overlap margin of contact plug.

Referring to FIG. 2G, an oxide film or the like is formed on the second interlayer insulating layer 38 including the bit line 400, the wiring connection pad 401, and the first contact plug 402. It is formed of insulating material.

A fourth opening for exposing a surface of the storage node contact plug 371 of the capacitor by removing a predetermined portion of the third interlayer insulating layer 42 by photolithography is formed using anisotropic etching such as dry etching. .

The fourth opening is filled with a conductive material such as doped polysilicon and then patterned to form a storage electrode 43 made of the remaining conductive impurity on the third interlayer insulating layer 42. Subsequently, although not shown, a dielectric film and an upper electrode are formed on the surface of the storage electrode 43 to complete the capacitor.

Next, the fourth interlayer insulating layer 44 is formed on the third interlayer insulating layer 43 including the capacitor to a sufficient thickness using an oxide film or the like.

Referring to FIG. 2H, predetermined portions of the fourth interlayer insulating layer 44 and the third interlayer insulating layer 42 are removed by photolithography using anisotropic etching, such as dry etching, to form a wiring connection pad 401. A fifth opening is formed to expose the top surface of the first contact plug 402. At this time, since the wiring connection pads 401 are formed in an annular shape and buried in the second interlayer insulating layer 38, an overlap alignment margin between the fifth opening and the first opening is ensured.

After depositing a conductive material such as polysilicon or tungsten doped with impurities to sufficiently fill the fifth opening, a planarization process such as etch back or chemical mechanical polishing is performed to expose the surface of the fifth interlayer insulating layer 44. A second contact plug 45 for connection is formed.

Then, the upper wiring 46 is formed of a conductor such as aluminum or doped polysilicon so as to contact the second contact plug 45 for wiring connection, and then the fifth interlayer insulating layer 47 covering the second contact plug 45 is formed of an oxide film or the like. Form.

FIG. 3 is an enlarged cross-sectional view of the annular wiring connecting pad part M of the wiring connection part manufactured according to the present invention of FIG. 2.

Referring to FIG. 3, the outermost portion of the first concentric circle 401 represents the wiring connection pad 401, and the second concentric circle 402 located next represents the first contact plug 402. The positioned third concentric circle 45 represents the second contact plug 45.

At this time, the distance OM between the circumference of the third concentric circle 45 and the outer circumference of the first concentric circle 401 becomes the overlapping margin of the second contact plug 45 and the first contact plug 402.

Accordingly, the present invention facilitates the process of forming a plug in the contact hole by reducing the aspect ratio of the contact hole in which the wiring connection portion between the wiring and the substrate is formed, and forms the wiring connection pad together with the bit line, but the cell design rules Since it is designed independently of the negative design rule, there is an advantage of reducing the overall chip size by reducing the required area for wiring connection formation.

Claims (9)

Forming a first insulating layer on the semiconductor substrate, Forming a second insulating layer of a material having an etching rate lower than that of the first insulating layer; Forming an etching mask exposing a predetermined portion of the second insulating layer; A first etching step of forming a first opening by isotropic etching to remove predetermined portions of the second insulating layer and the first insulating layer using the etching mask; Removing the first insulating layer exposed by the first opening by anisotropic etching using the etching mask to form a second opening exposing the surface of the semiconductor substrate; Forming a first contact plug on a side of the first opening with a conductive material and filling the second opening; Forming a third insulating layer on the second insulating layer including the first opening and the first contact plug; Removing a predetermined portion of the third insulating layer to form a third opening exposing the surface of the first contact plug; Forming a second contact plug filling the third opening with a conductive material and in contact with the first contact plug. The method of claim 1, wherein the first insulating layer and the second insulating layer are formed of oxide films having different etching selectivity. The method of claim 1, wherein the first etching is performed so that the surface of the semiconductor substrate is not exposed. The method of claim 1, wherein the forming of the sidewall and the first contact plug, Forming a conductive layer on the second insulating layer including the first and second openings; And etching the conductive layer to expose the surface of the second insulating layer. The method of claim 4, wherein the sidewall and the first contact plug are formed simultaneously with the bit line of the DRAM cell. The method of claim 1, wherein the semiconductor substrate includes a lower wiring and a portion exposed by the second opening is the lower wiring. The method of claim 1, wherein after forming the second contact plug, And forming an upper wiring on the third insulating layer so as to be in contact with the surface of the second contact plug. In the method of manufacturing a semiconductor memory device, Forming a transistor including an impurity diffusion region, a gate insulating film, and a gate, a first insulating layer covering the transistor, a bit line contact plug, and a capacitor lower electrode node plug in the cell portion of the semiconductor substrate having a cell portion and a peripheral portion defined therein; Forming a second insulating layer on the first insulating layer using an insulating material having an etching rate lower than that of the first insulating layer; Forming an etching mask exposing a predetermined portion of the second insulating layer of the peripheral portion; Removing the exposed second insulating layer and a portion of the first insulating layer under the isotropic etching using the etching mask to form a first opening; Forming a second opening exposing the surface of the semiconductor substrate by removing the first insulating layer by anisotropic etching using the etching mask; Removing the etching mask; Removing a predetermined portion of the second insulating layer to form a third opening that exposes the bit line contact plug surface of the cell portion; Forming a bit line filling the third opening with a conductive material and positioned on the second insulating layer, and forming a sidewall at the side of the first opening and forming a first contact plug filling the second opening; Wow, A third insulating layer is formed on the second insulating layer including the bit line, the sidewall, and the first contact plug, and a predetermined portion of the third insulating layer and the second insulating layer is removed to contact the lower electrode node. Forming a capacitor on the third insulating layer in contact with the plug; Forming a fourth insulating layer on the third insulating layer, the fourth insulating layer covering the capacitor; Removing a predetermined portion of the fourth and third insulating layers to form a fourth opening exposing the surface of the first contact plug; And forming a second contact plug filling the fourth opening. The method of claim 8, wherein the forming of the fourth opening is performed by using the sidewall as an overlap alignment margin with the first contact plug.