KR20040056958A - Method for MIM capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming an MIM(Metal/Insulator/Metal) capacitor of a semiconductor device is provided to improve process margin and flatness by simultaneously patterning a metal line and an electrode for the MIM capacitor. CONSTITUTION: A lower electrode forming substance, a dielectric substance and an upper electrode forming substance are sequentially deposited on a semiconductor substrate(31). An upper electrode is formed by selectively patterning the upper electrode forming substance. The dielectric film is formed by selectively etching the dielectric substance. An MIM capacitor(39) and a metal interconnection(38) are simultaneously formed by patterning the resultant structure using a photoresist pattern for defining a capacitor forming region and a metal interconnection forming region.

Description

MIM capacitor formation method of a semiconductor device {Method for MIM capacitor of semiconductor device}

The present invention relates to a semiconductor device, and more particularly, to a method of forming a MIM capacitor of a semiconductor device capable of increasing process margin and planarization characteristics by simultaneously patterning a metal line and an electrode for forming a MIM capacitor.

BACKGROUND ART Recently, a merged memory logic (MML) is a device in which a memory cell array unit such as a dynamic random access memory (DRAM) and an analog or peripheral circuit are integrated together in a chip.

Due to the emergence of such composite semiconductor devices, multimedia functions have been greatly improved, and thus, higher integration and higher speed of semiconductor devices have been achieved.

Meanwhile, in an analog circuit requiring high speed operation, development of a semiconductor device for implementing a high capacity capacitor is underway.

When the capacitor has a PIP (Polysilicon / Insulator / Polysilicon) structure, since the upper electrode and the lower electrode are used as the conductive polysilicon, an oxidation reaction occurs at the interface between the upper electrode and the lower electrode and the dielectric thin film, so that a natural oxide film is formed and thus the size of the total capacitance. There is a disadvantage that is reduced.

In order to solve this problem, the structure of the capacitor was changed from MIS (Metal / Insulator / Silicon) to MIM (Metal / Insulator / Metal). It is mainly used for high performance semiconductor devices.

Since the MIM type analog capacitor must be implemented at the same time as other semiconductor devices, the MIM type analog capacitors are electrically connected to the semiconductor devices through metal wires, which are interconnection lines.

Hereinafter, a MIM capacitor according to the related art will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views for forming a MIM capacitor of a semiconductor device of the prior art, and FIG. 2 is a block diagram illustrating a bridge short circuit phenomenon of the MIM capacitor according to the prior art process.

Analog capacitors in high-precision CMOS IC logic devices are a key element in advanced analog MOS technology, especially A / D converters and switched capacitor filters.

As the electrode structure of such a capacitor, various capacitor structures such as polysilicon / polysilicon, polysilicon / silicon, metal / silicon, metal / polysilicon, and metal / metal have been used.

Among them, metal / metal structures are widely used as analog capacitor structures due to their low thermal budget and low VCC.

First, as shown in FIG. 1A, a material layer 12 for forming a lower electrode, a dielectric material layer 13, and a material layer 14 for forming an upper electrode are deposited on a semiconductor substrate 11. .

As shown in FIG. 1B, the dielectric material layer 13 and the upper electrode forming material layer 14 are selectively etched using the first photoresist pattern 15 as a mask to form the MIM capacitor upper electrode 14a. The dielectric layer 13b is formed.

Subsequently, as shown in FIG. 1C, the MIM capacitor lower electrode 12a is formed by selectively etching the lower electrode forming material layer 12 using the second photoresist pattern 16.

As shown in FIG. 1D, an IMD (Inter Metal Dielectric) layer 17 is formed on the entire surface and planarized by a chemical mechanical polishing (CMP) process.

Subsequently, as shown in FIG. 1E, the IMD layer 17 is selectively patterned to form via holes.

Contact vias 18a and 18b are formed in the via holes to contact the MIM capacitor lower electrode 12a and the MIM capacitor upper electrode 14a, and the metal wires 19 connected to the contact plugs 18a and 18b are formed. Form.

Such MIM structure has the following process limitations.

First, it is necessary to be able to uniformly etch a material layer for forming a lower thickness upper electrode.

Second, endpoint detection of the thickness change of the upper electrode of the MIM capacitor should be easy.

Third, the etching margin should be large during the etching process of the material layer for forming the upper electrode using a dielectric material having an excellent etching selectivity.

Such process limitations result in a long development cycle since endpoint and over-etch margins change according to the pattern density of the upper electrode forming material layer during the development of a specific device.

In addition, when the thickness of the upper electrode forming material layer is increased, the IMD step increases, which is disadvantageous in terms of planarization.

However, the MIM capacitor forming process of the semiconductor device of the prior art has the following problems.

In the prior art, when the high pressure equipment is used during the etching process of the dielectric layer, a dielectric undercut of the pattern sidewall portion may occur, and in such a case, an electric field concentration may occur in the portion.

Breakdown occurs even at low voltages due to field concentration.

In the case of using low pressure equipment, sputtering occurs more severely than high pressure equipment, and the lower electrode forming material sputters, causing redeposition on the sidewall of the MIM pattern, thereby generating bridge short. Can be.

Due to process limitations, the end point and the over-etch margin change depending on the pattern density of the upper electrode forming material layer during the development of a specific device, thereby increasing the development cycle.

The present invention has been made to solve the problem of the MIM capacitor formation process of the prior art semiconductor device, a semiconductor device to improve the process margin and planarization characteristics by simultaneously patterning the metal line and the electrode for MIM capacitor formation Its purpose is to provide a method of forming a MIM capacitor.

1A-1E are cross-sectional views of a process for forming a MIM capacitor of a semiconductor device of the prior art.

2 is a block diagram showing a bridge short circuit phenomenon of the MIM capacitor according to the prior art process.

3A to 3E are cross-sectional views of a process for forming a MIM capacitor of a semiconductor device according to the present invention.

-Explanation of symbols for the main parts of the drawing-

31. Semiconductor substrate 32. Material layer for forming lower electrode

32a. Bottom electrode 33. Dielectric layer

33a. Dielectric Layer 34. First Photoresist Pattern

35. Material layer for forming the upper electrode 35a. Upper electrode

36. Second Photoresist Pattern Layer 38. Metal Wiring

38.MIM Capacitor

According to an aspect of the present invention, there is provided a method of forming a MIM capacitor of a semiconductor device, comprising sequentially depositing a lower electrode forming material layer, a dielectric material layer, and an upper electrode forming material layer on a semiconductor substrate; Selectively etching the upper electrode forming material layer so as to remain only in the capacitor forming region; Selectively wet etching the dielectric material layer so as to remain only in the capacitor formation region to remove the dielectric material layer in the metallization formation region; Defining and selectively etching the capacitor formation region and the metal wiring formation region to simultaneously pattern the MIM capacitor on which the lower electrode, the dielectric layer, and the upper electrode are stacked and the metal wiring; To provide.

That is, according to the method of forming a MIM capacitor of a semiconductor device according to the present invention, the over-electrode in the step of selectively etching the upper electrode forming material layer to remain only in the capacitor formation region, during the over-etching of the lower dielectric material layer The remaining portion of the dielectric material layer is removed by wet selectivity with high selectivity, thereby preventing undercut phenomenon or short bridging phenomenon in the sidewell region of the MIM capacitor.

In the method of forming a MIM capacitor of a semiconductor device according to the present invention, in the step of simultaneously patterning the MIM capacitor and the metal wiring, a photosensitive film pattern is formed separately on the upper electrode of the MIM capacitor so that the edge region of the upper electrode is more etched. It is desirable to. Accordingly, when the dielectric material layer of the metal line formation region is removed by the wet etching, an undercut may be prevented from occurring under the upper electrode due to the nature of the wet etching, thereby preventing the electric field concentration phenomenon from occurring under a high operating voltage.

Hereinafter, with reference to the accompanying drawings, it will be described in detail an embodiment of a method for forming a MIM capacitor of a semiconductor device according to the present invention. However, the scope of the present invention is not limited thereto, but is presented as an example.

3A to 3E are cross-sectional views for forming a MIM capacitor of a semiconductor device according to the present invention.

According to the manufacturing method according to the present invention, in the same manner as in the prior art, first, as shown in Figure 3a, the lower electrode forming material layer 32, the dielectric material layer 33 on the semiconductor substrate 31 In addition, the upper electrode forming material layer 35 is sequentially deposited to form a MIM capacitor stacked pattern.

As shown in FIG. 3B, the upper electrode 35a of the MIM capacitor is patterned by selectively etching the upper electrode forming material layer 35 using the first photoresist pattern 34 as a mask. When etching the upper electrode of the MIM capacitor, a portion of the lower dielectric material layer 32 is over-etched.

Subsequently, as shown in FIG. 3C, during patterning of the upper electrode 35a of the MIM capacitor, the dielectric material layer 33 of the remaining metal line forming region is removed by wet etching having a high selectivity. Accordingly, undercut phenomenon and short bridging phenomenon are prevented from occurring in the lower sidewell region of the upper electrode 35a.

After removing the dielectric material layer 33 of the metal wiring forming region, as shown in FIG. 3D, the photoresist is applied to the entire resultant, followed by an exposure and development process to perform the MIM capacitor forming region and the metal wiring forming region. The second photoresist pattern 36 is formed to define this. The MIM capacitor in which the lower electrode forming material layer 32 is selectively etched using the second photoresist pattern 36 to stack the lower electrode 32a, the dielectric layer 33a, and the upper electrode 35a ( 39 and the metal wiring 38 are simultaneously patterned, and the second photoresist pattern 36 of the MIM capacitor formation region is formed by patterning the edge region of the upper electrode 35a to be etched. Accordingly, the edge region of the upper electrode is further removed, such as "A", and when the dielectric material layer of the metal wiring forming region is removed by the wet etching, an undercut generated under the upper electrode due to the wet etching characteristics is removed. As a result, when the device is driven under a high operating voltage, the electric field is prevented from concentrating on the undercut portion.

Subsequently, as shown in FIG. 3E, the second photoresist pattern is removed to form metal wiring and a MIM capacitor.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

The MIM capacitor forming method of the semiconductor device according to the present invention described above has the following effects.

After patterning the upper electrode of the MIM capacitor, the remaining dielectric material layer on the upper portion of the metal wiring formation region is removed by wet etching with a high selectivity, thereby suppressing undercut and short bridges on the sidewall of the upper electrode, thereby reducing the operation characteristics and There is an effect of improving the reliability.

Claims (2)

Continuously depositing a lower electrode forming material layer, a dielectric material layer and an upper electrode forming material layer on a semiconductor substrate; Selectively etching the upper electrode forming material layer so as to remain only in the capacitor forming region; Selectively wet etching the dielectric material layer so as to remain only in the capacitor formation region to remove the dielectric material layer in the metallization formation region; Defining and selectively etching the capacitor formation region and the metal wiring formation region to simultaneously pattern the MIM capacitor on which the lower electrode, the dielectric layer, and the upper electrode are stacked and the metal wiring; . 2. The MIM of the semiconductor device according to claim 1, wherein in the step of simultaneously patterning the MIM capacitor and the metal wiring, a photosensitive film pattern is separately formed and patterned so that an edge region of the upper electrode is etched on the upper electrode of the MIM capacitor. How to form a capacitor.