CN110504284A - Columnar capacitor array structure and preparation method - Google Patents
Columnar capacitor array structure and preparation method Download PDFInfo
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- CN110504284A CN110504284A CN201810471970.8A CN201810471970A CN110504284A CN 110504284 A CN110504284 A CN 110504284A CN 201810471970 A CN201810471970 A CN 201810471970A CN 110504284 A CN110504284 A CN 110504284A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 60
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- 238000003491 array Methods 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
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- 229910052712 strontium Inorganic materials 0.000 claims description 4
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- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
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- 239000002131 composite material Substances 0.000 claims description 3
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 9
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- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 9
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- 238000000151 deposition Methods 0.000 description 8
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- 229910002370 SrTiO3 Inorganic materials 0.000 description 4
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- -1 Ru (ruthenium) Chemical class 0.000 description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 3
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- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 3
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 3
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- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- LKJPSUCKSLORMF-UHFFFAOYSA-N Monolinuron Chemical compound CON(C)C(=O)NC1=CC=C(Cl)C=C1 LKJPSUCKSLORMF-UHFFFAOYSA-N 0.000 description 2
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
Abstract
The present invention provides a kind of columnar capacitor array structure and preparation method thereof, and preparation method includes: offer semiconductor substrate, including several contact pads；Sacrificial layer is formed, including the first material layer and second material layer being alternately superimposed on；Etching sacrificial layer, to form capacitor hole, capacitor hole has corrugated or indented sidewall；Form electrode under filling perforation；Deposited stent supporting layer opens bracket supporting layer in a manner of Self-aligned etching；Form capacitor dielectric layer and upper electrode layer；Form top electrode obturator.The present invention can further reduce capacitor size, there is larger remaining space between adjacent capacitor, electrode under side wall is corrugated or jagged column is formed, the surface area of capacitor can be increased, improve capacitive energy, it is miniature to adapt to size, broken line type bracket supporting layer is formd using self aligned etching technics, increases the contact area of supporting layer and capacitor arrangement, improves support strength, and preparation process is simplified, improve the accuracy of device preparation.
Description
Technical field
The invention belongs to technical field of integrated circuits, more particularly to a kind of columnar capacitor array structure and preparation side
Method.
Background technique
Dynamic RAM (Dynamic Random Access Memory, referred to as: DRAM) is commonly used in computer
Semiconductor storage unit, be made of many duplicate storage units.In 20nm DRAM processing procedure below, DRAM is mostly used greatly
The capacitor structure of stacking-type, capacitor (Capacitor) are the cylindrical shapes of vertical high-aspect-ratio.
Currently, as shown in Figure 1, two-sided capacitance structure includes substrate 11, contact pad 12, lower electrode layer 13, capacitor dielectric
Layer 14 and upper electrode layer 15, wherein the two-sided capacitor of Cylinder is current main industry technology, cylindrical in array region
Bottom and deposited on sidewalls lower electrode material in deep hole, then using every three deep holes as basic unit, top aperture will in its center
The lower electrode of connection separates, and is formed using SiN as the rack for test tube structure of supporting layer, high k dielectric is deposited in deep hole
(high dielectric material) and upper electrode material are with the reduction of technology node size, this capacitor production program is in technique
It is difficult to realize, in the technical method of existing production capacitor, the diminution of capacitor size can bring that technical difficult and it is deposited
The reduction of charge capability is stored up, therefore, pillar capacitor (column capacitor) is made as future thrust, however, existing Pillar
Capacitor is there are the lower defect of electrode plate surface product, and accomplishing bigger depth-to-width ratio, there is biggish technical difficulty, meanwhile, it is advanced
The support of the capacitor of wide ratio is also urgent problem to be solved in the industry.
Therefore, how a kind of columnar capacitor array structure and preparation method are provided, with solve in the prior art capacitor it
Between the problems such as remaining space is smaller, dimensional contraction is small and capacitor relative surface area is small, support construction is complicated be necessary.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of columnar capacitor array structures
And preparation method, for solving between capacitor in the prior art, remaining space is smaller, dimensional contraction is small and capacitor is with respect to table
The problems such as area is small, support construction is complicated.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation side of columnar capacitor array structure
Method includes the following steps:
1) semi-conductive substrate is provided, the semiconductor substrate includes the Contact welding that several are located in memory array structure
Disk；
2) sacrificial layer is formed in Yu Suoshu semiconductor substrate, the sacrificial layer includes the first material layer being alternately superimposed on and
Two material layers, under default etching condition, the etch rate of the first material layer is greater than the etching speed of the second material layer
A wherein second material layer for rate, the sacrificial layer is served as a contrast relative to the first material layer closer in the semiconductor
Bottom；
3) the graphical sacrificial layer is to form capacitor hole, wherein the capacitor hole appears the contact pad, and described
Capacitor hole has the lateral past first material layer recessed corrugated or indented sidewall；
4) each capacitor hole is filled to form electrode under filling perforation, and the upper surface of electrode is higher than the sacrifice under the filling perforation
The upper surface of layer, and there is between electrode spacing under the filling perforation in the adjacent capacitor hole；
5) surface of the structure obtained in step 4) deposits a bracket supporting layer, and fills out described in bracket supporting layer covering
The sacrificial layer for being higher by surrounding them under portion and the filling perforation of electrode under hole；
6) in forming at least one opening on the bracket supporting layer in a manner of Self-aligned etching, to open the bracket
Supporting layer, and the sacrificial layer is removed based on the opening；
7) surface of the structure obtained in step 6) forms capacitor dielectric layer, and is formed in the surface of the capacitor dielectric layer
Upper electrode layer, the capacitor dielectric layer is corrugated or zigzag covers the side wall of electrode under the filling perforation；And
8) surface of Yu Suoshu upper electrode layer forms top electrode obturator, and the top electrode obturator is filled in adjacent institute
The gap between upper electrode layer is stated, and is electrically connected with the upper electrode layer.
As a preferred solution of the present invention, between step 1) and step 2) further include: Yu Suoshu semiconductor substrate table
Face forms a separation layer, and the sacrificial layer in step 2) is formed in the surface of the separation layer.
As a preferred solution of the present invention, the thickness of the separation layer is between 5nm~45nm；The separation layer
Include silicon nitride layer；The separation layer is formed using one of atomic layer deposition and low-pressure chemical vapor deposition.
As a preferred solution of the present invention, in step 2), the first material layer includes boron doped silicon oxide layer,
The second material layer includes silicon oxide layer.
As a preferred solution of the present invention, in step 2), the thickness of the second material layer is between first material
Between 1.5~3 times of thickness of feed layer.
As a preferred solution of the present invention, the thickness of the first material layer is between 3nm~30nm, and described
The thickness of two material layers is between 20nm~50nm；The thickness of the sacrificial layer is between 1 μm~1.5 μm.
As a preferred solution of the present invention, between step 2) and step 3) further include: the surface of Yu Suoshu sacrificial layer
A protection supporting layer is formed, and the protection supporting layer is etched based on the Patterned masking layer simultaneously in step 3).
As a preferred solution of the present invention, in step 3), the specific steps for forming the capacitor hole include:
3-1) in the Patterned masking layer for forming the window with array arrangement in the structure that step 2) obtains, and based on institute
It states Patterned masking layer and the sacrificial layer is etched using the technique of dry etching, it is perforative up and down to be formed in the sacrificial layer
Through-hole, the through-hole through-hole corresponding and described with the window appear the contact pad；
3-2) use the technique etch step 3-1 of wet etching) side wall of the through-hole that is formed, to form side wall in wave
Line shape or the jagged capacitor hole.
As a preferred solution of the present invention, in step 4), the specific steps for forming electrode under the filling perforation include:
The continuous lower electrode material of sacrificial layer surface deposition 4-1) in Yu Suoshu capacitor hole and around the capacitor hole
The bed of material；
Aperture mask layer 4-2) is formed on Yu Suoshu lower electrode material layer, the aperture mask layer includes that several apertures are covered
Film unit, wherein the aperture mask cell is corresponding with the contact pad, and the lateral dimension of the aperture mask cell is big
In the lateral dimension of the contact pad；
The lower electrode material layer 4-3) is etched based on the aperture mask layer, to divide the lower electrode material layer, shape
At electrode under the filling perforation between adjacent with spacing.
As a preferred solution of the present invention, step 4-3) in further include: while etching the lower electrode material layer,
Further etch the part sacrificial layer being in contact with the lower electrode material layer.
As a preferred solution of the present invention, in step 4), under the filling perforation electrode include be alternately superimposed on it is first straight
Diameter portion and second diameter portion, wherein the first diameter portion is formed based on the first material layer of the sacrificial layer, and described second is straight
Diameter portion is formed based on the second material layer of the sacrificial layer, and the lateral dimension in the first diameter portion is greater than the second diameter
The lateral dimension in portion.
As a preferred solution of the present invention, the lateral dimension in the first diameter portion is between 40nm~105nm,
The lateral dimension of the second diameter portion is between 35nm~100nm.
As a preferred solution of the present invention, the lateral dimension in the first diameter portion is between the second diameter portion
Between 1.08~1.18 times of lateral dimension.
As a preferred solution of the present invention, in step 6), the specific steps for opening the bracket supporting layer include:
6-1) Yu Suoshu bracket support layer surface forms hole pattern mask layer, and described hole graphic mask layer includes several
The hole of a array arrangement, wherein described hole appears being located on the sacrificial layer between electrode under the adjacent filling perforation
The bottom of the bracket supporting layer and the side for the bracket supporting layer being connected with the bottom；
It 6-2) is based on described hole graphic mask layer, is etched in a manner of Self-aligned etching and using the technique of dry etching
The bracket supporting layer, in forming at least one described opening corresponding with described hole on the bracket supporting layer, with
Open the bracket supporting layer.
As a preferred solution of the present invention, step 6-1) in, described hole is arranged in uniform intervals, and each described
Hole overlaps mutually with electrode under three adjacent filling perforations simultaneously.
As a preferred solution of the present invention, in step 7), the dielectric constant of the capacitor dielectric layer is between 4~400
Between；The lamination that the capacitor dielectric layer choosing is constituted from laminated construction, aluminium oxide and the hafnium oxide that strontium titanates and titanium oxide are constituted
One of laminated construction and compound calcium nutrition Ferroelectric material that structure, zirconium oxide and aluminium oxide are constituted；The capacitor is situated between
The thickness of matter layer is between 10nm~85nm；The thickness of the upper electrode layer is between 15nm~95nm.
As a preferred solution of the present invention, after step 8) further include: Yu Suoshu top electrode obturator surface is formed
Top electrode coating.
As a preferred solution of the present invention, in step 8), it is also formed with air chamber in the top electrode obturator, and
The air chamber is between the adjacent upper electrode layer.
The present invention also provides a kind of columnar capacitor array structures, comprising:
Semiconductor substrate, the semiconductor substrate include the contact pad that several are located in memory array structure；
Electrode under filling perforation is incorporated on the contact pad, and electrode has electrode cylinder and in the electricity under the filling perforation
Be higher by portion on pole body, and the electrode cylinder side wall is corrugated or zigzag；
Capacitor dielectric layer is formed under the filling perforation the described of surrounding them under the side wall of electrode and the filling perforation and partly leads
In body substrate；
Upper electrode layer is formed in the capacitor dielectric layer surface；And
Top electrode obturator is filled in the gap between the adjacent upper electrode layer, and is electrically connected with the upper electrode layer.
As a preferred solution of the present invention, the columnar capacitor array structure further includes bracket supporting layer, described
Bracket supporting layer at least covers the described of electrode under each filling perforation and is higher by portion, and the capacitor dielectric layer be consecutively formed at it is described
Under filling perforation under the surface and the filling perforation of electrode and the bracket supporting layer in the semiconductor substrate of surrounding them.
As a preferred solution of the present invention, the columnar capacitor array structure further includes protection supporting layer, described
Protection supporting layer is placed on the periphery of the electrode cylinder, and the upper surface of the protection supporting layer and the following table for being higher by portion
Face is in contact.
As a preferred solution of the present invention, one is also formed between the semiconductor substrate and the capacitor dielectric layer
Separation layer.
As a preferred solution of the present invention, the electrode cylinder of electrode includes be alternately superimposed under the filling perforation
One diameter portion and second diameter portion, wherein the lateral dimension in the first diameter portion is greater than the lateral ruler of the second diameter portion
It is very little.
As a preferred solution of the present invention, the columnar capacitor array structure further includes top electrode coating, institute
State the surface that top electrode coating is formed in the top electrode obturator.
As a preferred solution of the present invention, air chamber, and the air are also formed in the top electrode obturator
Chamber is between the adjacent upper electrode layer.
The present invention also provides a kind of organization of semiconductor memory, the organization of semiconductor memory includes as above-mentioned any one
Columnar capacitor array structure described in item scheme.
As described above, columnar capacitor array structure of the invention and preparation method, have the advantages that
The present invention provides a kind of columnar capacitor array structure and preparation method, and structure through the invention can be by capacitor
Size further reduces, and has biggish remaining space between adjacent capacitor, and size has better contractility, passes through to be formed
Electrode under side wall is corrugated or jagged column, can increase the surface of capacitor in the case where not increasing capacitor height
It is miniature to adapt to size to improve capacitive energy for product, in addition, the present invention is formd under filling perforation using self aligned etching technics
The bracket supporting layer of top of electrodes, and the bracket supporting layer structure with broken line shape is formed, increase supporting layer and capacitor knot
The contact area of structure improves support strength, and simplifies preparation process, improves the accuracy of device preparation.
Detailed description of the invention
Fig. 1 is shown as the structure of capacitor in the prior art.
Fig. 2 is shown as the preparation technology flow chart of array of capacitors structure of the invention.
Fig. 3 is shown as providing the top view of semiconductor substrate in the preparation of array of capacitors structure of the invention.
Fig. 4 is shown as the sectional view in the direction A-B in Fig. 3.
Fig. 5 is shown as forming the structural schematic diagram of sacrificial layer in the preparation of array of capacitors structure of the invention.
Fig. 6 is shown as forming the structural schematic diagram of separation layer in the preparation of array of capacitors structure of the invention.
Fig. 7 is shown as forming the structural schematic diagram of protection supporting layer in the preparation of array of capacitors structure of the invention.
Fig. 8 is shown as the top view of Fig. 7 structure, and Fig. 7 is the sectional view in the direction A-B in Fig. 8.
Fig. 9 is shown as forming the schematic diagram of through-hole in the preparation of array of capacitors structure of the invention.
Figure 10 is shown as the top view of Fig. 9 structure, and Fig. 9 is the sectional view in the direction A-B in Figure 10.
Figure 11 is shown as forming the structural schematic diagram in capacitor hole in the preparation of array of capacitors structure of the invention.
Figure 12 is shown as the top view of Figure 11 structure, and Figure 11 is the sectional view in the direction A-B in Figure 12.
Figure 13 is shown as forming the structural schematic diagram of lower electrode material layer in the preparation of array of capacitors structure of the invention.
Figure 14 is shown as the top view of Figure 13 structure, and Figure 13 is the sectional view in the direction A-B in Figure 14.
Figure 15 is shown as forming the structural schematic diagram of aperture photoresist layer in the preparation of array of capacitors structure of the invention.
Figure 16 is shown as the top view of Figure 15 structure, and Figure 15 is the sectional view in the direction A-B in Figure 16.
Figure 17 is shown as forming the structural schematic diagram of aperture mask layer in the preparation of array of capacitors structure of the invention.
Figure 18 is shown as the top view of Figure 17 structure, and Figure 17 is the sectional view in the direction A-B in Figure 18.
Figure 19 is shown as forming the structural schematic diagram of electrode under filling perforation in the preparation of array of capacitors structure of the invention.
Figure 20 is shown as forming the structural schematic diagram of bracket supporting layer in the preparation of array of capacitors structure of the invention.
Figure 21 is shown as the top view of Figure 20 structure, and Figure 20 is the sectional view in the direction A-B in Figure 21.
Figure 22 is shown as forming the structural representation of hole pattern mask layer in the preparation of array of capacitors structure of the invention
Figure.
Figure 23 is shown as forming the structural schematic diagram of hole photoresist layer in the preparation of array of capacitors structure of the invention.
Figure 24 is shown as the top view of Figure 23 structure, and Figure 23 is the sectional view in the direction A-B in Figure 24.
Figure 25 is shown as in the preparation of array of capacitors structure of the invention in the signal for forming aperture on bracket supporting layer
Figure.
Figure 26 is shown as the top view of Figure 25 structure, and Figure 25 is the sectional view in the direction A-B in Figure 26.
Figure 27 is shown as removing the structural schematic diagram of sacrificial layer in the preparation of array of capacitors structure of the invention.
Figure 28 is shown as the top view of Figure 27 structure, and Figure 27 is the sectional view in the direction A-B in Figure 28.
Figure 29 is shown as forming the structural schematic diagram of capacitor dielectric layer in the preparation of array of capacitors structure of the invention.
Figure 30 is shown as the top view of Figure 29 structure, and Figure 29 is the sectional view in the direction A-B in Figure 30.
Figure 31 is shown as forming the structural schematic diagram of upper electrode layer in the preparation of array of capacitors structure of the invention.
Figure 32 is shown as the top view of Figure 31 structure, and Figure 31 is the sectional view in the direction A-B in Figure 32.
Figure 33 is shown as forming the structural schematic diagram of top electrode obturator in the preparation of array of capacitors structure of the invention.
Figure 34 is shown as the top view of Figure 33 structure, and Figure 33 is the sectional view in the direction A-B in Figure 34.
Figure 35 is shown as forming the structural schematic diagram of top electrode coating in the preparation of array of capacitors structure of the invention.
Figure 36 is shown as the top view of Figure 35 structure, and Figure 35 is the sectional view in the direction A-B in Figure 36.
Component label instructions
11 substrates
12 contact pads
13 lower electrode layers
14 capacitor dielectric layers
15 upper electrode layers
100 semiconductor substrates
101 contact pads
102 sacrificial layers
102a first material layer
102b second material layer
103 separation layers
104 protection supporting layers
105 through-holes
106 capacitor holes
107 lower electrode material layers
108 aperture mask layers
109 aperture photoresist layers
110 aperture mask layers
110a aperture mask cell
Electrode under 111 filling perforations
111a first diameter portion
111b second diameter portion
111c electrode cylinder
111d is higher by portion
112 bracket supporting layers
112a bracket supporting layer bottom
112b bracket supporting layer side
113 hole pattern mask layers
113a hole
114 hole photoresist layers
114a hole window
115 openings
116 capacitor dielectric layers
117 upper electrode layers
118 top electrode obturators
119 air chambers
120 top electrode coatings
D1 first material layer thickness
D2 second material layer thickness
D3 separation layer thickness
D4 first diameter portion lateral dimension
D5 second diameter portion lateral dimension
D6 capacitor dielectric thickness degree
D7 upper electrode layer thickness
S1~S8 step 1)~step 8)
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 2 is please referred to Figure 36.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout form may also be increasingly complex.
As shown in Fig. 2~36, in order to achieve the above objects and other related objects, the present invention provides a kind of columnar capacitor battle array
The preparation method of array structure, includes the following steps:
1) semi-conductive substrate is provided, the semiconductor substrate includes the Contact welding that several are located in memory array structure
Disk；
2) sacrificial layer is formed in Yu Suoshu semiconductor substrate, the sacrificial layer includes the first material layer being alternately superimposed on and
Two material layers, under default etching condition, the etch rate of the first material layer is greater than the etching speed of the second material layer
A wherein second material layer for rate, the sacrificial layer is served as a contrast relative to the first material layer closer in the semiconductor
Bottom；
3) the graphical sacrificial layer is to form capacitor hole, wherein the capacitor hole appears the contact pad, and described
Capacitor hole has the lateral past first material layer recessed corrugated or indented sidewall；
4) each capacitor hole is filled to form electrode under filling perforation, and the upper surface of electrode is higher than the sacrifice under the filling perforation
The upper surface of layer, and there is between electrode spacing under the filling perforation in the adjacent capacitor hole；
5) surface of the structure obtained in step 4) deposits a bracket supporting layer, and fills out described in bracket supporting layer covering
The sacrificial layer for being higher by surrounding them under portion and the filling perforation of electrode under hole；
6) in forming at least one opening on the bracket supporting layer in a manner of Self-aligned etching, to open the bracket
Supporting layer, and the sacrificial layer is removed based on the opening；
7) surface of the structure obtained in step 6) forms capacitor dielectric layer, and is formed in the surface of the capacitor dielectric layer
Upper electrode layer, the capacitor dielectric layer is corrugated or zigzag covers the side wall of electrode under the filling perforation；And
8) surface of Yu Suoshu upper electrode layer forms top electrode obturator, and the top electrode obturator is filled in adjacent institute
The gap between upper electrode layer is stated, and is electrically connected with the upper electrode layer.
Below in conjunction with attached drawing the columnar capacitor structure and its preparation process that the present invention will be described in detail.
Firstly, as in Fig. 2 S1 and Fig. 3~4 shown in, carry out step 1), semi-conductive substrate 100 is provided, it is described partly to lead
Body substrate 100 includes that several are located at the contact pad 101 in memory array structure.
Specifically, being formed with memory array structure in the semiconductor substrate 100, the memory array structure includes more
A contact pad 101 (NC connects the contact pad of transistor), the memory array structure further includes having transistor
Character line (Word line) and bit line (Bitline), the contact pad 101 are electrically connected in the memory array structure
Transistor source further includes the M0 (inter-connection) made in peripheral circuit area in the semiconductor substrate.
In addition, the contact pad 101 can be but be not limited only to arrange in six square arrays, the capacitor with subsequent production
The arrangement of array structure is corresponding.It is further preferred that the semiconductor substrate 100 further includes semiconductor substrate, it is described to connect
Touching pad 101 is formed in the semiconductor substrate surface, in addition, be isolated between the contact pad 101 by wall,
The material of the wall can be silicon nitride (SiN), silica (SiO2), aluminium oxide (Al2O3) in any one or it is any
Two or more combinations, in this example, the material selection of the wall are SiN.
Then, as in Fig. 2 S2 and Fig. 5~8 shown in, carry out step 2), formed in Yu Suoshu semiconductor substrate 100 and sacrificed
Layer 102, the sacrificial layer 102 include the first material layer 102a and second material layer 102b being alternately superimposed on, in default etching item
Under part, the etch rate of the first material layer 102a is greater than the etch rate of the second material layer 102b, the sacrificial layer
A 102 wherein second material layer 102b is relative to the first material layer 102a closer in the semiconductor substrate.
Specifically, in this step, form sacrificial layer 102 in favor of subsequent and prepare electrode for capacitors and support construction,
In, it is preferred to use atom layer deposition process (Atomic Layer Deposition) or low pressure chemical vapor depositing operation (Low
Pressure Chemical Vapor Deposition) form the sacrificial layer 102, wherein the first material layer 102a
It is preferred with the stacking order of second material layer 102b are as follows: the bottom and top are slower second material of etch rate
Layer 102b, the size of electrode under the filling perforation being subsequently formed so as to reasonable disposition are conducive to the stability for improving capacitor.
In addition, on a preset condition based, such as under same etching condition, the etch rate of the first material layer 102a is greater than
The etch rate of the second material layer 102b, thus to be subsequently formed electrode under the column with corrugated or indented sidewall
Offer condition, is embodied in, subsequent capacitance hole etching processing procedure preferably comprise hole formation step with and subsequent hole cut
Dry etching can be used in facial contour modification step, hole formation step, and wet etching can be used in hole cross section profile modification step
Or dry etching, in the same corrosive liquid of wet etching, the etch rate of the second material layer 102b is less than described first
The etch rate of material layer 102a, so that in use corrosive liquid to the second material layer 102b and first material layer 102a
When being corroded, the lateral encroaching removal rate of the second material layer 102b is (i.e. along the length of the second material layer 102b
The removal rate in direction) much smaller than the first material layer 102a laterally remove rate (i.e. along the first material layer 102a
Length direction removal rate).The first material layer and the second material layer are as sacrificial layer in subsequent technique process
In can be removed.
As an example, the thickness D1 of the first material layer 102a is between 3nm~30nm in step 2), described
The thickness D2 of two material layer 102b is between 20nm~50nm.
As an example, 1.5~3 times between the first material layer 102a thickness of the thickness of the second material layer 102b
Between.
As an example, the thickness of the sacrificial layer 102 is between 1 μm~1.5 μm.
As an example, the first material layer 102a includes boron doped silicon oxide layer in step 2), second material
Layer 102b includes silicon oxide layer.
Specifically, in one example, the first material layer 102a includes boron doped silicon oxide layer, second material
Layer 102b includes silicon oxide layer, can be formed by way of alternating deposit (pulse gas injection).In addition, described
The number of plies of first material layer 102a and the second material layer 102b can be set according to actual needs, it is preferable that this reality
It applies in example, total number of plies of the first material layer 102a and the second material layer 102b are greater than 20 layers, and ensure at 1.3 μm
It is greater than with total number of plies 20 layers of the first material layer 102a and the second material layer 102b in height, in addition, described the
The thickness of one material layer 102a is preferably between 5nm~15nm, the thickness of the second material layer be preferably between 22nm~
Between 35nm；The thickness of the sacrificial layer is preferably between 1.2 μm~1.4 μm.
In a preferred embodiment, the thickness of the second material layer 102b is the thickness of the first material layer 102a
1.5~3 times, preferably 2 ± 0.2 times make finally formed capacitor hole to advantageously form corrugated or jagged side wall
106 side walls are uniform and smooth, and stable structure, and make capacitor knot of the electrode as lower electrode under the finally formed filling perforation
Structure is stablized.
As an example, between step 1) and step 2) further include: 100 surface of Yu Suoshu semiconductor substrate forms a separation layer
103, and the sacrificial layer 102 in step 2) is formed in the surface of the separation layer 103.
As an example, the thickness D3 of the separation layer 103 is between 5nm~45nm.
As an example, the separation layer 103 includes silicon nitride layer.
Specifically, further including forming a separation layer 103 on the semiconductor surface 100, the separation layer 103 can be made
For the insulating layer of protective separation All other routes, etching stop layer can also be used as, can also protect contact pad simultaneously.It is preferred that
Ground, the separation layer deposit work using atom layer deposition process (Atomic Layer Deposition) or low pressure chemical vapor
Skill (Low Pressure Chemical Vapor Deposition) formation, thickness are preferably between 10nm~30nm, separately
Outside, in a preferred embodiment, the spacer material layer between the separation layer and the contact pad selects identical material, to protect
Demonstrate,prove device stability.
Then shown in S3, as shown in figure 1 and Fig. 9~12, step 3), the graphical sacrificial layer 102, to form electricity are carried out
Hold hole 106, wherein the capacitor hole 106 appears the contact pad 101, and the capacitor hole 106 have it is lateral toward described the
One material layer 102a is recessed corrugated or indented sidewall.
Specifically, the upper surface of the structure obtained in step 2) forms photoresist as mask layer, certainly, in other examples
In can also form the mask layer (such as silicon nitride hard mask layer) of other materials again using photoetching process by the exposure mask layer pattern
Change, to obtain the Patterned masking layer with window, wherein the window can be along the surface of the Patterned masking layer
It arranges in six square arrays, to be corresponded with about 101 contact pad, finally to prepare the capacitor hole 106, the electricity
The sectional view for holding the side wall in hole can be the side wall of the rectangular saw-tooth shape in diagram, and use the finally obtained capacitor of this method
The side wall in hole 106 is very smooth, is conducive to subsequent preparation process and is conducive to the raising of device performance.
As an example, in step 3), the specific steps for forming the capacitor hole include:
(do not show in figure in the Patterned masking layer for forming the window with array arrangement in the structure that step 2) obtains 3-1)
Out), and based on the Patterned masking layer using the technique of dry etching the sacrificial layer 102 is etched, in the sacrificial layer
Perforative through-hole 105 up and down is formed in 102, the through-hole 105 through-hole 105 corresponding and described with the window appears described and connects
Pad 101 is touched, as shown in FIG. 9 and 10, the through-hole 105 and a pair above and below the window on the Patterned masking layer
It answers；
3-2) use wet etching technique etch step 3-1) formed the through-hole 105 side wall, to form side wall
The corrugated or jagged capacitor hole 106, as shown in FIG. 11 and 12.
Specifically, in this step, etching to form the capacitor hole 106 using two-step method, being beaten first using dry etching
Open form is carrying out through-hole modification using wet etching, wherein the etching liquid of the wet etching is preferably using quality point at through-hole
Count the NH between 0.15%~15%4OH aqueous solution, the etch rate of the etching liquid, the second material layer 102b can be remote
Less than the etch rate of the first material layer 102a, during corrosion, what the first material layer 102a was laterally removed
Rate is much larger than the rate that laterally removes of the second material layer 102b, and available side wall is corrugated or the institute of rectangular toothed
Capacitor hole 106 is stated, as shown in figure 11, the capacitor hole 106 includes that several perpendicular aperture portions (are based on second material layer 102b shape
At) and several borehole enlargement portions (being formed based on first material layer 102a) for being connected with the perpendicular aperture portion.
As an example, between step 2) and step 3) further include: the surface of Yu Suoshu sacrificial layer 102 forms a protection support
Layer 104, and the protection supporting layer 104 is etched based on the Patterned masking layer simultaneously in step 3), as shown in Fig. 7 and Fig. 9.
Specifically, being formed after the sacrificial layer 102, one layer of protection supporting layer 104 also is formed in the sacrificial layer surface,
It can be used as the protective layer in etching mask layer and etching process, and one layer can also be used as in final capacitor arrangement
The supporting layer of supporting role, improves the support strength of entire capacitance structure, and the material of the protection supporting layer can choose as nitrogen
SiClx layer.
Then, as in Fig. 2 S4 and Figure 13~19 shown in, carry out step 4), fill each capacitor hole 106 and filled out with being formed
Electrode 111 under hole, the upper surface of electrode 111 is higher than the upper surface of the sacrificial layer 102, and the adjacent capacitor under the filling perforation
There is between electrode 111 spacing under the filling perforation in hole 106.
Specifically, using atom layer deposition process (Atomic Layer Deposition) or chemical vapor deposition process
The technique of (Chemical Vapor Deposition) or physical vapour deposition (PVD) (Physical Vapor Deposition) in
Electrode 111 under filling perforation is formed in the capacitor hole 106, it is electric under the filling perforation eventually as the column lower electrode arrangement of capacitor
Pole 111 includes that one or both of metal nitride and metal silicide are formed by compound, such as titanium nitride (Titanium
Nitride), titanium silicide (Titanium Silicide), nickle silicide (Titanium Silicide), silicon titanium nitride
(TiSixNy), it can also be that metal electrode material is the metals such as conductive material such as Ru (ruthenium), Pt (platinum), Ir (iridium), Pd (palladium),
Or even metal oxide such as RuO2(ruthenium-oxide), IrO2(yttrium oxide) etc..Wherein it is preferred to which resistivity of material is from 1 × 10-8(Ω
M) to 1 × 102(Ω m) range.
As an example, the specific steps for forming electrode 111 under the filling perforation include: 4-1 in step 4)) Yu Suoshu capacitor
102 surface of the sacrificial layer in hole 106 and around the capacitor hole 106 deposits continuous lower electrode material layer 107；
Aperture mask layer 110 4-2) is formed on Yu Suoshu lower electrode material layer 107, if the aperture mask layer 110 includes
A dry aperture mask cell 110a, wherein the aperture mask cell 110a is corresponding with the contact pad 101, and described opens
The lateral dimension of hole mask cell 110a is greater than the lateral dimension of the contact pad 101；
The lower electrode material layer 107 4-3) is etched based on the aperture mask layer 110, to divide the lower electrode material
Layer 107 forms electrode 111 under the filling perforation between adjacent with spacing.
Specifically, this example provides a kind of formation process of capacitor lower electrode, wherein form the aperture mask layer
110 concrete technology includes: that as shown in figure 15,107 surface of Yu Suoshu lower electrode material layer forms one layer of aperture mask material
Layer 108, and in formation aperture photoresist layer 109 on the aperture mask layer 108, wherein it is fixed to be formed on aperture photoresist layer
The figure of the justice aperture mask cell 110a, by the pattern transfer of the aperture photoresist layer 108 to the aperture mask material
On layer 108, to form the aperture mask layer 110, it is preferred to use the technique of photoetching and plasma etching etches the lower electricity
Pole material layer 107, to be separated the connected lower electrode material layer 107 is deposited before.
In addition, the lateral dimension (size for being parallel to semiconductor substrate surface) of the aperture mask cell 110a is preferably big
In the size of the contact pad in the direction, preferably its circular in cross-section, the covering contact pad can be corresponded to.This
Outside, it is preferable that the lateral dimension of the aperture mask cell 110a is greater than 111 maximum transverse size of electrode under the filling perforation, such as
The size based on first material layer 102a forming position in this example, such as the lateral dimension of first diameter portion 111a, it is preferable that
The lateral dimension of the aperture mask cell 110a is less than 1/3 of the minimal transverse distance of electrode under the adjacent filling perforation, described
Minimal transverse distance refers to the smallest distance in the lateral distance under adjacent filling perforation between electrode.
As an example, step 4-3) in further include: while etching lower electrode material layer 107, further etching with
The part that the lower electrode material layer 107 the is in contact sacrificial layer 102.
Specifically, as shown in figure 17, the sacrificial layer of certain depth preferably being etched in etching process, is preferably etched most upper
One layer of some materials layer, i.e. part the first material layer 102a or the part second material layer 102b, it is preferable that most upper one
Layer is set as second material layer 102b, and thickness is greater than first material layer, it is further preferred that the above-mentioned depth further etched
It is the 1/4~3/4 of most upper layer of material layer (such as described second material layer 102b) thickness, to be further conducive to subsequent support layer
Formation, and be conducive to improve device entirety stability.In addition, when the sacrificial layer surface is formed with the protection supporting layer
When 104, while etching away the protection supporting layer.
As an example, electrode 111 includes the first diameter portion 111a and second being alternately superimposed under the filling perforation in step 4)
Diameter portion 111b, wherein the first diameter portion 111a is formed based on the first material layer 102a of the sacrificial layer, and described second
Diameter portion 111b is formed based on the second material layer 102b of the sacrificial layer, and the lateral dimension D4 of the first diameter portion 111a
Greater than the lateral dimension D5 of the second diameter portion 111b.
As an example, the lateral dimension of the first diameter portion 111a is between 40nm~105nm, the second diameter
The lateral dimension of portion 111b is between 35nm~100nm.
Specifically, the second diameter portion 111b can not increase capacitor height as enlarged-diameter portion in this example
Increase the surface area between the capacitor lower electrode and top electrode while spending, to increase capacitive energy, improves capacitor, In
In one preferred embodiment, the lateral dimension in the first diameter portion between the second diameter portion lateral dimension 1.08~
Between 1.18 times, 1.5~3 times with a thickness of the first diameter portion 111a thickness of the second diameter portion 111b, to have
Conducive to the stability of raising capacitor arrangement, and reach the realizability of technique.Preferably, in the present embodiment, described first
Total number of plies of diameter portion 111a and the second diameter portion 111b are greater than 20 layers, and ensure to have total layer in 1.3 μm of height
Number is greater than 20 layers of the first diameter portion 111a and the second diameter portion 111b, in addition, the first diameter portion 111a
Thickness is preferably between 5nm~15nm, and the thickness of the second diameter portion 111b is preferably between 22nm~35nm；It is described
The thickness of the laminated construction part of electrode is preferably between 1.2 μm~1.4 μm under filling perforation.
In addition, as shown in figure 17, electrode 111 is incorporated on the contact pad 101 under the filling perforation of formation, described to fill out
Electrode 111 has electrode cylinder 111c and is higher by portion 111d, and the electrode cylinder on the electrode cylinder 111c under hole
The side wall of 111c is corrugated or zigzag, wherein the electrode cylinder 111c includes the portion being embedded in 102 layers of the sacrificial layer
Point, the portion 111d that is higher by includes the part for being higher by the sacrificial layer 102, in addition, when being also formed with the guarantor in device architecture
When protecting supporting layer 104, electrode 111 under the filling perforation is divide into upper part and lower part by the protection supporting layer 104, that is, is located at the guarantor
Protect supporting layer 104 under the electrode cylinder 111c, and on the protection supporting layer 104 described in be higher by portion.
Then, as in Fig. 2 S5 and Figure 20~21 shown in, carry out step 5), it is heavy in the surface for the structure that step 4) obtains
One bracket supporting layer 112 of product, and the bracket supporting layer 112 cover electrode 111 under the filling perforation be higher by portion and the filling perforation
The sacrificial layer 102 of lower surrounding them.
Specifically, forming the bracket supporting layer 112 of capacitor arrangement in the step, wherein 112 shape of bracket supporting layer
The top of electrode 111 under filling perforation described in Cheng Yu can improve the mechanical strength of device in final structure, simplify preparation process,
It can be completed by subsequent self-registered technology, in addition, the present invention forms the bracket supporting layer 112 of a polyline shaped, thus
The contact area between the bracket supporting layer 112 and device architecture can be increased, also improve the length of supporting layer 112 itself,
So as to be further ensured that the integral strength of device, in addition, in a preferable example, the bracket supporting layer 112 with it is described
Protection supporting layer 104 is in contact, so that the two coats the top of electrode 111 under the filling perforation, greatly improves capacitor
Stability.In addition, the material of the bracket supporting layer 112 includes but is not limited to silicon nitride, the material of the bracket supporting layer
Material with the protection supporting layer 104 is preferably identical material, to further increase the stability between device architecture.
Continue, as in Fig. 2 S6 and Figure 22~28 shown in, carry out step 6), in the branch in a manner of Self-aligned etching
At least one opening 115 is formed on frame supporting layer 112, to open the bracket supporting layer 112, and is gone based on the opening 115
Except the sacrificial layer 102.
As an example, in step 6), the specific steps for opening the bracket supporting layer 112 include:
6-1) 112 surface of Yu Suoshu bracket supporting layer forms hole pattern mask layer 113, described hole graphic mask layer
113 include the hole 113a of several array arrangements, wherein described hole 113a appear under the adjacent filling perforation electrode 111 it
Between the bracket supporting layer 112 being located on the sacrificial layer 102 bottom 112a and the institute that is connected with the bottom
The side 112b for stating bracket supporting layer 112, as shown in Figure 23 and Figure 25；
It 6-2) is based on described hole graphic mask layer 113, in a manner of Self-aligned etching and using the technique of dry etching
The bracket supporting layer 112 is etched, with corresponding with described hole 113a in forming at least one on the bracket supporting layer 112
The opening 115, to open the bracket supporting layer 112, as shown in figure 27.
Specifically, the bracket supporting layer 112 is opened by way of Self-aligned etching in the step, based on opening
The opening 115 remove the sacrificial layer 102, wherein formed based on hole photoresist layer 114 formed described hole graphic mask
Layer 113 is formed with the hole window for appearing the bracket supporting layer for needing to open removal part on described hole photoresist layer 104
114a.In a preferred embodiment, described hole window 114a appears the bottom 112a and side 112b of bracket supporting layer 112,
Described hole photoresist layer 114 is based on using the technique of dry etching to perform etching, and in etching process, it is thicker to retain side 112b
Bracket supporting layer 112a, while the bracket supporting layer 112b that automatic etching removal bottom is relatively thin, so that bracket supporting layer 112 is beaten
It opens.Additionally, it is preferred that carrying out the removal of subsequent sacrificial layer using wet-etching technology.
As an example, step 6-1) in, described hole 114a arranges in uniform intervals, and each described hole 114a is simultaneously
Overlap mutually with electrode 111 under three adjacent filling perforations.
Specifically, this example provides the arrangement mode of hole 114a a kind of, this also determines the bracket support being subsequently formed
The position of opening 115 on layer 112, as shown in Figure 23 and Figure 24, a described hole 114a and three contact pads 101
Electrode 111 is overlapping under the filling perforation of corresponding position, when carrying out dry etching, with electrode 111 under three filling perforations
Overlapping bracket supporting layer out is etched away, and as shown in figure 26, and then manifests sacrificial layer, and what this method was formed has opening
115 bracket supporting layer 112 has suitable aperture position, and under the filling perforation of guarantee section position between electrode 111
The bottom of bracket support is connected, and can be conducive to the wet etching and enough support strengths of sacrificial layer.
Then, as in Fig. 2 S7 and Figure 29~32 shown in, carry out step 7), in the surface shape for the structure that step 6) obtains
Upper electrode layer 117, the capacitor dielectric layer 116 are formed at capacitor dielectric layer 116, and in the surface of the capacitor dielectric layer 116
Corrugated or zigzag covers the side wall of electrode 111 under the filling perforation.
As an example, the dielectric constant of the capacitor dielectric layer 116 is between 4~400 in step 7)；The capacitor
Dielectric layer 116 is selected from strontium titanates and titanium oxide (SrTiO3/TiO2) constitute laminated construction, aluminium oxide and hafnium oxide (AlO/HfO)
The laminated construction and compound calcium nutrition Ferroelectric that laminated construction, zirconium oxide and the aluminium oxide (ZrO/AlO/ZrO) of composition are constituted
(BST material, the iron electrode material of composite calcium hematite structure are by BaTiO to material3And SrTiO3The solid solution formed by a certain percentage
One of body).
As an example, the thickness D6 of the capacitor dielectric layer 116 is between 10nm~85nm, it is preferable that described in one
The capacitor dielectric layer of 111 two sides of electrode (part including first diameter portion 111a and second diameter portion 111b) under filling perforation
Spacing between 116 both sides is between 50nm~120nm.
As an example, the thickness D7 of the upper electrode layer 117 is between 15nm~95nm, it is preferable that filled out described in one
117 liang of the upper electrode layer of 111 two sides of electrode (part including first diameter portion 111a and second diameter portion 111b) under hole
Spacing between side is between 50nm~120nm.
Specifically, using atom layer deposition process (Atomic Layer Deposition) or chemical vapor deposition process
The technique shape of (Chemical Vapor Deposition) or physical vapour deposition (PVD) (Physical Vapor Deposition)
At the capacitor dielectric layer 116 and upper electrode layer 117, the material of the upper electrode layer 114 includes metal nitride and metal
One or both of silicide is formed by compound, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium
Silicide), nickle silicide (Titanium Silicide), silicon titanium nitride (TiSixNy) can also be that metal electrode material is
The metals such as conductive material such as Ru (ruthenium), Pt (platinum), Ir (iridium), Pd (palladium) or even metal oxide such as RuO2(ruthenium-oxide), IrO2
(yttrium oxide) etc..Wherein it is preferred to which resistivity of material is from 1 × 10-8(Ω m) is to 1 × 102(Ω m) range；The capacitor dielectric
Layer preferably high K dielectric material, to improve the capacitance of unit-area capacitance device.
Finally, as in Fig. 2 S8 and Figure 33~36 shown in, carry out step 8), the surface of Yu Suoshu upper electrode layer 117 is formed
Top electrode obturator 118, and the top electrode obturator 118 is filled in the gap between the adjacent upper electrode layer 117, and with
The upper electrode layer 117 is electrically connected.
As an example, being also formed with air chamber 119, and the air chamber in the top electrode obturator 118 in step 8)
119 between the adjacent upper electrode layer 117.
As an example, after step 8) further include: 118 surface of Yu Suoshu top electrode obturator forms top electrode coating
120。
Specifically, the material of the top electrode obturator 118 includes polysilicon (poly), fill up between each columnar capacitor
Gap, make stable structure and the upper electrode layer of each capacitor 117 link together；Again toward the institute of deposited metal material thereon
Top electrode coating 120 is stated, the stop layer and line as subsequent connect contact layer.In a preferred embodiment, also
Air chamber 119 is formed between the top electrode obturator 118 to play slow so as to the active force between releasing capacitor
Punching effect, so as to discharge the strain in structural material, the structure sheafs such as metal contact layer are because of warm in avoidable manufacturing process
The phenomenon that expansion squeezes and makes capacitor, and especially lower electrode layer deforms is conducive to the stability for improving device, wherein described
The formation of air chamber 119 can control the depositing operation of the top electrode obturator, such as control deposition doping, the deposition of polysilicon
Temperature and the pressure of substrate etc. control the formation of the air chamber.
As shown in Figure 33~36, the present invention also provides a kind of columnar capacitor array structures, wherein the columnar capacitor
Array structure is preferably prepared using the preparation method of the columnar capacitor array structure of the invention comprising:
Semiconductor substrate 100, the semiconductor substrate 100 include that several are located at the contact pad in memory array structure
101；
Electrode 111 under filling perforation are incorporated on the contact pad 101, and electrode 111 has electrode cylinder under the filling perforation
111c and be higher by portion 111d on the electrode cylinder 111c, and the electrode cylinder 111c side wall is corrugated or sawtooth
Shape；
Capacitor dielectric layer 116 is formed under the filling perforation under the side wall of electrode 111 and the filling perforation around electrode 111
The semiconductor substrate 100 on；
Upper electrode layer 117 is formed in 116 surface of capacitor dielectric layer；And
Top electrode obturator 118, is filled in the gap between the adjacent upper electrode layer 117, and with the upper electrode layer
117 electrical connections.
Specifically, being formed with memory array structure in the semiconductor substrate 100, the memory array structure includes more
A contact pad 101 (NC connects the contact pad of transistor), the memory array structure further includes having transistor
Character line (Word line) and bit line (Bitline), the contact pad 101 are electrically connected in the memory array structure
Transistor source further includes the M0 (inter-connection) made in peripheral circuit area in the semiconductor substrate.
Specifically, the contact pad 101 can be but be not limited only to arrange in six square arrays, the capacitor with subsequent production
The arrangement of device array structure is corresponding.It is further preferred that the semiconductor substrate 100 further includes semiconductor substrate, it is described
Contact pad 101 is formed in the semiconductor substrate surface, in addition, between the contact pad 101 by wall carry out every
From the material of the wall can be silicon nitride (SiN), silica (SiO2), aluminium oxide (Al2O3) in any one or
Any two or more combination, in this example, the material selection of the wall are SiN.
In addition, as shown in figure 35, electrode 111 is incorporated on the contact pad 101 under the filling perforation of formation, described to fill out
Electrode 111 has electrode cylinder 111c and is higher by portion 111d, and the electrode cylinder on the electrode cylinder 111c under hole
The side wall of 111c is corrugated or zigzag, wherein the electrode cylinder 111c includes the portion being embedded in 102 layers of the sacrificial layer
Point, the portion 111d that is higher by includes the part for being higher by the sacrificial layer 102, in addition, when being also formed with the guarantor in device architecture
When protecting supporting layer 104, electrode 111 under the filling perforation is divide into upper part and lower part by the protection supporting layer 104, that is, is located at the guarantor
Protect supporting layer 104 under the electrode cylinder 111c, and on the protection supporting layer 104 described in be higher by portion.
As an example, the columnar capacitor array structure further includes bracket supporting layer 112, the bracket supporting layer 112
At least cover the described of electrode 111 under each filling perforation and be higher by portion 111d, and the capacitor dielectric layer 116 be consecutively formed at it is described
The semiconductor of surrounding them serves as a contrast under the surface and the filling perforation of electrode 111 and the bracket supporting layer 112 under filling perforation
On bottom.
Specifically, the bracket supporting layer 112 is formed in the top of electrode 111 under the filling perforation, it can be in final structure
The middle mechanical strength for improving device, in addition, the present invention forms the bracket supporting layer 112 of a polyline shaped, so as to increase
Contact area between the bracket supporting layer and device architecture improves the length of supporting layer itself, also so as to further
Guarantee the integral strength of device, in addition, when being also formed with the protection supporting layer 104 in device architecture, the bracket support
While being higher by upper surface and the side wall of portion 111d described in 112 covering of layer, and the end of the protection supporting layer 104 is extended to,
So that the bracket supporting layer 112 is in contact with the protection supporting layer 104, so that the two is by electrode under the filling perforation
111 top cladding, greatly improves the stability of capacitor.In addition, the material of supporting layer 110 includes but not between described
It is limited to silicon nitride, the material of the bracket supporting layer and the material for protecting supporting layer 104 are preferably identical material, further
Improve the stability between device architecture.
As an example, the columnar capacitor array structure further includes protection supporting layer 104, the protection supporting layer 104
It is placed on the periphery of electrode 111 under the filling perforation, and the upper surface of the protection supporting layer 104 is higher by under portion 111d with described
Surface is in contact, and the outer rim of the protection supporting layer 104 is supported with the bracket on 111 side wall of electrode under the filling perforation
The inner wall of layer 112 is in contact.
Specifically, the columnar capacitor array structure further include protection supporting layer 104 its can be used as etching mask layer
And the protective layer in etching process, the supporting layer of one layer of supporting role can also be formed in final capacitor arrangement, mentioned
The material of the support strength of high entire capacitance structure, the protection supporting layer can choose as silicon nitride layer.
As an example, being also formed with a separation layer 103 between the semiconductor substrate 100 and the capacitor dielectric layer 116.
As an example, the thickness of the separation layer 103 is between 5nm~45nm；The separation layer includes silicon nitride
Layer.
Specifically, further including forming a separation layer 103 on the semiconductor surface 100, the separation layer 103 can be made
For the insulating layer of protective separation All other routes, etching stop layer can also be used as, can also protect contact pad simultaneously, thickness is excellent
Selected introductions are between 10nm~30nm, in addition, in a preferred embodiment, being isolated between the separation layer and the contact pad
Material layer selects identical material, to guarantee device stability.
As an example, the electrode cylinder 111c of electrode 111 includes the first diameter portion being alternately superimposed under the filling perforation
111a and second diameter portion 111b, wherein the lateral dimension of the first diameter portion 111a is greater than the second diameter portion 111b
Lateral dimension.As an example, the lateral dimension of the first diameter portion 111a is between 40nm~105nm, described second
The lateral dimension of diameter portion 111b is between 35nm~100nm.
Specifically, the second diameter portion 111b can not increase capacitor height as enlarged-diameter portion in this example
Increase the surface area between the capacitor lower electrode and top electrode while spending, to increase capacitive energy, improves capacitor, In
In one preferred embodiment, 1.5~3 times with a thickness of the first diameter portion 111a thickness of the second diameter portion 111b, from
And be conducive to improve the stability of capacitor arrangement, and reach the realizability of technique.Preferably, described in the present embodiment
Total number of plies of first diameter portion 111a and the second diameter portion 111b are greater than 20 layers, and ensure have in 1.3 μm of height
Total number of plies is greater than 20 layers of the first diameter portion 111a and the second diameter portion 111b, in addition, the first diameter portion
The thickness of 111a is preferably between 5nm~15nm, the thickness of the second diameter portion 111b be preferably between 22nm~35nm it
Between；The thickness of the laminated construction part of electrode is preferably between 1.2 μm~1.4 μm under the filling perforation.
As an example, the columnar capacitor array structure further includes top electrode coating 120, the top electrode coating
120 are formed in the surface of the top electrode obturator 118.
As an example, being also formed with air chamber 119 in the top electrode obturator 118, and the air chamber 119 is located at phase
Between the adjacent upper electrode layer 117.
Specifically, the dielectric constant of the capacitor dielectric layer 116 is between 4~400；The capacitor dielectric layer 116 selects
From strontium titanates and titanium oxide (SrTiO3/TiO2) lamination that constitutes of the laminated construction, aluminium oxide and the hafnium oxide (AlO/HfO) that constitute
The laminated construction and compound calcium nutrition Ferroelectric material (BST material that structure, zirconium oxide and aluminium oxide (ZrO/AlO/ZrO) are constituted
Material, the iron electrode material of composite calcium hematite structure is by BaTiO3And SrTiO3The solid solution formed by a certain percentage) in one
Kind.As an example, the thickness D6 of the capacitor dielectric layer 116 is between 10nm~85nm, it is preferable that under a filling perforation
Spacing between the both sides of the capacitor dielectric layer 116 of electrode two sides (part including first diameter portion and second diameter portion)
Between 50nm~120nm.
As an example, the thickness D7 of the upper electrode layer 117 is between 15nm~95nm, it is preferable that filled out described in one
Under hole between the both sides of the upper electrode layer 117 of electrode two sides (part including first diameter portion and second diameter portion) between
Away between 50nm~120nm.
Specifically, the material of the upper electrode layer 114 includes one or both of metal nitride and metal silicide
It is formed by compound, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide
(Titanium Silicide), silicon titanium nitride (TiSixNy), can also be metal electrode material be conductive material such as Ru (ruthenium),
The metals such as Pt (platinum), Ir (iridium), Pd (palladium) or even metal oxide such as RuO2(ruthenium-oxide), IrO2(yttrium oxide) etc..Wherein, excellent
Selection of land, resistivity of material is from 1 × 10-8(Ω m) is to 1 × 102(Ω m) range；The preferred high K dielectric material of capacitor dielectric layer,
To improve the capacitance of unit-area capacitance device.
In addition, the material of the top electrode obturator 118 includes polysilicon (poly), fill up between each columnar capacitor
Gap makes stable structure and the upper electrode layer of each capacitor 117 links together；Again toward the described of deposited metal material thereon
Top electrode coating 120, stop layer and line as subsequent connect contact layer.In a preferred embodiment, also exist
Air chamber 119 is formed between the top electrode obturator 118 plays buffering so as to the active force between releasing capacitor
Effect, so as to discharge the strain in structural material, the structure sheafs such as metal contact layer are because hot swollen in avoidable manufacturing process
It is swollen extruding and make capacitor, especially lower electrode layer deform the phenomenon that, be conducive to improve device stability, wherein the sky
The formation of air cavity 119 can control the depositing operation of the top electrode obturator, such as control deposition doping, the deposition temperature of polysilicon
The formation of the control such as pressure of the degree and substrate air chamber.
In addition, the organization of semiconductor memory includes as implemented the present invention also provides a kind of organization of semiconductor memory
Columnar capacitor array structure described in example, the specific structure of the array of capacitors structure please refer to above-described embodiment, this
Place is not repeated.As an example, the organization of semiconductor memory can be but be not limited only to dynamic RAM (DRAM).
In conclusion the present invention provides a kind of columnar capacitor array structure and preparation method thereof, preparation includes: offer one
Semiconductor substrate, the semiconductor substrate include the contact pad that several are located in memory array structure；In the semiconductor
Sacrificial layer is formed on substrate, the sacrificial layer includes the first material layer and second material layer being alternately superimposed on, in default etching item
Under part, the etch rate of the first material layer is greater than the etch rate of the second material layer, and wherein the one of the sacrificial layer
The second material layer is relative to the first material layer closer in the semiconductor substrate；The graphical sacrificial layer is with shape
At capacitor hole, wherein the capacitor hole appears the contact pad, and the capacitor hole has the lateral past first material layer
Recessed corrugated or indented sidewall；Each capacitor hole is filled to form electrode under filling perforation, electrode is upper under the filling perforation
Surface is higher than the upper surface of the sacrificial layer, and has spacing under the filling perforation in the adjacent capacitor hole between electrode；In
The surface of structure obtained in the previous step deposits a bracket supporting layer, and the bracket supporting layer covers the height of electrode under the filling perforation
Out under portion and the filling perforation surrounding them the sacrificial layer；It is formed in a manner of Self-aligned etching on the bracket supporting layer
At least one opening to open the bracket supporting layer, and removes the sacrificial layer based on the opening；In obtained in the previous step
The surface of structure forms capacitor dielectric layer, and forms upper electrode layer, the capacitor dielectric layer in the surface of the capacitor dielectric layer
Corrugated or zigzag covers the side wall of electrode under the filling perforation；And top electrode is formed in the surface of the upper electrode layer and is filled out
Body, and the gap between the adjacent upper electrode layer of top electrode obturator filling full phase are filled, and is electrically connected with the upper electrode layer
It connects.Through the above scheme, the present invention provides a kind of columnar capacitor array structure and preparation method, and structure through the invention can
To further reduce capacitor size, using column capacitance structure, there is biggish remaining space, size between adjacent capacitor
With better contractility, by forming electrode under side wall is corrugated or jagged column, capacitor can be increased in portion
Increase the surface area of capacitor in the case where height, to improve capacitive energy, it is miniature to adapt to size, in addition, the present invention uses certainly
The etching technics of alignment forms the bracket supporting layer of top of electrodes under filling perforation, and forms the bracket supporting layer with broken line shape
Structure increases the contact area of supporting layer and capacitor arrangement, improves support strength, and simplify preparation process, improve
The accuracy of device preparation.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial exploitation value
Value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (24)
1. a kind of preparation method of columnar capacitor array structure, which comprises the steps of:
1) semi-conductive substrate is provided, the semiconductor substrate includes the contact pad that several are located in memory array structure；
2) sacrificial layer is formed in Yu Suoshu semiconductor substrate, the sacrificial layer includes the first material layer being alternately superimposed on and the second material
The bed of material, the etch rate of the first material layer is greater than the etch rate of the second material layer, institute under default etching condition
The wherein second material layer of sacrificial layer is stated relative to the first material layer closer in the semiconductor substrate；
3) the graphical sacrificial layer is to form capacitor hole, wherein the capacitor hole appears the contact pad, and the capacitor
Hole has the lateral past first material layer recessed corrugated or indented sidewall；
4) each capacitor hole is filled to form electrode under filling perforation, and the upper surface of electrode is higher than the sacrificial layer under the filling perforation
Upper surface, and there is between electrode spacing under the adjacent filling perforation；
5) surface of the structure obtained in step 4) deposits a bracket supporting layer, and the bracket supporting layer covers under the filling perforation
The sacrificial layer for being higher by surrounding them under portion and the filling perforation of electrode；
6) in forming at least one opening on the bracket supporting layer in a manner of Self-aligned etching, to open the bracket support
Layer, and the sacrificial layer is removed based on the opening；
7) surface of the structure obtained in step 6) forms capacitor dielectric layer, and is formed and powered in the surface of the capacitor dielectric layer
Pole layer, the capacitor dielectric layer is corrugated or zigzag covers the side wall of electrode under the filling perforation；And
8) surface of Yu Suoshu upper electrode layer forms top electrode obturator, and the top electrode obturator is filled in adjacent described power on
Pole layer between gap and be electrically connected with the upper electrode layer.
2. the preparation method of columnar capacitor array structure according to claim 1, which is characterized in that step 1) and step
2) between further include: Yu Suoshu semiconductor substrate surface forms a separation layer, and the sacrificial layer in step 2) is formed in institute
State the surface of separation layer.
3. the preparation method of columnar capacitor array structure according to claim 2, which is characterized in that the separation layer
Thickness is between 5nm~45nm；The separation layer includes silicon nitride layer；Using atomic layer deposition and low-pressure chemical vapor deposition
One of form the separation layer.
4. the preparation method of columnar capacitor array structure according to claim 1, which is characterized in that in step 2), institute
Stating first material layer includes boron doped silicon oxide layer, and the second material layer includes silicon oxide layer；The first material layer
Thickness is between 3nm~30nm, and the thickness of the second material layer is between 20nm~50nm；The thickness of the sacrificial layer
Between 0.5 μm~1.5 μm.
5. the preparation method of columnar capacitor array structure according to claim 1, which is characterized in that in step 2), institute
The thickness of second material layer is stated between 1.5~3 times of the first material layer thickness.
6. the preparation method of columnar capacitor array structure according to claim 1, which is characterized in that step 2) and step
3) between further include: the surface of Yu Suoshu sacrificial layer forms a protection supporting layer, and simultaneously based on described graphical in step 3)
Mask layer etches the protection supporting layer.
7. the preparation method of columnar capacitor array structure according to claim 1, which is characterized in that in step 3), shape
Specific steps at the capacitor hole include:
3-1) in the Patterned masking layer for forming the window with array arrangement in the structure that step 2) obtains, and based on the figure
Shape mask layer etches the sacrificial layer using the technique of dry etching, perforative logical up and down to be formed in the sacrificial layer
Hole, the through-hole through-hole corresponding and described with the window appear the contact pad；And
3-2) use wet etching technique etch step 3-1) formed the through-hole side wall, it is corrugated to form side wall
Or the jagged capacitor hole.
8. the preparation method of columnar capacitor array structure according to claim 1, which is characterized in that in step 4), shape
Specific steps at electrode under the filling perforation include:
4-1) sacrificial layer surface in Yu Suoshu capacitor hole and around the capacitor hole deposits continuous lower electrode material layer；
Aperture mask layer 4-2) is formed on Yu Suoshu lower electrode material layer, the aperture mask layer includes several aperture exposure mask lists
Member, wherein the aperture mask cell is corresponding with the contact pad, and the lateral dimension of the aperture mask cell is greater than institute
State the lateral dimension of contact pad；And
The lower electrode material layer 4-3) is etched based on the aperture mask layer, to divide the lower electrode material layer, forms phase
Electrode under the filling perforation between neighbour with spacing.
9. the preparation method of columnar capacitor array structure according to claim 8, which is characterized in that step 4-3) in also
It include: while etching the lower electrode material layer, further to etch described in the part being in contact with the lower electrode material layer
Sacrificial layer.
10. the preparation method of columnar capacitor array structure according to claim 1, which is characterized in that in step 4), institute
Stating electrode under filling perforation includes the first diameter portion being alternately superimposed on and second diameter portion, wherein the first diameter portion is based on described
The first material layer of sacrificial layer is formed, and the second diameter portion is formed based on the second material layer of the sacrificial layer, and described
The lateral dimension in one diameter portion is greater than the lateral dimension of the second diameter portion.
11. the preparation method of columnar capacitor array structure according to claim 10, which is characterized in that described first is straight
The lateral dimension in diameter portion between 40nm~105nm, the lateral dimension of the second diameter portion between 35nm~100nm it
Between；The lateral dimension in the first diameter portion is between 1.08~1.18 times of the lateral dimension of the second diameter portion.
12. the preparation method of columnar capacitor array structure according to claim 1, which is characterized in that in step 6), beat
The specific steps for opening the bracket supporting layer include:
6-1) Yu Suoshu bracket support layer surface forms hole pattern mask layer, and described hole graphic mask layer includes several battle arrays
Arrange the hole of arrangement, wherein described hole appears described on the sacrificial layer between electrode under the adjacent filling perforation
The bottom of bracket supporting layer and the side for the bracket supporting layer being connected with the bottom；And
It 6-2) is based on described hole graphic mask layer, in a manner of Self-aligned etching and using described in the technique of dry etching etching
Bracket supporting layer, in forming at least one described opening corresponding with described hole on the bracket supporting layer, to open
The bracket supporting layer.
13. the preparation method of columnar capacitor array structure according to claim 12, which is characterized in that step 6-1)
In, described hole is arranged in uniform intervals, and each described hole overlaps mutually with electrode under three adjacent filling perforations simultaneously.
14. the preparation method of columnar capacitor array structure according to claim 1, which is characterized in that in step 7), institute
The dielectric constant of capacitor dielectric layer is stated between 4~400；The capacitor dielectric layer choosing constitutes folded from strontium titanates and titanium oxide
The laminated construction and composite calcium iron that laminated construction, zirconium oxide and the aluminium oxide that layer structure, aluminium oxide and hafnium oxide are constituted are constituted
One of mine sections electric material；The thickness of the capacitor dielectric layer is between 10nm~85nm；The thickness of the upper electrode layer
Degree is between 15nm~95nm.
15. the preparation method of columnar capacitor array structure according to claim 1, which is characterized in that after step 8)
Further include: the top electrode obturator surface Yu Suoshu forms top electrode coating.
16. the preparation method of columnar capacitor array structure, feature described according to claim 1~any one of 15 exist
In being also formed with air chamber in the top electrode obturator, and the air chamber is located at the adjacent top electrode in step 8)
Between layer.
17. a kind of columnar capacitor array structure characterized by comprising
Semiconductor substrate, the semiconductor substrate include the contact pad that several are located in memory array structure；
Electrode under filling perforation is incorporated on the contact pad, and electrode has electrode cylinder and in the electrode column under the filling perforation
Be higher by portion on body, and the electrode cylinder side wall is corrugated or zigzag；
Capacitor dielectric layer is formed in the semiconductor lining of surrounding them under the side wall of electrode under the filling perforation and the filling perforation
On bottom；
Upper electrode layer is formed in the capacitor dielectric layer surface；And
Top electrode obturator, the gap being filled between the adjacent upper electrode layer are simultaneously electrically connected with the upper electrode layer.
18. columnar capacitor array structure according to claim 17, which is characterized in that the columnar capacitor array junctions
Structure further includes bracket supporting layer, and the bracket supporting layer at least covers the described of electrode under each filling perforation and is higher by portion, and described
Capacitor dielectric layer is consecutively formed under the filling perforation electrode under the surface and the filling perforation of electrode and the bracket supporting layer
In the semiconductor substrate of surrounding.
19. columnar capacitor array structure according to claim 18, which is characterized in that the columnar capacitor array junctions
Structure further includes protection supporting layer, the periphery for protecting supporting layer to be placed on the electrode cylinder, and the protection supporting layer
Upper surface is in contact with the lower surface for being higher by portion.
20. columnar capacitor array structure according to claim 17, which is characterized in that the semiconductor substrate with it is described
A separation layer is also formed between capacitor dielectric layer.
21. columnar capacitor array structure according to claim 17, which is characterized in that electrode is described under the filling perforation
Electrode cylinder includes the first diameter portion being alternately superimposed on and second diameter portion, wherein the lateral dimension in the first diameter portion is big
In the lateral dimension of the second diameter portion.
22. columnar capacitor array structure according to claim 17, which is characterized in that the columnar capacitor array junctions
Structure further includes top electrode coating, and the top electrode coating is formed in the surface of the top electrode obturator.
23. columnar capacitor array structure described in any one of 7~22 according to claim 1, which is characterized in that on described
Air chamber is also formed in electrode obturator, and the air chamber is between the adjacent upper electrode layer.
24. a kind of organization of semiconductor memory, which is characterized in that the organization of semiconductor memory includes such as claim 17 institute
The columnar capacitor array structure stated.
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