CN113540347A - Capacitor, semiconductor device, electronic apparatus, and method of manufacturing the same - Google Patents
Capacitor, semiconductor device, electronic apparatus, and method of manufacturing the same Download PDFInfo
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- CN113540347A CN113540347A CN202010291407.XA CN202010291407A CN113540347A CN 113540347 A CN113540347 A CN 113540347A CN 202010291407 A CN202010291407 A CN 202010291407A CN 113540347 A CN113540347 A CN 113540347A
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
The application relates to a cylindrical capacitor structure and a semiconductor device, comprising: a semiconductor substrate; a plurality of capacitors on the semiconductor substrate, the capacitors including a lower electrode, a dielectric layer, and an upper electrode; a support located over the top of the lower electrode. The capacitor and the semiconductor device obtained by the manufacturing method can effectively solve the problems of inclination and collapse of the lower electrode in the manufacturing method while ensuring the depth-to-width ratio.
Description
Technical Field
The present application relates to a capacitor and a method of manufacturing the same, and also relates to a semiconductor device, an electronic apparatus, and a method of manufacturing the same including the capacitor.
Background
In recent years, semiconductor manufacturers have been increasingly researching high-integration, high-speed semiconductor devices, as semiconductor users demand semiconductor devices having low power consumption, high storage capacity, and high-speed characteristics. In particular, Dynamic Random Access Memory (DRAM) is widely used as a semiconductor Memory cell because of its free data input/output capability and large storage capacity.
In order to rapidly improve the integration and scalability of the memory, the integration density of the semiconductor device is continuously increased, and the design size standard of the semiconductor device is also continuously reduced. For example, a DRAM is typically a collection of cells, each cell having a mos (metal Oxide semiconductor) transistor and a storage capacitor. As the integration level increases, the size of the semiconductor chip decreases, and the size of the capacitor necessarily decreases, which gradually decreases the spacing between the electrodes and accordingly decreases the capacitance of the capacitor, thereby decreasing the charge storage capacity of the capacitor. However, even in consideration of the increase in the integration degree of the semiconductor memory, it is necessary to make the capacitor have a sufficient capacitance to ensure smooth operation and performance of the semiconductor memory device.
The capacitance of the capacitor depends on the thickness of the dielectric layer, the dielectric constant, and the contact area between the Top Electrode (TE) and the Bottom Electrode (BE). Accordingly, in order to solve the contradiction between the reduction in design size and the improvement in storage capacitance described above, including the increase in the surface area of the storage electrode (capacitor lower electrode), the reduction in the thickness of the dielectric layer, and the use of a dielectric layer having a High dielectric constant (High-k), are methods for increasing the capacitance of the capacitor.
Among these methods, enlarging the surface area of the storage electrode (including maximizing the height of the cylindrical capacitor) is most commonly used. Specifically, a capacitor having a single Cylinder Storage (OCS) structure in which the total effective area of the capacitor can be increased by increasing the vertical area while reducing the horizontal area occupied by the capacitor in the semiconductor memory cell, thereby increasing the Storage capacitance.
As shown in fig. 1, the following methods are commonly used in the prior art to manufacture cylindrical capacitors:
first, referring to fig. 1a, an interlayer insulating layer 102 may be formed on an upper surface of a semiconductor substrate (not shown), then a storage node pad 104 may be formed on the interlayer insulating layer, then an etch stop layer 106 may be formed on surfaces of the interlayer insulating layer 102 and the storage node pad 104, and then a mold oxide layer 106 may be formed on a surface of the etch stop layer 106;
next, referring to fig. 1b, a photoresist pattern is formed on the upper surface of the mold oxide layer 108 using a conventional photolithography process using a hard mask layer (not shown), thereby forming a trench 110 exposing a predetermined region of the lower electrode corresponding to the storage node pad 104, and then removing the hard mask layer;
next, referring to fig. 1c, a conductive material is deposited on the surfaces of the patterned mold oxide layer 108 and the trench 110 to form a lower electrode layer 112;
next, referring to fig. 1d, a blanket filling with a sacrificial oxide 114 is performed, and then a planarization process is performed to expose the top surfaces of the mold oxide layer 108 and the lower electrode layer 112;
next, referring to fig. 1e, the mold oxide layer 108 and the sacrificial oxide 114 are etched away to obtain the lower electrode 112;
then, a dielectric layer and an upper electrode are deposited on the surface of the lower electrode to finally form a cylindrical capacitor (not shown).
However, the storage node electrode using the capacitor having the OCS structure described above has a relatively high Aspect Ratio (Aspect Ratio), that is, its vertical height is much greater than its width. Such high aspect ratio storage node electrodes are prone to tilting (Leaning) or collapsing (Collapse). In particular, when a Mold oxide layer (Mold oxide) formed between storage electrode nodes is removed, the inclination or collapse of the lower electrode is more easily caused due to surface tension. In order to solve the above-mentioned tilt or collapse problem of the electrode, in the process step of manufacturing the lower electrode, a process step of forming a support layer is added, and due to the increasing aspect ratio, even a plurality of support layers are required to be added to prevent the tilt or collapse of the lower electrode, as shown in fig. 1f, a first mold oxide layer 108a is formed on the surface of the etch stop layer 106, then a first support layer 109a is formed, then a second mold oxide layer 108b is formed, and a second support layer 109b is formed, then a hard mask layer 111 is formed on the surface of the second support layer, so that after the subsequent steps and the opening treatment of the support layers, the removal of the mold oxide layer and the sacrificial layer as described above (as shown in fig. 1g), a lower electrode 112 with the first support layer 109a and the second support layer 109b can be finally obtained (as shown in fig. 1 h).
Although the use of the support layer can effectively avoid the tilting or collapse of the lower electrode caused by the high aspect ratio, the deposition step of the support layer and the subsequent opening step of the support layer require more materials, and the completion time of the whole manufacturing process is increased due to the addition of more process steps, thereby reducing the productivity and increasing the cost.
Disclosure of Invention
The purpose of the application is realized by the following technical scheme:
in accordance with one or more embodiments, the present application discloses a cylindrical capacitor structure comprising:
a semiconductor substrate;
a plurality of first capacitors on the semiconductor substrate, the first capacitors including a lower electrode, a first dielectric layer, and a first upper electrode;
and the supports are used for supporting the lower electrode and are positioned on the inner wall and the outer wall of the first dielectric layer.
In accordance with one or more embodiments, the present application also discloses a method of manufacturing a capacitor structure, comprising the process steps of:
providing a semiconductor substrate, wherein a sacrificial mold layer is arranged on the semiconductor substrate;
forming a support layer on the sacrificial mold layer;
etching the supporting layer and the sacrificial mold layer to form a first groove, wherein the first groove corresponds to the position of the lower electrode;
sequentially forming a lower electrode layer, a first dielectric layer and a first upper electrode layer in the first groove, wherein the first upper electrode comprises a first barrier layer and a first electrode layer;
forming a support disk over the first lower electrode, the support disk extending downwardly beyond an inner ring and an outer ring, the inner ring being on top of the first dielectric layer and the outer ring being on top of the remaining support layer;
removing the residual sacrificial mold layer to form a second groove;
and forming a second dielectric layer and a second upper electrode in the second groove, wherein the second upper electrode comprises a second barrier layer and a second electrode layer.
The application also discloses a semiconductor device, an electronic device and the like comprising the capacitor structure or the capacitor structure prepared by the manufacturing method according to one or more embodiments.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application, or may be learned by the practice of the embodiments. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1a to 1h are schematic views illustrating a process for manufacturing a conventional cylindrical capacitor.
Fig. 2a to 2p are schematic views of a process for manufacturing a cylindrical capacitor according to an embodiment of the present application.
Detailed Description
The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. However, the present application is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" and the like include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit of the present application.
Moreover, relative terms, such as "lower" or "bottom" and "upper" or "top," are used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the lower side of another element would then be turned over to be on the upper side of the other element. The exemplary term "lower" therefore includes both "lower" and "upper" directions, depending on the particular orientation of the figure. Likewise, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented above the other elements. Thus, the exemplary term "below" or "beneath.
Embodiments of the present application are described herein with reference to cross-sectional (and/or plan) views that schematically illustrate idealized embodiments of the present application. Likewise, deviations from the schematic shape due to, for example, manufacturing processes and/or tolerances, can be expected. Thus, embodiments of the present application are not to be considered as limiting the particular shapes of regions illustrated herein, but to include deviations in shapes that result, for example, from manufacturing. For example, etched areas illustrated or described as rectangles typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present application.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. It will be understood by those skilled in the art that references to a structural or functional component disposed adjacent to another component may have portions that overlap or underlie the other component.
The application discloses a capacitor structure and a manufacturing method thereof. The shape of the capacitor may be, for example, cylindrical, spherical, rectangular, and any suitable shape that can be obtained by one skilled in the art. The following examples are given by way of example of a capacitor having a cylindrical structure, but the present application is not limited thereto. In one embodiment of the present application, a supporting layer is disposed, and a specific capacitor structure and a manufacturing process are as follows:
as shown in fig. 2o and 2p, the present application illustrates a semiconductor device including a capacitor structure, which may be used in, for example, some kind of electronic device, such as a smart phone, a computer, a tablet computer, a wearable smart device, an artificial smart device, a mobile power supply, and the like. The semiconductor device includes a semiconductor substrate, such as a semiconductor substrate of a circuit element of a mos (metal Oxide semiconductor) transistor, on which functional components (not shown) such as a gate, a source/drain, and a bit line are formed. An Interlayer insulating layer 201(Interlayer Insulation) is formed on the semiconductor substrate; a Landing Pad 202 (bonding Pad) is formed on the interlayer insulating layer 201. A lower electrode 208 is formed on the upper portion of the landing pad 202, and the lower electrode in this embodiment has a cylindrical sidewall and bottom wall, and an upper opening, and the sidewall and bottom wall of the lower electrode 208 form the inside of the lower electrode. A first dielectric layer 209 and a first upper electrode are sequentially formed on the inner side of the sidewall of the lower electrode, wherein the first upper electrode includes a first barrier layer 210 (in other embodiments, the first barrier layer may not be provided as required) and a first upper electrode layer 211, the first barrier layer 210 has a height substantially the same as that of the lower electrode 208, the first dielectric layer 209 is higher than the heights of the lower electrode 208 and the first barrier layer 210 (the heights of the three layers are based on the top height), the first upper electrode layer 211 fills the inner space of the lower electrode, and the lower electrode 208, the first dielectric layer 209 and the first upper electrode form a first capacitor. A second dielectric layer 213 and a second upper electrode are sequentially formed on the outer side of the sidewall of the lower electrode, the second upper electrode includes a second barrier layer 214 (in other embodiments, the second barrier layer may not be provided as needed) and a second upper electrode layer 215, the second upper electrode layer 215 fills the space outside the lower electrode, and the lower electrode 208 and the second upper electrode form a second capacitor. A disk-shaped support 205 'is formed on the upper portion of the inner and outer walls of the first dielectric layer 209, and the support 205' protrudes downward from both sides of the first dielectric layer 209, covers the top of the lower electrode 208 and the first barrier layer 210, and extends in the horizontal direction from the top of the sidewall of the lower electrode that it covers to both the inside and outside of the lower electrode. Meanwhile, since the disk-shaped support 205 ' extends to the outside of the lower electrode, the second upper electrode has a structure with a small top and a large bottom, and the turning plane with the small top and the large bottom is located within the height range of the support 205 ', so that the support 205 ' just covers the turning plane. Uppermost is an upper electrode plate 216 which communicates a first upper electrode inside the lower electrode 208 and a second upper electrode outside the lower electrode 208 to collectively form an upper electrode opposite the lower electrode, thereby completing the construction of an inner first capacitor and an outer second capacitor. In addition, in this embodiment, as can also be seen from fig. 2o and 2p, unlike the prior art, the dielectric layer includes a first dielectric layer 209 located inside the sidewall of the lower electrode 208 and a second dielectric layer 213 located outside the sidewall of the lower electrode 208, and the first and second dielectric layers are not connected (or are discontinuous); similarly, in this embodiment, as can also be seen from fig. 2o and 2p, unlike the prior art, the barrier layer also includes a first barrier layer 210 located inside the sidewall of the lower electrode 208 and a second barrier layer 214 located outside the sidewall of the lower electrode 208, and the first and second barrier layers are also not connected (or are discontinuous).
Next, referring to fig. 2a-2p, the process and the materials used for the semiconductor device according to an embodiment of the present application will be described in further detail:
in the process of the present application, a semiconductor substrate on which a circuit element such as a bcat (buried Channel Array transistor) is already formed may be provided, and functional components (not shown) such as a gate, a source/drain, and a bit line may be formed on the semiconductor substrate.
As shown in fig. 2a, an Interlayer insulating layer 201 may be formed on the semiconductor substrate; a Landing Pad 202 (bonding Pad) is formed on the interlayer insulating layer 201, and the Landing Pad 202 may be made of W, Co, or the like.
Subsequently, an etch stop layer 203(Stopper) may be formed on the surfaces of the interlayer insulating layer 201 and the landing pad 202, the etch stop layer 203 being composed of a nitride material, such as silicon nitride.
Subsequently, a sacrificial Mold layer 204(Mold) may be formed on the surface of the etch stop layer 203, wherein the sacrificial Mold layer 204 is usually made of an Oxide, i.e., an Oxide sacrificial Mold layer (Mold Oxide), and the material thereof may include any one or a combination of two or more of doped oxides, such as SiO2, SiOH, PSG (Phosphosilicate glass), BPSG (Borophosphosilicate glass), SiCOH, TEOS (Tetraethylorthosilicate); the sacrificial layer may also be a multi-layer structure, such as a TEOS layer structure. The sacrificial mold layer may be formed by a suitable process such as Chemical Vapor Deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).
Subsequently, a support layer 205 (support) may be formed by depositing a support material on the surface of the sacrificial oxide film layer 204, where the support material is a nitride, and specifically, any one or a combination of two or more of SiN, SiCN, and BNx may be adopted, and the support material has a high etching selectivity with the materials of the lower electrode, the upper electrode, and the dielectric layer in the capacitor, so as to facilitate subsequent selective etching.
Subsequently, a Hard Mask layer 206(HM, Hard Mask) may be formed on the surface of the support layer 205, and the Hard Mask layer may include a common Hard Mask material such as polysilicon (Poly-Si), doped silicon (Dope-Si), Amorphous Carbon (ACL), a spin-on Silicon (SOH) layer, and the like, which are formed using a CVD process.
The hard mask layer 206 may then be photolithographically processed using conventional lithographic means to obtain a patterned hard mask layer.
As shown in fig. 2b, the sacrificial oxide mold layer 204 may then be etched in accordance with the patterned hard mask layer 206,until the etch stop layer 203 is etched away to expose the landing pad 202, forming the first recess 207, the etching may be performed by a conventional dry etching process, for example, using CH2F2/O2/Ar/CHF3The dry etching process of the fluorine-containing gas; conventional wet etch processes may also be used, including, for example, HF and NH4Mixed buffer solutions of F, e.g. HF: NH mixed in a ratio of about 1: 6 to 1: 104LAL solution of F.
The hard mask layer 206 can then be removed, for example, using a conventional ashing process or the like.
As shown in fig. 2c, a first conductive material may be subsequently deposited on the inner wall of the first groove 207 and the surface of the support layer 205 to form a lower Electrode layer 208(Bottom Electrode); since the prior art generally employs high dielectric constant dielectric materials, e.g. Ta2O5、Al2O3And/or HfO2Etc. are used as dielectric layers of capacitors, and the quality of the interface between the dielectric material and the polysilicon electrode may be reduced. In particular, the quality of the interface between the dielectric material and the polysilicon electrode may decrease as the dielectric constant increases, and therefore, it is preferable to use a high work function metal, such as TiNx、TaNx、WNxAny one or more than two of the refractory metal materials are combined into the lower electrode to replace the traditional polysilicon electrode. The deposition process may employ a common CVD, PECVD, ALD (atomic layer vapor deposition), or the like.
As shown in fig. 2d, a High-k dielectric material (High-k Dielectrics) may be deposited on the surface of the lower electrode layer 208 to form a first dielectric layer 209, which is used to separate the lower electrode layer from the first upper electrode deposited subsequently to form a capacitor; AlO can be adopted as the high dielectric materialx、HfOx、ZrOx、TaOxAnd the like, or a combination of two or more thereof.
As shown in FIG. 2e, a Barrier material (Barrier Metal) of TiN may then be deposited on the surface of the first dielectric layer 209 to form a first Barrier layer 210(Barrier Metal) of the first upper electrodex、TaNx、WNxAnd any one or a combination of two or more of these refractory metal materials. The barrier layer is mainly used to prevent diffusion of materials between layers, and certainly, the process for forming the barrier layer is not necessary, and this step may be omitted as needed, and it is understood that the first barrier layer may not be provided in the structure formed subsequently.
As shown in fig. 2f, subsequently, a second conductive material may be deposited to cover the first barrier layer 210 and fill the first recess 207 to form a first upper Electrode layer 211(Top Electrode) of the first upper Electrode; the second conductive material is metal W or doped silicon. The first upper electrode layer 211 and the first barrier layer 210 collectively form a first upper electrode.
As shown in fig. 2g, the surface of the first upper electrode may then be planarized until the top of the support layer 205 is exposed; the Planarization process employs a Chemical Mechanical Planarization (CMP) process.
As shown in fig. 2h, the lower electrode layer 208 and the first barrier layer 210 on both sides of the first dielectric layer 209 may be selectively etched back to form an etch-back trench 212; a relatively simple and easy wet etch process may be used to etch back portions of lower electrode layer 208 and first barrier layer 210 together.
As shown in fig. 2i, the support material may then be deposited over the entire semiconductor substrate again to backfill the etch-back trenches until the surface of the support layer 205' is substantially filled, the same support material may be used for both support layers, and the deposition process may be performed using ALD. In the capacitor structure of the present application, as shown in fig. 2p, since the first dielectric layer 209 is not etched back, the top height of the first dielectric layer 209 is higher than the height of the selectively etched back lower electrode layer 208 and the first barrier layer 210 on both sides thereof, and therefore, the support 205' is located on both sides of the inner wall and the outer wall of the first dielectric layer 209; meanwhile, the support 205' is located above the top of the bottom electrode 208 and extends from the top of the sidewall of the bottom electrode 208 to the inside and outside of the bottom electrode 208 along the horizontal direction, while the height of the support is lower than the top of the bottom electrode and is located outside the sidewall of the bottom electrode in the prior art.
As shown in fig. 2j, the surface of the filled support layer 205' may be subsequently subjected to an opening process to expose the remaining sacrificial oxide layer 204; the perforated unit Pattern has any one or a combination of two or more of a Linear Type Slit (Linear Type Slit) and a Mesh Pattern (Mesh Pattern). The support layer 205' after opening becomes the structure of the support disc. Specifically, in order to form the opening and the support disc structure, a mask in the shape of a support disc may be first formed on the surface of the support layer 205 ', and then the support layer 205' may be etched according to the mask to form the opening and leave the support disc structure, and then the mask layer may be removed by an ashing process or the like. After the support disk is formed over first dielectric layer 209, it can be seen that the support disk extends downward beyond an inner ring and an outer ring, where the inner ring is over the top of the first barrier layer 210 remaining after etch back and the outer ring is over the top of the lower electrode layer 208 remaining after etch back.
As shown in fig. 2k, subsequently, the remaining sacrificial oxide mold layer 204 may be removed by opening, etching to form a second recess 212; the etching here adopts a wet etching process, and although the wet etching process is adopted, since the lower electrode layer 208 is not isolated but supported by the first dielectric layer 209, the first barrier layer 210, and particularly the filled first upper electrode layer 211 formed inside the lower electrode layer 208, the surface tension applied thereto is at least reduced to 1/2 of the original manufacturing method, thereby effectively avoiding the problems of tilting and collapse caused by the surface tension caused by the wet etching process. Due to the advantages, compared with the prior art that even more than two support layers are needed, the number of the support layers used can be reduced in the embodiment of the present application, for example, only one support layer can be provided, and unnecessary process steps related to deposition, cleaning and the like are naturally reduced, so that the process is saved, and the cost is saved.
As shown in fig. 2l, subsequently, a high dielectric material may be deposited on the inner walls of the second recess 212 and the surface of the support layer 205' to form a second dielectric layer 213; AlO can be adopted as the high dielectric materialx、HfOx、ZrOx、TaOxAnd the like, or a combination of two or more thereof;the deposition process is, for example, an ALD process.
As shown in fig. 2m, subsequently, a barrier material may be deposited on the surface of the second dielectric layer 213 to form a second barrier layer 214; the barrier material is TiNx、TaNx、WNxAny one or a combination of two or more of the refractory metal materials; the deposition process is an ALD process. The barrier layer is mainly used to prevent diffusion of materials between layers, and certainly, the process for forming the barrier layer is not necessary, and this step may be omitted as needed, and it is understood that the structure formed subsequently will not have the second barrier layer.
Subsequently, a second conductive material may be deposited to cover the second barrier layer 214 and fill the second recess 212 to form a second upper electrode layer 215; the second conductive material is metal W or doped silicon. The deposition process may be CVD, PECVD, or the like. The second upper electrode layer 215 and the second barrier layer 214 form a second upper electrode. Due to the special structure of the formed support disc, the formed second upper electrode can present a structure with a small upper part and a large lower part, the turning surface with the small upper part and the large lower part is positioned in the height range of the support layer, and the support layer can cover the turning surface.
As shown in fig. 2n, the surface of the second upper electrode layer 215 may then be planarized until the top surface of the support layer is exposed; the Planarization process employs a Chemical Mechanical Planarization (CMP) process.
As shown in fig. 2o, the support layer 205 'may then be etched back to expose the first upper electrode layer 211, and the remaining support layer becomes the support 205' in the capacitor structure, which can serve as a support for the high aspect ratio lower electrode. Wherein, the back etching support layer is plasma etching which is carried out under the state of Low Bias Power (Low Bias Power) or No Bias Power (No Bias Power) by adopting fluorine-based gas or mixed gas containing fluorine-based gas; wherein the fluorine-based gas is selected from CHF3、CH2F2、CHF3、CHxFy、NF3、SF6Any one or two or more ofAnd (3) mixing. By adopting the etching gas, high selectivity can be generated on the material of the supporting layer, the lower electrode, the dielectric layer and the material of the top electric layer, so that the supporting layer can be effectively etched back, and the lower electrode, the dielectric layer and the top electric layer are reserved.
As shown in fig. 2p, subsequently, a second conductive material may be deposited again to form an upper electrode Plate 216(TE Plate) to conduct the exposed first and second upper electrode layers 211 and 215; the second conductive material is metal W or doped silicon.
In addition to the above embodiments, the present application can also provide two or more support layers to obtain a larger aspect ratio than the existing cylindrical capacitor, so as to meet the requirements of higher integration and decreasing design size. The method can be realized by only depositing two oxide sacrificial mold layers and two supporting layers respectively and by the aid of the manufacturing method for depositing the first dielectric layer, the second dielectric layer, the barrier layer and the upper electrode respectively.
The cylindrical capacitor and the semiconductor device obtained by the manufacturing method can effectively solve the problems of inclination and collapse of the lower electrode in the manufacturing method while ensuring the depth-to-width ratio.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (17)
1. A cylindrical capacitor structure, comprising:
a semiconductor substrate;
a plurality of first capacitors on the semiconductor substrate, the first capacitors including a lower electrode, a first dielectric layer, and a first upper electrode;
and the supports are used for supporting the lower electrode and are positioned on the inner wall and the outer wall of the first dielectric layer.
2. The capacitor structure of claim 1, wherein:
the top of the first dielectric layer is higher than the top of the lower electrode.
3. The capacitor structure of claim 1, wherein:
the first upper electrode comprises a first barrier layer and a first electrode layer; wherein the top of the first dielectric layer is higher than the top of the first barrier layer.
4. The capacitor structure of claim 1, wherein:
the capacitor further comprises a second dielectric layer and a second upper electrode which are positioned on the outer side of the side wall of the lower electrode, and the lower electrode, the second dielectric layer and the second upper electrode form a second capacitor.
5. The capacitor structure of claim 4, wherein:
the first upper electrode and the second upper electrode are in communication.
6. The capacitor structure of claim 1, wherein:
the second upper electrode is provided with a mechanism with a small upper part and a big lower part, and the turning surface with the small upper part and the big lower part is positioned in the height range of the support.
7. The capacitor structure of claim 6, wherein: the support covers the turning surface.
8. The capacitor structure of any one of claims 1-7, wherein:
the support extends from the top of the sidewall of the lower electrode in the horizontal direction to both the inside and outside of the lower electrode.
9. The capacitor structure of any one of claim 8, wherein:
the support covers the lower electrode and the first barrier layer.
10. The capacitor structure of any one of claims 1-7, wherein:
the support comprises a nitride material; further, the nitride material comprises SiN, SiCN, BNxAny one or a combination of two or more of them.
11. A method for manufacturing a capacitor structure comprises the following process steps:
providing a semiconductor substrate, wherein a sacrificial mold layer is arranged on the semiconductor substrate;
forming a support layer on the sacrificial mold layer;
etching the supporting layer and the sacrificial mold layer to form a first groove, wherein the first groove corresponds to the position of the lower electrode;
sequentially forming a lower electrode layer, a first dielectric layer and a first upper electrode layer in the first groove, wherein the first upper electrode comprises a first barrier layer and a first electrode layer;
forming a support disk over said first dielectric layer, the support disk extending downwardly beyond an inner ring and an outer ring, the inner ring being on top of said first barrier layer and the outer ring being on top of said lower electrode layer;
removing the residual sacrificial mold layer to form a second groove;
and forming a second dielectric layer and a second upper electrode in the second groove, wherein the second upper electrode comprises a second barrier layer and a second electrode layer.
12. The manufacturing method according to claim 11, characterized in that: the step of forming a support disk over the first lower electrode comprises:
carrying out planarization treatment until the top of the supporting layer is exposed;
selectively etching to remove the lower electrodes positioned at two sides of the first dielectric layer and the top of the first barrier layer;
filling a support material layer on the whole semiconductor substrate;
and etching the support material layer to form the support disc.
13. The manufacturing method according to claim 12, characterized in that: the step of etching the layer of support material to form the support disk comprises:
forming a mask in a shape of a support disk on the layer of support material;
etching the support material layer;
the mask is removed.
14. The manufacturing method according to claim 11, characterized in that: after forming the second upper electrode, the method further includes:
carrying out a CMP process on the second upper electrode layer until the supporting disc is exposed;
etching back the support disc until the top of the support disc is removed;
filling the second upper electrode layer material.
15. A semiconductor device comprising a capacitor structure according to any one of claims 1 to 10 or a capacitor structure produced by a method according to any one of claims 11 to 14.
16. An electronic device comprising the semiconductor device according to claim 15.
17. The electronic device of claim 16, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI802218B (en) * | 2022-01-12 | 2023-05-11 | 力晶積成電子製造股份有限公司 | Capacitor structure and manufacturing method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090146256A1 (en) * | 2007-12-05 | 2009-06-11 | Elpida Memory, Inc. | Method of forming semiconductor device including capacitor and semiconductor device including capacitor |
| US20090294907A1 (en) * | 2008-06-02 | 2009-12-03 | Stefan Tegen | Semiconductor component with mim capacitor |
| KR20100051344A (en) * | 2008-11-07 | 2010-05-17 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming using the same |
| US20100176486A1 (en) * | 2009-01-13 | 2010-07-15 | Elpida Memory, Inc. | Semiconductor device and method of manufacturing the same |
| CN107393909A (en) * | 2017-07-25 | 2017-11-24 | 睿力集成电路有限公司 | Double sided capacitor and its manufacture method |
| CN109148426A (en) * | 2018-09-29 | 2019-01-04 | 长鑫存储技术有限公司 | Capacitance structure and forming method thereof |
| CN110504284A (en) * | 2018-05-17 | 2019-11-26 | 长鑫存储技术有限公司 | Columnar capacitor array structure and preparation method |
-
2020
- 2020-04-14 CN CN202010291407.XA patent/CN113540347B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090146256A1 (en) * | 2007-12-05 | 2009-06-11 | Elpida Memory, Inc. | Method of forming semiconductor device including capacitor and semiconductor device including capacitor |
| US20090294907A1 (en) * | 2008-06-02 | 2009-12-03 | Stefan Tegen | Semiconductor component with mim capacitor |
| KR20100051344A (en) * | 2008-11-07 | 2010-05-17 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming using the same |
| US20100176486A1 (en) * | 2009-01-13 | 2010-07-15 | Elpida Memory, Inc. | Semiconductor device and method of manufacturing the same |
| CN107393909A (en) * | 2017-07-25 | 2017-11-24 | 睿力集成电路有限公司 | Double sided capacitor and its manufacture method |
| CN110504284A (en) * | 2018-05-17 | 2019-11-26 | 长鑫存储技术有限公司 | Columnar capacitor array structure and preparation method |
| CN109148426A (en) * | 2018-09-29 | 2019-01-04 | 长鑫存储技术有限公司 | Capacitance structure and forming method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI802218B (en) * | 2022-01-12 | 2023-05-11 | 力晶積成電子製造股份有限公司 | Capacitor structure and manufacturing method thereof |
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