CN208753321U

CN208753321U - Columnar capacitor array structure

Info

Publication number: CN208753321U
Application number: CN201820732886.2U
Authority: CN
Inventors: 徐政业
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-05-17
Filing date: 2018-05-17
Publication date: 2019-04-16
Anticipated expiration: 2028-05-17

Abstract

The utility model provides a column capacitor array structure, include: a semiconductor substrate including a plurality of contact pads; a via-filling lower electrode combined on the contact pad, wherein the sidewall of the via-filling lower electrode is corrugated or zigzag; a planar support layer covering the upper surface of each of the lower electrodes; the capacitor dielectric layer is formed on the side wall of the filling hole lower electrode and the semiconductor substrate around the filling hole lower electrode; the upper electrode layer is formed on the surface of the capacitance dielectric layer; and the upper electrode filling body is filled in the gap between the adjacent upper electrode layers and is electrically connected with the upper electrode layers. The utility model discloses can further reduce the electric capacity size, have great residual space between the adjacent electric capacity, form the column bottom electrode that the lateral wall is corrugate or cockscomb structure, can increase the surface area of electric capacity, improve the electric capacity ability, adapt to the size and shrink a little, form planar support supporting layer, can prepare the supporting layer that needs thickness, have the aspect ratio advantage, improve support strength, simplify preparation technology and device structure.

Description

Columnar capacitor array structure

Technical field

The utility model belongs to technical field of integrated circuits, more particularly to a kind of columnar capacitor array structure.

Background technique

Dynamic RAM (Dynamic Random Access Memory, referred to as: DRAM) is commonly used in computer Semiconductor storage unit, be made of many duplicate storage units.In 20nm DRAM processing procedure below, DRAM is mostly used greatly The capacitor structure of stacking-type, capacitor (Capacitor) are the cylindrical shapes of vertical high-aspect-ratio.

Currently, as shown in Figure 1, two-sided capacitance structure includes substrate 11, contact pad 12, lower electrode layer 13, capacitor dielectric Layer 14 and upper electrode layer 15, wherein the two-sided capacitor of Cylinder is current main industry technology, cylindrical in array region Bottom and deposited on sidewalls lower electrode material in deep hole, then using every three deep holes as basic unit, top aperture will in its center The lower electrode of connection separates, and is formed using SiN as the rack for test tube structure of supporting layer, high k dielectric is deposited in deep hole (high dielectric material) and upper electrode material are with the reduction of technology node size, this capacitor production program is in technique It is difficult to realize, in the technical method of existing production capacitor, the diminution of capacitor size can bring that technical difficult and it is deposited The reduction of charge capability is stored up, therefore, pillar capacitor (column capacitor) is made as future thrust, however, existing Pillar Capacitor is there are the lower defect of electrode plate surface product, and accomplishing bigger depth-to-width ratio, there is biggish technical difficulty, meanwhile, it is advanced The support of the capacitor of wide ratio is also urgent problem to be solved in the industry.

Therefore, how a kind of columnar capacitor array structure and preparation method are provided, with solve in the prior art capacitor it Between the problems such as remaining space is smaller, dimensional contraction is small and capacitor relative surface area is small, support construction is complicated be necessary.

Utility model content

In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of columnar capacitor arrays Structure, for solve remaining space is smaller between capacitor, dimensional contraction is small in the prior art and capacitor relative surface area is small, The problems such as support construction is complicated.

In order to achieve the above objects and other related objects, the utility model provides a kind of system of columnar capacitor array structure Preparation Method includes the following steps:

1) semi-conductive substrate is provided, the semiconductor substrate includes the Contact welding that several are located in memory array structure Disk；

2) sacrificial layer is formed in Yu Suoshu semiconductor substrate, the sacrificial layer includes the first material layer being alternately superimposed on and Two material layers, under default etching condition, the etch rate of the first material layer is greater than the etching speed of the second material layer Rate；

3) the graphical sacrificial layer is to form capacitor hole, wherein the capacitor hole appears the contact pad, and described Capacitor hole has corrugated or indented sidewall, lateral recessed toward the first material layer；

4) each capacitor hole is filled to form electrode under filling perforation, and the upper surface separation of electrode appears under the filling perforation In the sacrificial layer, the lower surface of electrode is bonded to the corresponding contact pad under the filling perforation；

5) surface of the structure obtained in step 4) deposits a plane formula bracket supporting layer, and the plane formula bracket supports Layer cover the upper surface of electrode under the filling perforation and with and the filling perforation under the sacrificial layer of surrounding them be mechanically connected；

6) at least one opening is formed on Yu Suoshu plane formula bracket supporting layer, to open the plane formula bracket support Layer, and the sacrificial layer is removed based on the opening；

7) surface of the structure obtained in step 6) forms capacitor dielectric layer, and is formed in the surface of the capacitor dielectric layer Upper electrode layer；And

8) surface of Yu Suoshu upper electrode layer forms top electrode obturator, and the top electrode obturator is filled in adjacent institute The gap between upper electrode layer is stated, and is electrically connected with the upper electrode layer.

As a kind of preferred embodiment of the utility model, between step 1) and step 2) further include: Yu Suoshu semiconductor lining Bottom surface forms a separation layer, and the sacrificial layer in step 2) is formed in the surface of the separation layer.

As a kind of preferred embodiment of the utility model, the thickness of the separation layer is between 5nm~45nm；It is described every Absciss layer includes silicon nitride layer；The separation layer is formed using one of atomic layer deposition and low-pressure chemical vapor deposition.

As a kind of preferred embodiment of the utility model, in step 2), the first material layer includes boron doped oxidation Silicon layer, the second material layer include silicon oxide layer.

As a kind of preferred embodiment of the utility model, in step 2), the second material layer with a thickness of described first 1.5~3 times of layer thickness；The thickness of the first material layer is between 3nm~30nm, the thickness of the second material layer Degree is between 20nm~50nm；The thickness of the sacrificial layer is between 1 μm~1.5 μm.

As a kind of preferred embodiment of the utility model, in step 2), the thickness of the second material layer is between described Between 1.5~3 times of one layer thickness.

As a kind of preferred embodiment of the utility model, between step 2) and step 3) further include: Yu Suoshu sacrificial layer Surface forms protection supporting layer (104), and etches the protection support based on the Patterned masking layer simultaneously in step 3) Layer.

As a kind of preferred embodiment of the utility model, in step 3), the specific steps for forming the capacitor hole include:

3-1) in the Patterned masking layer for forming the window with array arrangement in the structure that step 2) obtains, and based on institute It states Patterned masking layer and the sacrificial layer is etched using the technique of dry etching, it is perforative up and down to be formed in the sacrificial layer Through-hole, and the through-hole through-hole corresponding and described with the window appears the contact pad；And

3-2) use the technique etch step 3-1 of wet etching) side wall of the through-hole that is formed, to form side wall in wave Line shape or the jagged capacitor hole.

As a kind of preferred embodiment of the utility model, in step 4), the specific steps packet of electrode under the filling perforation is formed It includes:

The continuous lower electrode material of sacrificial layer surface deposition 4-1) in Yu Suoshu capacitor hole and around the capacitor hole The bed of material；And

The lower electrode material layer 4-2) is planarized, and stops at the sacrificial material layer, to divide the lower electrode material The bed of material forms electrode under the discontiguous filling perforation between each other.

As a kind of preferred embodiment of the utility model, in step 4), electrode includes be alternately superimposed under the filling perforation One diameter portion and second diameter portion, wherein the first diameter portion is formed based on the first material layer of the sacrificial layer, and described Two diameter portions are formed based on the second material layer of the sacrificial layer, and the lateral dimension in the first diameter portion is greater than described second The lateral dimension in diameter portion.

As a kind of preferred embodiment of the utility model, the lateral dimension in the first diameter portion is between 40nm~105nm Between, the lateral dimension of the second diameter portion is between 35nm~100nm.

As a kind of preferred embodiment of the utility model, the lateral dimension in the first diameter portion is between the second diameter Between 1.08~1.18 times of the lateral dimension in portion.

As a kind of preferred embodiment of the utility model, in step 6), the specific of the plane formula bracket supporting layer is opened Step includes:

Hole pattern mask layer 6-1) is formed on Yu Suoshu plane formula bracket supporting layer, described hole graphic mask layer includes The hole of several array arrangements, wherein described hole appears and is located at the sacrificial layer between electrode under the adjacent filling perforation On the plane formula bracket supporting layer；

It 6-2) is based on described hole graphic mask layer, the plane formula bracket supporting layer is etched, in the plane formula branch At least one described opening corresponding with described hole is formed on frame supporting layer, to open the plane formula bracket supporting layer.

As a kind of preferred embodiment of the utility model, step 6-1) in, described hole is in a strip shape to be intervally arranged, and each A described hole is located between the gap that electrode is constituted under four adjacent filling perforations.

As a kind of preferred embodiment of the utility model, in step 7), the dielectric constant of the capacitor dielectric layer between 4~ Between 400；The capacitor dielectric layer choosing constitutes folded from laminated construction, aluminium oxide and the hafnium oxide that strontium titanates and titanium oxide are constituted One of laminated construction and compound calcium nutrition Ferroelectric material that layer structure, zirconium oxide and aluminium oxide are constituted；The capacitor The thickness of dielectric layer is between 10nm~85nm；The thickness of the upper electrode layer is between 15nm~95nm.

As a kind of preferred embodiment of the utility model, after step 8) further include: Yu Suoshu top electrode obturator surface Form top electrode coating.

As a kind of preferred embodiment of the utility model, in step 8), air is also formed in the top electrode obturator Chamber, and the air chamber is between the adjacent upper electrode layer.

The utility model also provides a kind of columnar capacitor array structure, comprising:

Semiconductor substrate, the semiconductor substrate include the contact pad that several are located in memory array structure；

Electrode under filling perforation is incorporated on the contact pad, and the side wall of electrode is corrugated under the filling perforation or zigzag；

Plane formula bracket supporting layer, the unilateral plane formula bracket supporting layer cover the upper table of electrode under each filling perforation Face；

Capacitor dielectric layer is formed in the semiconductor of surrounding them under the side wall of electrode and the filling perforation under the filling perforation On substrate；

Upper electrode layer is formed in the capacitor dielectric layer surface；And

Top electrode obturator, the top electrode obturator are filled in the gap between the adjacent upper electrode layer, and with institute State upper electrode layer electrical connection.

As a kind of preferred embodiment of the utility model, the columnar capacitor array structure further includes protection supporting layer, It is described protection supporting layer be placed on electrode under the filling perforation upper surface periphery, and it is described protection supporting layer upper surface with it is described The lower surface of plane formula bracket supporting layer is in contact.

As a kind of preferred embodiment of the utility model, also formed between the semiconductor substrate and the capacitor dielectric layer There is a separation layer.

As a kind of preferred embodiment of the utility model, under the filling perforation electrode include the first diameter portion being alternately superimposed on and Second diameter portion, wherein the lateral dimension in the first diameter portion is greater than the lateral dimension of the second diameter portion.

As a kind of preferred embodiment of the utility model, the lateral dimension in the first diameter portion is between 40nm~105nm Between, the lateral dimension of the second diameter portion is between 35nm~100nm；The thickness in the first diameter portion is between 3nm Between~30nm, the thickness of the second diameter portion is between 20nm~50nm.

As a kind of preferred embodiment of the utility model, the lateral dimension in the first diameter portion is between the second diameter Between 1.08~1.18 times of the lateral dimension in portion；The thickness of the second diameter portion is between first diameter portion thickness Between 1.5~3 times.

As a kind of preferred embodiment of the utility model, the columnar capacitor array structure further includes top electrode covering Layer, the top electrode coating are formed in the surface of the top electrode obturator.

As a kind of preferred embodiment of the utility model, the dielectric constant of the capacitor dielectric layer is between 4~400； The laminated construction of laminated construction, aluminium oxide and hafnium oxide composition that the capacitor dielectric layer choosing is constituted from strontium titanates and titanium oxide, One of laminated construction and compound calcium nutrition Ferroelectric material that zirconium oxide and aluminium oxide are constituted；The capacitor dielectric layer Thickness is between 10nm~85nm；The thickness of the upper electrode layer is between 15nm~95nm.

As a kind of preferred embodiment of the utility model, it is also formed with air chamber in the top electrode obturator, and described Air chamber is between the adjacent upper electrode layer.

The utility model also provides a kind of organization of semiconductor memory, and the organization of semiconductor memory includes such as above-mentioned It anticipates columnar capacitor array structure described in a scheme.

As described above, the columnar capacitor array structure of the utility model, has the advantages that

The utility model provides a kind of columnar capacitor array structure and preparation method, can by the structure of the utility model To further reduce capacitor size, there is biggish remaining space between adjacent capacitor, size has better contractility, By forming electrode under side wall is corrugated or jagged column, electricity can be increased in the case where not increasing capacitor height It is miniature to adapt to size to improve capacitive energy for the surface area of appearance, in addition, formation is flat on electrode under filling perforation for the utility model Face formula bracket supporting layer allows to prepare the supporting layer for needing thickness, has depth-width ratio (high aspect ratio) advantage, increases The contact area for adding supporting layer and capacitor arrangement improves mechanical support intensity, and simplifies preparation process and device entirety Structure.

Detailed description of the invention

Fig. 1 is shown as the structure of capacitor in the prior art.

Fig. 2 is shown as the preparation technology flow chart of the array of capacitors structure of the utility model.

Fig. 3 is shown as providing the top view of semiconductor substrate in the preparation of the array of capacitors structure of the utility model.

Fig. 4 is shown as the sectional view in the direction A-B in Fig. 3.

Fig. 5 is shown as forming the structural schematic diagram of sacrificial layer in the preparation of the array of capacitors structure of the utility model.

Fig. 6 is shown as forming the structural schematic diagram of separation layer in the preparation of the array of capacitors structure of the utility model.

Fig. 7 is shown as forming the structural representation of protection supporting layer in the preparation of the array of capacitors structure of the utility model Figure.

Fig. 8 is shown as the top view of Fig. 7 structure, and Fig. 7 is the sectional view in the direction A-B in Fig. 8.

Fig. 9 is shown as forming the schematic diagram of through-hole in the preparation of the array of capacitors structure of the utility model.

Figure 10 is shown as the top view of Fig. 9 structure, and Fig. 9 is the sectional view in the direction A-B in Figure 10.

Figure 11 is shown as forming the structural schematic diagram in capacitor hole in the preparation of the array of capacitors structure of the utility model.

Figure 12 is shown as the top view of Figure 11 structure, and Figure 11 is the sectional view in the direction A-B in Figure 12.

The structure that Figure 13 is shown as being formed lower electrode material layer in the preparation of the array of capacitors structure of the utility model is shown It is intended to.

Figure 14 is shown as the top view of Figure 13 structure, and Figure 13 is the sectional view in the direction A-B in Figure 14.

Figure 15 is shown as forming the structural representation of electrode under filling perforation in the preparation of the array of capacitors structure of the utility model Figure.

Figure 16 is shown as the top view of Figure 15 structure, and Figure 15 is the sectional view in the direction A-B in Figure 16.

Figure 17 is shown as forming the knot of plane formula bracket supporting layer in the preparation of the array of capacitors structure of the utility model Structure schematic diagram.

Figure 18 is shown as the top view of Figure 17 structure, and Figure 17 is the sectional view in the direction A-B in Figure 18.

The preparation that Figure 19 is shown as the array of capacitors structure of the utility model forms the diagram of hole photoresist layer.

Figure 20 is shown as the top view of Figure 19 structure, and Figure 19 is the sectional view in the direction A-B in Figure 20.

The preparation that Figure 21 is shown as the array of capacitors structure of the utility model forms the diagram of hole pattern mask layer.

Figure 22 is shown as the top view of Figure 21 structure, and Figure 21 is the sectional view in the direction A-B in Figure 22.

Figure 23 is shown as opening showing for plane formula bracket supporting layer in the preparation of the array of capacitors structure of the utility model It is intended to.

Figure 24 is shown as being formed on plane formula bracket supporting layer in the preparation of the array of capacitors structure of the utility model and open Schematic diagram behind hole.

Figure 25 is shown as the top view of Figure 24 structure, and Figure 24 is the sectional view in the direction A-B in Figure 25.

Figure 26 is shown as removing the structural schematic diagram of sacrificial layer in the preparation of the array of capacitors structure of the utility model.

Figure 27 is shown as the top view of Figure 26 structure, and Figure 26 is the sectional view in the direction A-B in Figure 27.

Figure 28 is shown as forming the structural representation of capacitor dielectric layer in the preparation of the array of capacitors structure of the utility model Figure.

Figure 29 is shown as the top view of Figure 28 structure, and Figure 28 is the sectional view in the direction A-B in Figure 29.

Figure 30 is shown as forming the structural schematic diagram of upper electrode layer in the preparation of the array of capacitors structure of the utility model.

Figure 31 is shown as the top view of Figure 30 structure, and Figure 30 is the sectional view in the direction A-B in Figure 31.

The structure that Figure 32 is shown as being formed top electrode obturator in the preparation of the array of capacitors structure of the utility model is shown It is intended to.

Figure 33 is shown as the top view of Figure 32 structure, and Figure 32 is the sectional view in the direction A-B in Figure 33.

The structure that Figure 34 is shown as being formed top electrode coating in the preparation of the array of capacitors structure of the utility model is shown It is intended to.

Figure 35 is shown as the top view of Figure 34 structure, and Figure 34 is the sectional view in the direction A-B in Figure 35.

Component label instructions

11 substrates

12 contact pads

13 lower electrode layers

14 capacitor dielectric layers

15 upper electrode layers

100 semiconductor substrates

101 contact pads

102 sacrificial layers

102a first material layer

102b second material layer

103 separation layers

104 protection supporting layers

105 through-holes

106 capacitor holes

107 lower electrode material layers

Electrode under 108 filling perforations

108a first diameter portion

108b second diameter portion

109 plane formula bracket supporting layers

110 hole pattern mask layers

110a hole

111 hole photoresist layers

111a hole window

112 openings

113 capacitor dielectric layers

114 upper electrode layers

115 top electrode obturators

116 air chambers

117 top electrode coatings

118 mask pattern material layers

D1 first material layer thickness

D2 second material layer thickness

D3 separation layer thickness

D4 first diameter portion lateral dimension

D5 second diameter portion lateral dimension

D6 capacitor dielectric thickness degree

D7 upper electrode layer thickness

S1~S8 step 1)~step 8)

Specific embodiment

Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer With carrying out various modifications or alterations under the spirit without departing from the utility model.

Fig. 2 is please referred to Figure 35.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of utility model, though it is only shown with related component in the utility model rather than when according to actual implementation in diagram Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind Become, and its assembly layout form may also be increasingly complex.

As shown in Fig. 2~35, in order to achieve the above objects and other related objects, the utility model provides a kind of column capacitor The preparation method of device array structure, includes the following steps:

5) surface of the structure obtained in step 4) deposits a plane formula bracket supporting layer, and the plane formula bracket supports Layer covers the upper surface of electrode under the filling perforation and is mechanically connected with the sacrificial layer of surrounding them under the filling perforation；

The columnar capacitor structure and its preparation process of the utility model are described in detail below in conjunction with attached drawing.

Firstly, as in Fig. 2 S1 and Fig. 3~4 shown in, carry out step 1), semi-conductive substrate 100 is provided, it is described partly to lead Body substrate 100 includes that several are located at the contact pad 101 in memory array structure.

Specifically, being formed with memory array structure in the semiconductor substrate 100, the memory array structure includes more A contact pad 101 (NC connects the contact pad of transistor), the memory array structure further includes having transistor Character line (Word line) and bit line (Bitline), the contact pad 101 are electrically connected in the memory array structure Transistor source further includes the M0 (inter-connection) made in peripheral circuit area in the semiconductor substrate.

In addition, the contact pad 101 can be but be not limited only to arrange in six square arrays, the capacitor with subsequent production The arrangement of array structure is corresponding.It is further preferred that the semiconductor substrate 100 further includes semiconductor substrate, it is described to connect Touching pad 101 is formed in the semiconductor substrate surface, in addition, be isolated between the contact pad 101 by wall, The material of the wall can be silicon nitride (SiN), silica (SiO₂), aluminium oxide (Al₂O₃) in any one or it is any Two or more combinations, in this example, the material selection of the wall are SiN.

Then, as in Fig. 2 S2 and Fig. 5~8 shown in, carry out step 2), formed in Yu Suoshu semiconductor substrate 100 and sacrificed Layer 102, the sacrificial layer 102 include the first material layer 102a and second material layer 102b being alternately superimposed on, in default etching item Under part, the etch rate of the first material layer 102a is greater than the etch rate of the second material layer 102b.

Specifically, in this step, form sacrificial layer 102 in favor of subsequent and prepare electrode for capacitors and support construction, In, it is preferred to use atom layer deposition process (Atomic Layer Deposition) or low pressure chemical vapor depositing operation (Low Pressure Chemical Vapor Deposition) form the sacrificial layer 102, wherein the first material layer 102a It is preferred with the stacking order of second material layer 102b are as follows: the bottom and top are slower second material of etch rate Layer 102b, the size of electrode under the filling perforation being subsequently formed so as to reasonable disposition are conducive to the stability for improving capacitor.

In addition, on a preset condition based, such as under same etching condition, the etch rate of the first material layer 102a is greater than The etch rate of the second material layer 102b, thus to be subsequently formed electrode under the column with corrugated or indented sidewall Offer condition, is embodied in, subsequent capacitance hole etching processing procedure preferably comprise hole formation step with and subsequent hole cut Dry etching can be used in facial contour modification step, hole formation step, and wet etching can be used in hole cross section profile modification step Or dry etching, in the same corrosive liquid of wet etching, the etch rate of the second material layer 102b is less than described first The etch rate of material layer 102a, so that in use corrosive liquid to the second material layer 102b and first material layer 102a When being corroded, the lateral encroaching removal rate of the second material layer 102b is (i.e. along the length of the second material layer 102b The removal rate in direction) much smaller than the first material layer 102a laterally remove rate (i.e. along the first material layer 102a Length direction removal rate).The first material layer and the second material layer are as sacrificial layer in subsequent technique process In can be removed, it is preferable that a wherein second material layer 102b for the sacrificial layer 102 is relative to the first material layer 102a is prepared, and further increase the electric property of device architecture closer in the semiconductor substrate 100 to be conducive to device And mechanical stability.

As an example, the thickness D1 of the first material layer 102a is between 3nm~30nm in step 2), described The thickness D2 of two material layer 102b is between 20nm~50nm.

As an example, 1.5~3 times between the first material layer 102a thickness of the thickness of the second material layer 102b Between.

As an example, the thickness of the sacrificial layer 102 is between 1 μm~1.5 μm.

As an example, the first material layer 102a includes boron doped silicon oxide layer in step 2), second material Layer 102b includes silicon oxide layer.

Specifically, in one example, the first material layer 102a includes boron doped silicon oxide layer, second material Layer 102b includes silicon oxide layer, can be formed by way of alternating deposit (pulse gas injection).In addition, described The number of plies of first material layer 102a and the second material layer 102b can be set according to actual needs, it is preferable that this reality It applies in example, total number of plies of the first material layer 102a and the second material layer 102b are greater than 20 layers, and ensure at 1.3 μm It is greater than with total number of plies 20 layers of the first material layer 102a and the second material layer 102b in height, in addition, described the The thickness of one material layer 102a is preferably between 5nm~15nm, the thickness of the second material layer be preferably between 22nm~ Between 35nm；The thickness of the sacrificial layer is preferably between 1.2 μm~1.4 μm.

In a preferred embodiment, the thickness of the second material layer 102b is the thickness of the first material layer 102a 1.5~3 times, so that finally formed 106 side wall of capacitor hole is uniform and smooth, and stable structure, and make finally formed Electrode is stablized as the capacitor arrangement of lower electrode under the filling perforation.

As an example, between step 1) and step 2) further include: 100 surface of Yu Suoshu semiconductor substrate forms a separation layer 103, and the sacrificial layer 102 in step 2) is formed in the surface of the separation layer 103.

As an example, the thickness D3 of the separation layer 103 is between 5nm~45nm

As an example, the separation layer 103 includes silicon nitride layer.

Specifically, further including forming a separation layer 103 on the semiconductor surface 100, the separation layer 103 can be made For the insulating layer of protective separation All other routes, etching stop layer can also be used as, can also protect contact pad simultaneously.It is preferred that Ground, the separation layer deposit work using atom layer deposition process (Atomic Layer Deposition) or low pressure chemical vapor Skill (Low Pressure Chemical Vapor Deposition) formation, thickness are preferably between 10nm~30nm, separately Outside, in a preferred embodiment, the spacer material layer between the separation layer and the contact pad selects identical material, to protect Demonstrate,prove device stability.

Then shown in S3, as shown in figure 1 and Fig. 9~12, step 3) is carried out, the graphical sacrificial layer 102 is to form electricity Hold hole 106, wherein the capacitor hole 106 appears the contact pad 101, and the capacitor hole 106 has corrugated or sawtooth Shape side wall, it is lateral recessed toward the first material layer 102a.

Specifically, the upper surface of the structure obtained in step 2) forms photoresist as mask layer, certainly, in other examples In can also form the mask layer (such as silicon nitride hard mask layer) of other materials again using photoetching process by the exposure mask layer pattern Change, to obtain the Patterned masking layer with window, wherein the window can be along the surface of the Patterned masking layer It arranges in six square arrays, to be corresponded with about 101 contact pad, finally to prepare the capacitor hole 106, the electricity The sectional view for holding the side wall in hole can be the side wall of the rectangular saw-tooth shape in diagram, and use the finally obtained capacitor of this method The side wall in hole 106 is very smooth, is conducive to subsequent preparation process and is conducive to the raising of device performance.

As an example, in step 3), the specific steps for forming the capacitor hole include:

(do not show in figure in the Patterned masking layer for forming the window with array arrangement in the structure that step 2) obtains 3-1) Out), and based on the Patterned masking layer using the technique of dry etching the sacrificial layer 102 is etched, in the sacrificial layer Perforative through-hole 105 up and down is formed in 102, the through-hole 105 through-hole 105 corresponding and described with the window appears described and connects Pad 101 is touched, as shown in FIG. 9 and 10, the through-hole 105 and a pair above and below the window on the Patterned masking layer It answers；

3-2) use wet etching technique etch step 3-1) formed the through-hole 105 side wall, to form side wall The corrugated or jagged capacitor hole 106, as shown in FIG. 11 and 12.

Specifically, in this step, etching to form the capacitor hole 106 using two-step method, being beaten first using dry etching Open form is carrying out through-hole modification using wet etching, wherein the etching liquid of the wet etching is preferably using quality point at through-hole Count the NH between 0.15%~15%₄OH aqueous solution, the etch rate of the etching liquid, the second material layer 102b can be remote Less than the etch rate of the first material layer 102a, during corrosion, what the first material layer 102a was laterally removed Rate is much larger than the rate that laterally removes of the second material layer 102b, and available side wall is corrugated or the institute of rectangular toothed Capacitor hole 106 is stated, as shown in figure 11, the capacitor hole 106 includes that several perpendicular aperture portions (are based on second material layer 102b shape At) and several borehole enlargement portions (being formed based on first material layer 102a) for being connected with the perpendicular aperture portion.

As an example, between step 2) and step 3) further include: the surface of Yu Suoshu sacrificial layer 102 forms a protection support Layer 104, and the protection supporting layer 104 is etched based on Patterned masking layer simultaneously in step 3), as shown in Fig. 7 and Fig. 9.

Specifically, being formed after the sacrificial layer 102, one layer of protection supporting layer 104 also is formed in the sacrificial layer surface, It can be used as the protective layer in etching mask layer and etching process, and one layer can also be used as in final capacitor arrangement The supporting layer of supporting role, improves the support strength of entire capacitance structure, and the material of the protection supporting layer can choose as nitrogen SiClx layer, and the protection supporting layer formed is etched together during step 3) the graphical sacrificial layer, preferably Same mask layer is used with the etching of the sacrificial layer.

Then, as in Fig. 2 S4 and Figure 13~16 shown in, carry out step 4), fill each capacitor hole 106 and filled out with being formed Electrode 108 under hole, and under the filling perforation electrode 108 upper surface separation be emerging in the sacrificial layer 102, under the filling perforation The lower surface of electrode 108 is bonded to the corresponding contact pad 101.

Specifically, using atom layer deposition process (Atomic Layer Deposition) or chemical vapor deposition process The technique of (Chemical Vapor Deposition) or physical vapour deposition (PVD) (Physical Vapor Deposition) in Electrode 111 under filling perforation is formed in the capacitor hole 106, it is electric under the filling perforation eventually as the column lower electrode arrangement of capacitor Pole 111 includes that one or both of metal nitride and metal silicide are formed by compound, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide (Titanium Silicide), silicon titanium nitride (TiSixNy), can also be metal electrode material be conductive material such as Ru (ruthenium), Pt (platinum), Ir (iridium), the metals such as Pd (palladium), Or even metal oxide such as RuO₂(ruthenium-oxide), IrO₂(yttrium oxide) etc..Wherein it is preferred to which resistivity of material is from 1 × 10^-8(Ω M) to 1 × 10²(Ω m) range.

As an example, in step 4), the specific steps for forming electrode 108 under the filling perforation include:

102 surface of sacrificial layer deposition 4-1) in Yu Suoshu capacitor hole 106 and around the capacitor hole 106 is continuous Lower electrode material layer 107；

The lower electrode material layer 107 4-2) is planarized, and stops at the sacrificial layer 102, to divide the lower electrode Material layer forms electrode 108 under the discontiguous filling perforation between each other.

Specifically, in this step, a kind of formation process of electrode under capacitor arrangement is provided, using the technique of planarization, If lower electrode material layer 107 of the chemical mechanical milling tech to formation planarizes, thus by the lower electrode material layer of formation It separates, forms electrode 108 under discontiguous filling perforation from each other, it is preferable that the upper surface of electrode 108 and institute under the filling perforation The upper surface flush of sacrificial layer 102 is stated, further includes be formed in the sacrificial layer surface described in addition, in other examples Supporting layer 104 is protected, at this point, being planarized to the protection supporting layer 104, as shown in figure 15, the utility model is using simple Technique has obtained electrode under mutual discontiguous filling perforation, simplifies preparation process.

As an example, electrode 108 includes the first diameter portion 108a and second being alternately superimposed under the filling perforation in step 4) Diameter portion 108b, wherein the first diameter portion 108a is formed based on the first material layer 102a of the sacrificial layer, and described second Diameter portion 108b is formed based on the second material layer 102b of the sacrificial layer, and the lateral dimension D4 of the first diameter portion 108a Greater than the lateral dimension D5 of the second diameter portion 108b.

As an example, the lateral dimension of the first diameter portion 108a is between 40nm~105nm, the second diameter The lateral dimension of portion 108b is between 35nm~100nm.

Specifically, the second diameter portion 108b can not increase capacitor height as enlarged-diameter portion in this example Increase the surface area between the capacitor lower electrode and top electrode while spending, to increase capacitive energy, improves capacitor, In one preferred embodiment, the lateral dimension in the first diameter portion between the second diameter portion lateral dimension 1.08~ Between 1.18 times, 1.5~3 times with a thickness of the first diameter portion 108a thickness of the second diameter portion 108b, to have Conducive to the stability of raising capacitor arrangement, and reach the realizability of technique.Preferably, in the present embodiment, described first Total number of plies of diameter portion 108a and the second diameter portion 108b are greater than 20 layers, and ensure to have total layer in 1.3 μm of height Number is greater than 20 layers of the first diameter portion 108a and the second diameter portion 108b, in addition, the first diameter portion 108a Thickness is preferably between 5nm~15nm, and the thickness of the second diameter portion 108b is preferably between 22nm~35nm；It is described The thickness of the laminated construction part of electrode is preferably between 1.2 μm~1.4 μm under filling perforation.

Then, as in Fig. 2 S5 and Figure 20~21 shown in, carry out step 5), it is heavy in the surface for the structure that step 4) obtains One plane formula bracket supporting layer 109 of product, and the plane formula bracket supporting layer 109 covers the upper surface of electrode under the filling perforation simultaneously It is mechanically connected with the sacrificial layer 102 of surrounding them under the filling perforation.

Specifically, forming the plane formula bracket supporting layer of capacitor arrangement in the step, wherein the plane formula bracket branch Support layer 109 is formed in the top of electrode 108 under the filling perforation, is preferably only formed in the top end surface at the top of electrode under filling perforation, The supporting layer of a plane formula is constituted, the mechanical strength of device can be improved in final structure, and simplify technique, the utility model A planar plane formula bracket supporting layer 109 is formed, planar plane formula bracket supporting layer can be made any need The thickness wanted has depth-width ratio (high aspect ratio) advantage, and structure is simple, and preparation process is simple, and cost is relatively low, described Planar bracket supporting layer CVD (chemical vapor deposition, Chemical Vapor Deposition) or MLD (molecular-layer deposition, Molecular Layer Deposition) process deposits, the bottom surface of the plane formula bracket supporting layer is preferably plane, And the planar bracket supporting layer is only located at the lower electrode and fills a vacancy the top of layer, does not connect with the side wall of electrode under the filling perforation Touching, in addition, the lower surface of the plane formula bracket supporting layer 109 is upper with the protection supporting layer 104 in a preferable example Surface is in contact, so that the two coats the top of electrode 108 under the filling perforation, greatly improves the stability of capacitor. In addition, the material of the plane formula bracket supporting layer 109 includes but is not limited to silicon nitride, the material of the plane formula bracket supporting layer The material of material and the protection supporting layer 104 is preferably identical material, to further increase the stability between device architecture.

Continue, as in Fig. 2 S6 and Figure 17~27 shown in, step 6) is carried out, on Yu Suoshu plane formula bracket supporting layer 109 At least one opening 112 is formed, to open the plane formula bracket supporting layer 109, and the sacrifice is removed based on the opening Layer.

As an example, in step 6), the specific steps for opening the plane formula bracket supporting layer 109 include:

6-1) 112 surface of Yu Suoshu plane formula bracket supporting layer forms hole pattern mask layer 110, and described hole figure is covered The hole 110a of film layer 110 including several array arrangements, wherein described hole appear under the adjacent filling perforation electrode 108 it Between be located at the sacrificial layer on the plane formula bracket supporting layer 109, as shown in figure 21；

It 6-2) is based on described hole graphic mask layer 110, etches the plane formula bracket supporting layer 109, in described flat At least one described opening 112 corresponding with described hole 110a is formed on the formula bracket supporting layer of face, to open the plane Formula bracket supporting layer 109, as shown in figure 23.

Specifically, preferably the plane formula bracket supporting layer 109 is opened by dry etching in the step, to be based on beating The opening 112 opened removes the sacrificial layer 102, wherein as shown in FIG. 19 and 20, based on the formation of hole photoresist layer 111 Described hole graphic mask layer 110, described hole graphic mask layer 110 open the plane formula bracket supporting layer by being deposited on 109 mask pattern material layer 118 is formed, and is formed on described hole photoresist layer 111 and is appeared the flat of needs opening removal part The hole window 111a of face formula bracket supporting layer.In a preferred embodiment, described hole window 111a appears plane formula bracket Supporting layer 109 is located at the part under adjacent filling perforation between electrode, and electricity under its figure under extending to and the adjacent filling perforation Pole 108 does not contact, using the process transfer pattern of dry etching, so that plane formula bracket supporting layer 109 is opened, technique letter It is single.Additionally, it is preferred that carrying out the removal of subsequent sacrificial layer using wet-etching technology.

As an example, step 6-1) in, the interval in a strip shape described hole 110a (namely corresponding described hole window 111a) Arrangement, and each described hole is located between the gap that electrode 108 is constituted under four adjacent filling perforations.

Specifically, this example provides a kind of arrangement mode of hole, uniform intervals arrangement preferably in a strip shape, this is also determined The position for the opening 112 on plane formula bracket supporting layer 109 being subsequently formed, as shown in Figure 20, Figure 22 and Figure 25, described in one Hole is located between four 101 corresponding positions of contact pad, when carrying out dry etching, under four filling perforations Plane formula bracket supporting layer between electrode 108 is etched away, and then manifests sacrificial layer, and what this method was formed has opening 112 plane formula bracket supporting layer 109 has suitable aperture position, and electrode 108 under the filling perforation of guarantee section position The plane formula bracket supporting layer of upper surface is connected, can be conducive to sacrificial layer wet etching and enough supports Intensity.

Then, as in Fig. 2 S7 and Figure 28~31 shown in, carry out step 7), in the surface shape for the structure that step 6) obtains Upper electrode layer 114 is formed at capacitor dielectric layer 113, and in the surface of the capacitor dielectric layer 113.

As an example, the dielectric constant of the capacitor dielectric layer 113 is between 4~400 in step 7)；The capacitor Dielectric layer 116 is selected from strontium titanates and titanium oxide (SrTiO₃/TiO₂) constitute laminated construction, aluminium oxide and hafnium oxide (AlO/HfO) The laminated construction and compound calcium nutrition Ferroelectric that laminated construction, zirconium oxide and the aluminium oxide (ZrO/AlO/ZrO) of composition are constituted Material (consolidated by what BaTiO3 and SrTiO3 were formed by a certain percentage by BST material, the iron electrode material of composite calcium hematite structure One of solution).

As an example, the thickness D6 of the capacitor dielectric layer 113 is between 10nm~85nm, it is preferable that described in one The capacitor dielectric layer of 108 two sides of electrode (part including first diameter portion 108a and second diameter portion 108b) under filling perforation Spacing between 116 both sides is between 50nm~120nm.

As an example, the thickness D7 of the upper electrode layer 114 is between 15nm~95nm, it is preferable that filled out described in one The upper electrode layer 117 of 108 two sides of electrode (part including first diameter portion 108a and second diameter portion 108b) under hole Spacing between both sides is between 50nm~120nm.

Specifically, using atom layer deposition process (Atomic Layer Deposition) or chemical vapor deposition process The technique shape of (Chemical Vapor Deposition) or physical vapour deposition (PVD) (Physical Vapor Deposition) At the capacitor dielectric layer 116 and upper electrode layer 117, the material of the upper electrode layer 114 includes metal nitride and metal One or both of silicide is formed by compound, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide (Titanium Silicide), silicon titanium nitride (TiSixNy) can also be that metal electrode material is Conductive material such as Ru (ruthenium), Pt (platinum), Ir (iridium), the metals such as Pd (palladium) or even metal oxide such as RuO2 (ruthenium-oxide), IrO2 (yttrium oxide) etc..Wherein it is preferred to which resistivity of material is from 1 × 10^-8(Ω m) is to 1 × 10²(Ω m) range；The capacitor dielectric Layer preferably high K dielectric material, to improve the capacitance of unit-area capacitance device.

Finally, as in Fig. 2 S8 and Figure 32~35 shown in, carry out step 8), the surface of Yu Suoshu upper electrode layer 114 is formed Top electrode obturator 115, and the top electrode obturator 115 is filled in the gap between the adjacent upper electrode layer 114, and with The upper electrode layer 114 is electrically connected.

As an example, being also formed with air chamber 116, and the air chamber in the top electrode obturator 115 in step 8) 116 between the adjacent upper electrode layer 115.

As an example, after step 8) further include: 115 surface of Yu Suoshu top electrode obturator forms top electrode coating 117。

Specifically, the material of the top electrode obturator 115 includes polysilicon (poly), fill up between each columnar capacitor Gap, make stable structure and the upper electrode layer of each capacitor 114 link together；Again toward the institute of deposited metal material thereon Top electrode coating 117 is stated, the stop layer and line as subsequent connect contact layer.In a preferred embodiment, also Air chamber 116 is formed between the top electrode obturator 115 to play slow so as to the active force between releasing capacitor Punching effect, so as to discharge the strain in structural material, the structure sheafs such as metal contact layer are because of warm in avoidable manufacturing process The phenomenon that expansion squeezes and makes capacitor, and especially lower electrode layer deforms is conducive to the stability for improving device, wherein described The formation of air chamber 116 can control the depositing operation of the top electrode obturator, such as control deposition doping, the deposition of polysilicon Temperature and the pressure of substrate etc. control the formation of the air chamber.

As shown in Figure 32~35, the utility model also provides a kind of columnar capacitor array structure, wherein the column electricity Vessel array structure preferably uses the preparation method of the columnar capacitor array structure of the utility model to prepare comprising:

Semiconductor substrate 100, the semiconductor substrate 100 include that several are located at the contact pad in memory array structure 101；

Electrode 108 under filling perforation are incorporated on the contact pad 101, and the side wall of electrode 108 is corrugated under the filling perforation Or zigzag；

Plane formula bracket supporting layer 109 is covered in the upper surface of electrode 108 under each filling perforation；

Capacitor dielectric layer 113 is formed under the filling perforation under the side wall of electrode 108 and the filling perforation around electrode 108 The semiconductor substrate 100 on；

Upper electrode layer 114 is formed in 113 surface of capacitor dielectric layer；And

Top electrode obturator 115, between the top electrode obturator 115 is filled between the adjacent upper electrode layer 114 Gap, and be electrically connected with the upper electrode layer 114.

Specifically, the plane formula bracket supporting layer 109 is formed in the top of electrode 108 under the filling perforation, preferably shape At the top end surface at the top of electrode under filling perforation, the supporting layer of a plane formula is constituted, device can be improved in final structure Mechanical strength, and simplify technique, the utility model formed a planar plane formula bracket supporting layer 109, it is planar Plane formula bracket supporting layer can be made the thickness of any needs, structure is simple, and preparation process is simple, and cost is relatively low, institute The bottom surface for stating plane formula bracket supporting layer is preferably plane, and the planar bracket supporting layer is only located at the lower electrode and fills out The top of dead level is not contacted with the side wall of electrode under the filling perforation, in addition, in a preferable example, the plane formula bracket branch The lower surface for supportting layer 109 is in contact with the upper surface for protecting supporting layer 104, so that the two is by electrode 108 under the filling perforation Top cladding, greatly improve the stability of capacitor.In addition, the material of the plane formula bracket supporting layer 109 includes But it is not limited to silicon nitride, the material of the plane formula bracket supporting layer and the material of the protection supporting layer 104 are preferably same Material, to further increase the stability between device architecture.

As an example, the columnar capacitor array structure further includes protection supporting layer 104, the protection supporting layer 104 Be placed on electrode 108 under the filling perforation upper surface periphery, and it is described protection supporting layer 104 upper surface be located at the plane The lower surface of formula bracket supporting layer 109 is in contact.

Specifically, the columnar capacitor array structure further include protection supporting layer 104 its can be used as etching mask layer And the protective layer in etching process, the supporting layer of one layer of supporting role can also be formed in final capacitor arrangement, mentioned The material of the support strength of high entire capacitance structure, the protection supporting layer can choose as silicon nitride layer.

As an example, being also formed with a separation layer 103 between the semiconductor substrate 100 and the capacitor dielectric layer 113.

As an example, the thickness of the separation layer 103 is between 5nm~45nm；The separation layer 103 includes silicon nitride Layer.

Specifically, further including forming a separation layer 103 on the semiconductor surface 100, the separation layer 103 can be made For the insulating layer of protective separation All other routes, etching stop layer can also be used as, can also protect contact pad simultaneously, thickness is excellent Selected introductions are between 10nm~30nm, in addition, in a preferred embodiment, being isolated between the separation layer and the contact pad Material layer selects identical material, to guarantee device stability.

As an example, electrode 108 includes the first diameter portion 108a being alternately superimposed on and second diameter portion under the filling perforation 108b, wherein the lateral dimension of the first diameter portion 108a is greater than the lateral dimension of the second diameter portion 108b.

Specifically, the second diameter portion 108b can not increase capacitor height as enlarged-diameter portion in this example Increase the surface area between the capacitor lower electrode and top electrode while spending, to increase capacitive energy, improves capacitor, In one preferred embodiment, 1.5~3 times with a thickness of the first diameter portion 108a thickness of the second diameter portion 108b, from And be conducive to improve the stability of capacitor arrangement, and reach the realizability of technique.

As an example, the columnar capacitor array structure further includes top electrode coating 117, the top electrode coating 117 are formed in the surface of the top electrode obturator 115.

As an example, being also formed with air chamber 106 in the top electrode obturator 115, and the air chamber 106 is located at phase Between the adjacent upper electrode layer 114.

Specifically, the dielectric constant of the capacitor dielectric layer 113 is between 4~400；The capacitor dielectric layer 113 selects From strontium titanates and titanium oxide (SrTiO₃/TiO₂) lamination that constitutes of the laminated construction, aluminium oxide and the hafnium oxide (AlO/HfO) that constitute The laminated construction and compound calcium nutrition Ferroelectric material (BST material that structure, zirconium oxide and aluminium oxide (ZrO/AlO/ZrO) are constituted Material, the iron electrode material of composite calcium hematite structure is by BaTiO₃And SrTiO₃The solid solution formed by a certain percentage) in one Kind.As an example, the thickness D6 of the capacitor dielectric layer 113 is between 10nm~85nm, it is preferable that under a filling perforation Spacing between the both sides of the capacitor dielectric layer 116 of electrode two sides (part including first diameter portion and second diameter portion) Between 50nm~120nm.

As an example, the thickness D7 of the upper electrode layer 114 is between 15nm~95nm, it is preferable that filled out described in one Under hole between the both sides of the upper electrode layer 114 of 108 two sides of electrode (part including first diameter portion and second diameter portion) Spacing between 50nm~120nm.

Specifically, the material of the upper electrode layer 114 includes one or both of metal nitride and metal silicide It is formed by compound, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide (Titanium Silicide), silicon titanium nitride (TiSixNy) can also be that metal electrode material is conductive material such as Ru (ruthenium), Pt (platinum), Ir (iridium), the metals such as Pd (palladium) or even metal oxide such as RuO2 (ruthenium-oxide), IrO₂(yttrium oxide) etc..Wherein, Preferably, resistivity of material is from 1 × 10^-8(Ω m) is to 1 × 10²(Ω m) range；The preferred high K dielectric material of capacitor dielectric layer Material, to improve the capacitance of unit-area capacitance device.

In addition, the material of the top electrode obturator 115 includes polysilicon (poly), fill up between each columnar capacitor Gap makes stable structure and the upper electrode layer of each capacitor 114 links together；Again toward the described of deposited metal material thereon Top electrode coating 117, stop layer and line as subsequent connect contact layer.In a preferred embodiment, also exist Air chamber 116 is formed between the top electrode obturator 115 plays buffering so as to the active force between releasing capacitor Effect, so as to discharge the strain in structural material, the structure sheafs such as metal contact layer are because hot swollen in avoidable manufacturing process It is swollen extruding and make capacitor, especially lower electrode layer deform the phenomenon that, be conducive to improve device stability, wherein the sky The formation of air cavity 116 can control the depositing operation of the top electrode obturator, such as control deposition doping, the deposition temperature of polysilicon The formation of the control such as pressure of the degree and substrate air chamber.

In addition, the utility model also provides a kind of organization of semiconductor memory, the organization of semiconductor memory includes such as The specific structure of columnar capacitor array structure as described in the examples, the array of capacitors structure please refers to above-mentioned implementation Example, is not repeated herein.As an example, the organization of semiconductor memory can be but be not limited only to dynamic RAM (DRAM)。

In conclusion the utility model provides a kind of columnar capacitor array structure, comprising: semiconductor substrate, described half Conductor substrate includes the contact pad that several are located in memory array structure；Electrode under filling perforation is incorporated into the contact pad On, the side wall of electrode is corrugated under the filling perforation or zigzag；Plane formula bracket supporting layer, and the plane formula bracket supports Layer covers the upper surface of electrode under each filling perforation；Capacitor dielectric layer is formed under the filling perforation side wall of electrode and described Under filling perforation in the semiconductor substrate of surrounding them；Upper electrode layer is formed in the capacitor dielectric layer surface；And top electrode Obturator, the top electrode obturator are filled in the gap between the adjacent upper electrode layer and are electrically connected with the upper electrode layer It connects.Through the above scheme, the utility model provides a kind of columnar capacitor array structure and preparation method, passes through the utility model Structure capacitor size can be further reduced, there is biggish remaining space, size has more preferable between adjacent capacitor Contractility can be in the feelings for not increasing capacitor height by forming electrode under side wall is corrugated or jagged column Increase the surface area of capacitor under condition, to improve capacitive energy, adaptation size is miniature, in addition, the utility model forms filling perforation The plane formula bracket supporting layer of lower top of electrodes, can prepare the supporting layer for needing thickness, have depth-width ratio (high aspect Ratio) advantage improves support strength, and simplifies preparation process and structure.So the utility model effectively overcomes now There is the various shortcoming in technology and has high industrial utilization value.

The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.

Claims

1. a kind of columnar capacitor array structure characterized by comprising

Plane formula bracket supporting layer, and the plane formula bracket supporting layer covers the upper surface of electrode under each filling perforation；

Capacitor dielectric layer is formed in the semiconductor lining of surrounding them under the side wall of electrode under the filling perforation and the filling perforation On bottom；

Upper electrode layer is formed in the capacitor dielectric layer surface；And

Top electrode obturator, the top electrode obturator are filled in the gap between the adjacent upper electrode layer and power on described Pole layer electrical connection.

2. columnar capacitor array structure according to claim 1, which is characterized in that the columnar capacitor array structure It further include protection supporting layer, the protection supporting layer is placed on the upper surface periphery of electrode under the filling perforation, and protection branch The upper surface of support layer is in contact with the lower surface of the plane formula bracket supporting layer.

3. columnar capacitor array structure according to claim 1, which is characterized in that the semiconductor substrate and the electricity Hold and is also formed with a separation layer between dielectric layer.

4. columnar capacitor array structure according to claim 1, which is characterized in that electrode includes alternating under the filling perforation Stacked first diameter portion and second diameter portion, wherein the lateral dimension in the first diameter portion is greater than the second diameter portion Lateral dimension.

5. columnar capacitor array structure according to claim 4, which is characterized in that the lateral ruler in the first diameter portion It is very little between 40nm~105nm, the lateral dimension of the second diameter portion is between 35nm~100nm；Described first is straight The thickness in diameter portion is between 3nm~30nm, and the thickness of the second diameter portion is between 20nm~50nm.

6. columnar capacitor array structure according to claim 4, which is characterized in that the lateral ruler in the first diameter portion Between 1.08~1.18 times of the very little lateral dimension between the second diameter portion；The thickness of the second diameter portion is between described Between 1.5~3 times of first diameter portion thickness.

7. columnar capacitor array structure according to claim 1, which is characterized in that the columnar capacitor array structure It further include top electrode coating, the top electrode coating is formed in the surface of the top electrode obturator.

8. columnar capacitor array structure according to claim 1, which is characterized in that the dielectric of the capacitor dielectric layer is normal Number is between 4~400；Laminated construction, aluminium oxide and the oxidation that the capacitor dielectric layer choosing is constituted from strontium titanates and titanium oxide One in laminated construction and compound calcium nutrition Ferroelectric material that laminated construction, zirconium oxide and the aluminium oxide that hafnium is constituted are constituted Kind；The thickness of the capacitor dielectric layer is between 10nm~85nm；The thickness of the upper electrode layer between 15nm~95nm it Between.

9. columnar capacitor array structure described according to claim 1~any one of 8, which is characterized in that described to power on Air chamber is also formed in the obturator of pole, and the air chamber is between the adjacent upper electrode layer.

10. a kind of organization of semiconductor memory, which is characterized in that the organization of semiconductor memory includes such as claim 1 institute The columnar capacitor array structure stated.