CN208189581U - A kind of column capacitance structure - Google Patents
A kind of column capacitance structure Download PDFInfo
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- CN208189581U CN208189581U CN201820677169.4U CN201820677169U CN208189581U CN 208189581 U CN208189581 U CN 208189581U CN 201820677169 U CN201820677169 U CN 201820677169U CN 208189581 U CN208189581 U CN 208189581U
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Abstract
The utility model provides a kind of column capacitance structure, the column capacitance structure include substrate, multiple engagement pads of discrete setting, discrete setting multiple capacitor lower electrode plates, capacitance dielectric layer, capacitor electric pole plate, wherein, capacitor lower electrode plate includes a columnar body, and can further comprise at least one layer of annular shoulder for being connected to columnar body side wall, to constitute umbrella column capacitor lower electrode plate.Capacitance structure provided by the utility model is simple, can save the processing step of some complexity, such as is not required to increase additional processing procedure and will be separated from each other between capacitor lower electrode plate, so as to reduce technology difficulty, saves manufacturing cost.Capacitor bottom crown can form rough surface, and effective area is increased, thus can improve the storage charge capability of capacitor.
Description
Technical field
The utility model belongs to semiconductor integrated circuit field, is related to a kind of column capacitance structure.
Background technique
Capacitor is a kind of passive electronic components with electrostatic format of field storage energy.In simplest form, capacitor
It is isolated including two conductive plates, and between two conductive plates by being referred to as dielectric insulating materials.The capacitor of capacitor
It is directly proportional to the surface area of pole plate, between pole plate at a distance from be inversely proportional.The capacitor of capacitor additionally depends on the object of separation pole plate
The dielectric constant of matter.
The standard unit of capacitor is method (farad, referred to as F), this is a big unit, and more common unit is microfarad
(microfarad, abbreviation μ F) and pico farad (picofarac, abbreviation PF), wherein 1 μ F=10-6F, 1pF=10-12F。
Capacitor can be manufactured on integrated circuit (IC) chip.In dynamic random access memory (dynamic
Random access memory, abbreviation DRAM) in, capacitor is commonly used in connecting with transistor.Capacitor, which helps to maintain, to be deposited
The content of reservoir.Due to its small physical size, these components have low capacitor.They must be with thousands of frequencies per second
It recharges, otherwise, DRAM will lose data.
Existing DRAM storage array area's capacitor production the following steps are included:
(1) argyle design is formed in two directions in pitch-multiplied (Pitch doubling) method in array region,
Diamond shape can gradually become circular pattern in etch transfer patterning process, become cylindrical deep hole；
(2) bottom and deposited on sidewalls lower electrode material in deep hole, then using every three deep holes as basic unit, wherein
Square aperture separates the lower electrode of connection in the heart, forms the rack for test tube structure with silicon nitride (SiN) for supporting layer；
(3) high-k dielectric material and upper electrode material are deposited in deep hole.
With the reduction of technology node, this capacitor production program is difficult to realize in technique.The research of industry needs
Simplify structure to be applied to 17nm process node and hereinafter, so column (pillar) capacitor is made as future thrust.
The disadvantage of column capacitor is that electrode plate suqare is lower, is needed its structural improvement to increase its capacitance.It is existing
The shortcomings that making the technical method of capacitor is that the diminution of capacitor size can bring technical difficult and its storage charge capability
Reduction.The capacitor lower electrode plate of capacitor links together in the technical method of existing production capacitor, needs to increase by one of light
Scribing Cheng Kaikong and etch process will be separated from each other between capacitor lower electrode plate, form the supporting layer using SiN layer as capacitor
Structure.
Therefore, how a kind of new column capacitance structure is provided, to reduce capacitor size, while obtaining biggish charge and depositing
Energy storage power, and technology difficulty is reduced, become those skilled in the art's important technological problems urgently to be resolved.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of column capacitance structure,
Diminution for solving capacitor size in the prior art can bring technical difficult and storage charge capability reduction ask
Topic.
In order to achieve the above objects and other related objects, the utility model provides a kind of column capacitance structure, the column
Capacitance structure includes:
Substrate；
Multiple engagement pads of discrete setting, array arrangement is in the substrate；
Multiple capacitor lower electrode plates of discrete setting, the capacitor lower electrode plate include a columnar body, and each described
Columnar body is connect with an engagement pad respectively；
Capacitance dielectric layer is coated on multiple capacitor lower electrode plate surfaces；
Capacitor electric pole plate is coated on the capacitive dielectric layer surface.
Optionally, the width range of the columnar body is 35~100nm.
Optionally, the floor space of the columnar body is greater than the top area of the engagement pad.
Optionally, the resistivity of material range of the capacitor lower electrode plate and the capacitor electric pole plate is 1 × 10-8Ωm
To 1 × 102The material dielectric constant range of Ω m, the capacitance dielectric layer are 4~400.
Optionally, the column capacitance structure further includes capacitor electric pole plate articulamentum, the capacitor top electrode articulamentum
It is coated on capacitor electric pole plate surface, and fills the gap between the adjacent capacitor lower electrode plate.
Optionally, the column capacitance structure further includes line contact layer, and the line contact layer is formed in the capacitor
On electric pole plate articulamentum.
Optionally, the column capacitance structure further includes isolated insulation layer, and the isolated insulation layer is coated on the substrate
Surface, and there is the opening for exposing the engagement pad, the bottom of the columnar body in position corresponding with the engagement pad
Portion is located in the opening, and connect with the engagement pad.
The utility model also provides another column capacitance structure, and the column capacitance structure includes:
Substrate；
Multiple engagement pads of discrete setting, array arrangement is in the substrate；
Multiple capacitor lower electrode plates of discrete setting, the capacitor lower electrode plate is including a columnar body and is connected to institute
State the multi-layer annular flank of columnar body side wall, the discrete setting of each layer annular shoulder, each columnar body respectively with
One engagement pad connection；
Capacitance dielectric layer is coated on multiple capacitor lower electrode plate surfaces；
Capacitor electric pole plate is coated on the capacitive dielectric layer surface.
Optionally, the thickness of the annular shoulder is less than the spacing of the adjacent annular shoulder, the adjacent annular shoulder
Spacing range be 20~500nm.
Optionally, the width range of the columnar body is 35~100nm, the thickness range of the annular shoulder is 3~
30nm, width range are 40~105nm.
Optionally, the floor space of the columnar body is greater than the top area of the engagement pad.
Optionally, the resistivity of material range of the capacitor lower electrode plate and the capacitor electric pole plate is 1 × 10-8Ωm
To 1 × 102The material dielectric constant range of Ω m, the capacitance dielectric layer are 4~400.
Optionally, the column capacitance structure further includes capacitor electric pole plate articulamentum, the capacitor top electrode articulamentum
It is coated on capacitor electric pole plate surface, and fills the gap between the adjacent capacitor lower electrode plate.
Optionally, the column capacitance structure further includes line contact layer, and the line contact layer is formed in the capacitor
On electric pole plate articulamentum.
Optionally, the column capacitance structure further includes isolated insulation layer, and the isolated insulation layer is coated on the substrate
Surface, and there is the opening for exposing the engagement pad, the bottom of the columnar body in position corresponding with the engagement pad
Portion is located in the opening, and connect with the engagement pad.
As described above, the column capacitance structure of the utility model, has the advantages that electricity provided by the utility model
It is simple to hold structure, the processing step of some complexity can be saved, such as being not required to increase additional processing procedure will be between capacitor lower electrode plate
It is separated from each other, so as to reduce technology difficulty, saves manufacturing cost, be suitable for technique more lower than prior art node, example
Such as 17nm or even its technology node below.Capacitor bottom crown can form rough surface, and effective area is increased,
The storage charge capability of capacitor can thus be improved.
Detailed description of the invention
Fig. 1 is shown as the top plan view of the substrate provided in embodiment two.
Fig. 2 is shown as in Fig. 1 the vertical cross-section diagram in region shown in four-headed arrow.
Fig. 3 is shown as forming the plane vertical view that an isolated insulation layer is presented after the substrate surface in embodiment two
Figure.
Fig. 4 is shown as in Fig. 3 the vertical cross-section diagram in region shown in four-headed arrow.
Fig. 5 is shown as being formed a hard mask layer in embodiment two in the isolated insulation layer surface, and is formed multiple discrete
The through-hole of setting in the hard mask layer after the top plan view that is presented.
Fig. 6 is shown as in Fig. 5 the vertical cross-section diagram in region shown in four-headed arrow.
Fig. 7 is shown as in embodiment two filling full capacitor lower electrode material in the through hole, and removes the hard exposure mask
The top plan view presented after extra capacitor lower electrode material on layer.
Fig. 8 is shown as in Fig. 7 the vertical cross-section diagram in region shown in four-headed arrow.
What Fig. 9 was shown as being presented after removing the hard mask layer around the capacitor lower electrode plate in embodiment two
Top plan view.
Figure 10 is shown as in Fig. 9 the vertical cross-section diagram in region shown in four-headed arrow.
Figure 11 is shown as forming capacitance dielectric layer institute after multiple capacitor lower electrode plate surfaces in embodiment two
The top plan view of presentation.
Figure 12 is shown as in Figure 11 the vertical cross-section diagram in region shown in four-headed arrow.
Figure 13 is shown as forming a capacitor electric pole plate in embodiment two to be presented after the capacitor dielectric layer surface
Top plan view.
Figure 14 is shown as in Figure 13 the vertical cross-section diagram in region shown in four-headed arrow.
Figure 15 is shown as being formed capacitor electric pole plate articulamentum in embodiment two after capacitor electric pole plate surface
The top plan view presented.
Figure 16 is shown as in Figure 15 the vertical cross-section diagram in region shown in four-headed arrow.
Institute after Figure 17 is shown as being formed line contact layer in embodiment two on the capacitor electric pole plate articulamentum
The top plan view of presentation.
Figure 18 is shown as in Figure 17 the vertical cross-section diagram in region shown in four-headed arrow.
Figure 19 is shown as the vertical cross-section diagram of the single capacitor formed in embodiment two.
Figure 20 is shown as in Figure 19 the horizontal sectional view in region shown in four-headed arrow.
Figure 21 is shown as being formed a hard mask layer in example IV in the schematic diagram of the isolated insulation layer surface.
Figure 22 is shown as forming schematic diagram of the through-hole of multiple discrete settings in the hard mask layer in example IV.
Figure 23 is shown as progress wet etching in example IV and obtains the schematic diagram of rough through-hole side wall.
Figure 24 is shown as in example IV filling full capacitor lower electrode material in the through hole, and removes the hard exposure mask
The schematic diagram of extra capacitor lower electrode material on layer.
Figure 25 is shown as removing the schematic diagram of the hard mask layer around the capacitor lower electrode plate in example IV.
Figure 26 is shown as being formed a capacitance dielectric layer in example IV in the signal of multiple capacitor lower electrode plate surfaces
Figure.
Figure 27 is shown as example IV and forms a capacitor electric pole plate in the schematic diagram of the capacitor dielectric layer surface.
Figure 28 is shown as forming capacitor electric pole plate articulamentum showing on capacitor electric pole plate surface in example IV
It is intended to.
Figure 29 is shown as forming signal of the line contact layer on the capacitor electric pole plate articulamentum in example IV
Figure.
Figure 30 is shown as the vertical cross-section diagram of the single capacitor of example IV formation.
Figure 31 is shown as the horizontal sectional view in region shown in the four-headed arrow of outer ring in Figure 30.
Figure 32 is shown as the horizontal sectional view in region shown in inner ring four-headed arrow in Figure 30.
Component label instructions
101 substrates
102 engagement pads
103 capacitor bottom crowns
104 high k capacitance dielectric layers
105 capacitor top crowns
106 SiN supporting layers
107 polysilicon articulamentums 107
108 line contact layers
201 substrates
202 engagement pads
203 isolated insulation layers
204 hard mask layers
2041 first film layers
2042 second film layers
205 through-holes
206 capacitor lower electrode plates
2061 columnar bodies
2062 annular shoulders
207 capacitance dielectric layers
208 capacitor electric pole plates
209 capacitor electric pole plate articulamentums
210 line contact layers
The thickness of T annular shoulder
The spacing of D adjacent annular flank
WinThe width of columnar body
WoutThe width of annular shoulder
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1 to Fig.3 2.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model is only shown with related component in the utility model rather than when according to actual implementation in schema then
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
Embodiment one
The utility model provides a kind of column capacitance structure, please refers to Figure 18, is shown as the section of the column capacitance structure
Figure, including substrate 201, multiple engagement pads 202 of discrete setting, discrete setting multiple capacitor lower electrode plates 206, capacitive dielectric
Layer 207 and capacitor electric pole plate 208, wherein multiple 202 array arrangements of engagement pad are in the substrate 201, the capacitor
Lower electrode plate 206 includes a columnar body, and each columnar body is connect with an engagement pad 202 respectively, the electricity
Hold dielectric layer 207 and be coated on multiple 206 surfaces of capacitor lower electrode plate, the capacitor electric pole plate 208 is coated on the electricity
Hold 207 surface of dielectric layer.
As an example, the width range of the columnar body is 35~100nm.It should be pointed out that according to the column
The difference of main body horizontal cross sectional geometry, the width may have different definition, if such as columnar body horizontal cross-section shape
Shape is circle, then width refers to diameter herein, if the columnar body horizontal cross sectional geometry is square, width refers to herein
Side length.
Specifically, column is still presented together with the capacitance dielectric layer 207 for being coated on its surface in the capacitor lower electrode plate 206
Shape structure, that is to say, that the capacitor lower electrode plate 206 is not filled by the gap between the adjacent capacitor lower electrode plate 206 of full phase.
As an example, the column knot that the capacitor lower electrode plate 206 is presented together with the capacitance dielectric layer 207 for being coated on its surface
The width range of structure is 45~120nm.
Specifically, the capacitor lower electrode plate 206 is together with the capacitance dielectric layer 207 for being coated on its surface and is coated
Column structure is still presented in the structure that capacitor electric pole plate 208 in 207 surface of capacitance dielectric layer collectively constitutes, that is to say, that
The capacitor electric pole plate 208 is not filled by the gap between the adjacent capacitor lower electrode plate 206 of full phase.As an example, the electricity
Electrode plate 206 is held together with the capacitance dielectric layer 207 for being coated on its surface and is coated on 207 table of capacitance dielectric layer
The width range of the presented column structure of capacitor electric pole plate 208 in face is 50~130nm.
Specifically, the floor space of the columnar body can be greater than the top area of the engagement pad 202, to increase column capacitor
The effective area of lower electrode plate increases the storage charge capability of capacitor with this.
Specifically, the resistivity of material range of the capacitor lower electrode plate 206 and the capacitor electric pole plate 208 is 1
×10-8Ω m to 1 × 102Ωm.As an example, used by the capacitor lower electrode plate 206 and the capacitor electric pole plate 208
Conductive material may include the metals such as Ru (ruthenium), Pt (platinum), Ir (iridium), Pd (palladium) or even metal oxide such as RuO2(oxidation
Ruthenium), IrO2(yttrium oxide) etc. or nitride such as TiN (titanium nitride) etc..
Specifically, the capacitance dielectric layer 207 uses high k (relative dielectric constant) medium, material dielectric constant range is 4
~400.As an example, high K medium material used by the capacitance dielectric layer 207 may include SrTiO3/TiO2Composite layer,
AH(Al2O3/HfO2) composite layer, ZAZ (ZrO2/Al2O3/ZrO2) composite layer, the BST material (iron electrode of composite calcium hematite structure
Material is by BaTiO3And SrTiO3The solid solution formed by a certain percentage) etc..
Specifically, the column capacitance structure further includes capacitor electric pole plate articulamentum 209, the capacitor top electrode connection
Layer 209 is coated on 208 surface of capacitor electric pole plate, and fills the gap between the adjacent capacitor lower electrode plate 206.Institute
The filling for stating capacitor electric pole plate articulamentum 209 can make stable structure, and the electric pole plate of each capacitor is linked together.Make
For example, the material of the capacitor electric pole plate articulamentum 209 includes the polysilicon of doping.
Specifically, the column capacitance structure further includes line contact layer 210, the line contact layer 210 is formed in institute
It states on capacitor electric pole plate articulamentum 209.The line contact layer 210 is alternatively arranged as subsequent erosion in addition to contacting for line
Carve the stop layer of step.As an example, the line contact layer 210 uses conductive metallic material.
Specifically, the column capacitance structure further includes isolated insulation layer 203, the isolated insulation layer 203 is coated on institute
201 surface of substrate is stated, and there is the opening for exposing the engagement pad 202, institute in position corresponding with the engagement pad 202
The bottom for stating columnar body is located in the opening, and connect with the engagement pad 202.The isolated insulation layer 203 as every
Insulating layer from other routes.As an example, the material of the isolated insulation layer 203 includes SiN.
Figure 19 is please referred to, the vertical cross-section diagram of single capacitor in the column capacitance structure of the utility model, Figure 20 are shown as
The horizontal sectional view in region shown in four-headed arrow is shown as in Figure 19.In the present embodiment, the column of the capacitor lower electrode plate 206
The horizontal cross-section of main body is circle, that is to say, that the columnar body is cylinder, in other embodiments, electric under the capacitor
The horizontal cross-section of the columnar body of pole plate 206 is also possible to other shapes, such as ellipse, polygon, should not excessively limit herein
The protection scope of the utility model processed.
Since the capacitor lower electrode plate 206 of the column capacitance structure of the utility model uses column structure, there is structure letter
Single feature has biggish remaining space between each capacitor, and size has better contractility.
Embodiment two
A kind of method making column capacitance structure in embodiment one is provided in the present embodiment, comprising the following steps:
As shown in Figures 1 and 2, it executes step S101: a substrate 201 being provided, multiple arrays is equipped in the substrate 201 and arranges
The engagement pad 202 of cloth.Wherein, Fig. 1 is shown as the top plan view of the substrate.Fig. 2 is shown as in Fig. 1 area shown in four-headed arrow
The vertical cross-section diagram in domain.
In the present embodiment, multiple engagement pads 202 are arranged in the substrate 201 in six square arrays, in other embodiments,
Multiple engagement pads 202 can also use other array arrangement modes, should not excessively limit the protection scope of the utility model herein.
It should be pointed out that Fig. 1 and Fig. 2 show the array region of initial structure, can have around the array region
Peripheral circuit area, and peripheral circuit area can well in advance starting metal layer (M0).
As shown in Figures 3 and 4, it executes step S102: forming an isolated insulation layer 203 on 201 surface of substrate.Its
In, Fig. 3 is shown as formed as top plan view that the isolated insulation layer 203 is presented after 201 surface of substrate (in figure
It has been shown in broken lines the position of the engagement pad), Fig. 4 is shown as in Fig. 3 the vertical cross-section diagram in region shown in four-headed arrow.
As an example, depositing one layer of nitridation using atom deposition method (Atomic Layer Deposition, abbreviation ALD)
Silicon (SiN) is used as the isolated insulation layer 203, for other routes to be isolated.The thickness range of the isolated insulation layer 203 is 5
~45nm.
As shown in Figures 5 and 6, it first carries out step S103: forming a hard mask layer 204 in 203 table of isolated insulation layer
Face；Step S104 is executed again: forming the through-hole 205 of multiple discrete settings in the hard mask layer 204, each through-hole
205 position is corresponding with the position of an engagement pad 202 respectively, and the through-hole 205 extends downward into the isolation
To expose 202 upper surface of engagement pad in insulating layer 203.Wherein, Fig. 5 is shown as formed as the hard mask layer 204 in institute
203 surface of isolated insulation layer is stated, and the through-hole 205 for forming multiple discrete settings is presented later in the hard mask layer 204
Top plan view, Fig. 6 is shown as in Fig. 5 the vertical cross-section diagram in region shown in four-headed arrow.
As an example, the material of the hard mask layer 204 is selected from silica, silicon nitride, silicon carbide, silicon oxynitride, carbon nitrogen
The one of which of SiClx, carbon silicon oxynitride and the constituted group of boron nitride.The thickness range of the hard mask layer 204 is 1000
~2500nm.Using plasma dry ecthing method, and be etch stop layer with the engagement pad 202, etching obtains the through-hole
205 in the hard mask layer 204.
As shown in Figures 7 and 8, it executes step S105: filling full capacitor lower electrode material in the through-hole 205, and go
Except capacitor lower electrode material extra on the hard mask layer 204, the capacitor lower electrode plate 206 of multiple discrete settings is obtained.
Wherein, Fig. 7 is shown as filling full capacitor lower electrode material in the through-hole 205, and removes more on the hard mask layer 204
The top plan view presented after remaining capacitor lower electrode material, Fig. 8 are shown as in Fig. 7 the vertical of region shown in four-headed arrow
Sectional view.
Specifically, using atom deposition method (Atomic Layer Deposition, abbreviation ALD), chemical vapour deposition technique
(Chemical Vapor Deposition, abbreviation CVD) or physical vaporous deposition (Physical Vapor
Deposition) deposited capacitances lower electrode material.
As shown in FIG. 9 and 10, it executes step S106: removing the hard exposure mask around the capacitor lower electrode plate 206
Layer 204.Wherein, Fig. 9 is shown as being presented after removing the hard mask layer 204 around the capacitor lower electrode plate 206
Top plan view, Figure 10 are shown as in Fig. 9 the vertical cross-section diagram in region shown in four-headed arrow.As it can be seen that the capacitor lower electrode plate
206 are presented column.
It is done as an example, being removed the hard mask layer 204 around the capacitor lower electrode plate 206 with wet etching
Only.
Further, after removing the hard mask layer around the capacitor lower electrode plate, following steps are further included:
As shown in FIG. 11 and 12, it executes step S107: forming a capacitance dielectric layer 207 in multiple capacitor lower electrodes
206 surface of plate, wherein Figure 11 be shown as formed as the capacitance dielectric layer 207 multiple 206 surfaces of capacitor lower electrode plate it
The top plan view presented afterwards, Figure 12 are shown as in Figure 11 the vertical cross-section diagram in region shown in four-headed arrow.
As an example, depositing the capacitor using atom deposition method (Atomic Layer Deposition, abbreviation ALD)
Dielectric layer 207.
As shown in FIG. 13 and 14, it executes step S108: forming a capacitor electric pole plate 208 in the capacitor dielectric layer
207 surfaces, wherein Figure 13 is shown as formed as the capacitor electric pole plate 208 and is in after 207 surface of capacitor dielectric layer
Existing top plan view, Figure 14 are shown as in Figure 13 the vertical cross-section diagram in region shown in four-headed arrow.
As an example, forming the capacitor using atom deposition method (Atomic Layer Deposition, abbreviation ALD)
Electric pole plate 208.
As shown in Figure 15 and Figure 16, step S109 is executed: forming capacitor electric pole plate articulamentum 209 and power in the capacitor
208 surface of pole plate, the capacitor electric pole plate articulamentum 209 fill the gap between the adjacent capacitor lower electrode plate 206,
In, Figure 15 is shown as formed as the capacitor electric pole plate articulamentum 209 and is presented after 208 surface of capacitor electric pole plate
Top plan view, Figure 16 is shown as in Figure 15 the vertical cross-section diagram in region shown in four-headed arrow.
As an example, the polysilicon of deposition doping, fills up the gap between each columnar capacitor, makes stable structure and will be each
The electric pole plate of capacitor links together.
As shown in FIG. 17 and 18, it executes step S110: forming line contact layer 210 and connected in the capacitor electric pole plate
On layer 209, wherein Figure 17 is shown as formed as the line contact layer 210 on the capacitor electric pole plate articulamentum 209
The top plan view presented later, Figure 18 are shown as in Figure 17 the vertical cross-section diagram in region shown in four-headed arrow.
As an example, the stop layer and line contact layer of deposited metal material subsequent.
So far, production obtains column capacitance structure.After the production method of the present embodiment forms through-hole in hard mask layer, directly
It is access to and wherein fills up capacitor lower electrode material, and toward being etched back at the top of hard mask layer, then by capacitor lower electrode surrounding materials
Hard mask layer remove, form the column capacitor lower electrode plate being isolated from each other, then can Direct precipitation capacitor dielectric material and
Upper electrode material forms complete capacitance structure.The production method of the present embodiment is suitable for work more lower than prior art node
Skill, such as 17nm or even its technology node below.Since capacitance structure is simple, the processing step of some complexity, example can be saved
Such as being not required to increase additional processing procedure will be separated from each other between capacitor lower electrode plate, so as to reduce technology difficulty, save manufacture
Cost.
Embodiment three
The present embodiment and embodiment one are the difference is that capacitor lower electrode plate has bigger surface area.Please refer to figure
29, be shown as the sectional view of the column capacitance structure of the present embodiment, including substrate 201, multiple engagement pads 202 of discrete setting,
Multiple capacitor lower electrode plates 206, capacitance dielectric layer 207 and the capacitor electric pole plate 208 of discrete setting, wherein connect described in multiple
In the substrate 201, the capacitor lower electrode plate 206 includes a columnar body 2061 and is connected to 202 array arrangement of touch pad
The multi-layer annular flank 2062 of 2061 side wall of columnar body, the discrete setting of each layer annular shoulder 2062 are each described
Columnar body 2061 is connect with an engagement pad 202 respectively, and the capacitance dielectric layer 207 is coated under multiple capacitors
206 surface of electrode plate, the capacitor electric pole plate 208 are coated on 207 surface of capacitance dielectric layer.
Specifically, the thickness of the annular shoulder 2062 is less than the spacing of the adjacent annular shoulder, as an example, as schemed
Shown in 25, the thickness T range of annular shoulder is 3~30nm, and the space D range of adjacent annular flank is 20~500nm, column master
The width W of bodyinRange is 35~100nm, the width W of annular shoulderoutRange is 40~105nm.By the capacitance dielectric layer
207 thickness effect, the capacitor lower electrode plate 206 are constituted together with the capacitance dielectric layer 207 for being coated on its surface
The width range of column structure is 50~120nm (including outer ring and inner ring), by the thickness shadow of the capacitor electric pole plate 208
It rings, the capacitor lower electrode plate 206 is together with the capacitance dielectric layer 207 for being coated on its surface and is coated on capacitor Jie
The width range for the column structure that the capacitor electric pole plate 208 on 207 surface of electric layer is constituted be 55~130nm (including outer ring and
Inner ring).
It should be pointed out that according to the difference of 2061 horizontal cross sectional geometry of columnar body, the width may have not
With definition, if such as 2061 horizontal cross sectional geometry of the columnar body be circle, width refers to diameter herein, if the column
2061 horizontal cross sectional geometry of shape main body is square, then width refers to side length herein.
Specifically, the floor space of the columnar body 2061 can be greater than the top area of the engagement pad 202, to increase column
The effective area of capacitor lower electrode plate 206 increases the storage charge capability of capacitor with this.
Specifically, the resistivity of material range of the capacitor lower electrode plate 206 and the capacitor electric pole plate 208 is 1
×10-8Ω m to 1 × 102Ωm.As an example, used by the capacitor lower electrode plate 206 and the capacitor electric pole plate 208
Conductive material may include the metals such as Ru (ruthenium), Pt (platinum), Ir (iridium), Pd (palladium) or even metal oxide such as RuO2(oxidation
Ruthenium), IrO2(yttrium oxide) etc. or nitride such as TiN (titanium nitride) etc..
Specifically, the capacitance dielectric layer 207 uses high k (relative dielectric constant) medium, material dielectric constant range is 4
~400.As an example, high K medium material used by the capacitance dielectric layer 207 may include SrTiO3/TiO2Composite layer,
AH(Al2O3/HfO2) composite layer, ZAZ (ZrO2/Al2O3/ZrO2) composite layer, the BST material (iron electrode of composite calcium hematite structure
Material is by BaTiO3And SrTiO3The solid solution formed by a certain percentage) etc..
Specifically, the column capacitance structure further includes capacitor electric pole plate articulamentum 209, the capacitor top electrode connection
Layer 209 is coated on 208 surface of capacitor electric pole plate, and fills the gap between the adjacent capacitor lower electrode plate 206.Institute
The filling for stating capacitor electric pole plate articulamentum 209 can make stable structure, and the electric pole plate of each capacitor is linked together.Make
For example, the material of the capacitor electric pole plate articulamentum 209 includes the polysilicon of doping.
Specifically, the column capacitance structure further includes line contact layer 210, the line contact layer 210 is formed in institute
It states on capacitor electric pole plate articulamentum 209.The line contact layer 210 is alternatively arranged as subsequent erosion in addition to contacting for line
Carve the stop layer of step.As an example, the line contact layer 210 uses conductive metallic material.
Specifically, the column capacitance structure further includes isolated insulation layer 203, the isolated insulation layer 203 is coated on institute
201 surface of substrate is stated, and there is the opening for exposing the engagement pad 202, institute in position corresponding with the engagement pad 202
The bottom for stating columnar body is located in the opening, and connect with the engagement pad 202.The isolated insulation layer 203 as every
Insulating layer from other routes.As an example, the material of the isolated insulation layer 203 includes SiN.
Figure 30 is please referred to, the vertical cross-section diagram of single capacitor in the column capacitance structure of the utility model, Figure 31 are shown as
It is shown as the horizontal sectional view in region shown in the four-headed arrow of outer ring in Figure 30.Figure 32 is shown as in Figure 30 shown in inner ring four-headed arrow
The horizontal sectional view in region.In the present embodiment, the horizontal cross-section of the columnar body 2061 of the capacitor lower electrode plate 206 is circle
Shape, that is to say, that the columnar body 2061 is cylinder, in other embodiments, the column of the capacitor lower electrode plate 206
The horizontal cross-section of main body 2061 is also possible to other shapes, such as ellipse, polygon, and it is practical new should not excessively to limit this herein
The protection scope of type.
Since the capacitor lower electrode plate 206 of the column capacitance structure of the utility model is further in 2061 side wall of columnar body
With annular shoulder 2062, the surface area of capacitive electrode plates can be effectively increased, to obtain bigger charge storage.
Example IV
The present embodiment provides a kind of methods for making column capacitance structure in embodiment three, comprising the following steps:
As shown in Figures 1 and 2, it executes step S201: a substrate 201 being provided, multiple arrays is equipped in the substrate 201 and arranges
The engagement pad 202 of cloth.Wherein, Fig. 1 is shown as the top plan view of the substrate.Fig. 2 is shown as in Fig. 1 area shown in four-headed arrow
The vertical cross-section diagram in domain.
In the present embodiment, multiple engagement pads 202 are arranged in the substrate 201 in six square arrays, in other embodiments,
Multiple engagement pads 202 can also use other array arrangement modes, should not excessively limit the protection scope of the utility model herein.
It should be pointed out that Fig. 1 and Fig. 2 show the array region of initial structure, can have around the array region
Peripheral circuit area, and peripheral circuit area can well in advance starting metal layer (M0).
As shown in Figures 3 and 4, it executes step S202: forming an isolated insulation layer 203 on 201 surface of substrate.Its
In, Fig. 3 is shown as formed as top plan view that the isolated insulation layer 203 is presented after 201 surface of substrate (in figure
It has been shown in broken lines the position of the engagement pad), Fig. 4 is shown as in Fig. 3 the vertical cross-section diagram in region shown in four-headed arrow.
As an example, depositing one layer of nitridation using atom deposition method (Atomic Layer Deposition, abbreviation ALD)
Silicon (SiN) is used as the isolated insulation layer 203, for other routes to be isolated.The thickness range of the isolated insulation layer 203 is 5
~45nm.
As shown in figure 21, it first carries out step S203: forming a hard mask layer 204 on 203 surface of isolated insulation layer.
Specifically, the hard mask layer 204 include at least two layers of first film layers 2041, the first film layer of adjacent two layers 2041 it
Between be interspersed with the second film layer 2042, the wet process that the wet etch rate of second film layer 2042 is greater than first film layer 2041 is carved
Erosion rate.
As an example, first film layer 2041 is non-doped layer, second film layer 2042 is doped layer.The present embodiment
In, the material of first film layer 2041 preferably uses silica, and the material of second film layer 2042 is preferably mixed using boron
Miscellaneous silica.
Specifically, using pulse jet method (pulse gas injection) in the process for forming the hard mask layer 204
In carry out interruption doping, obtain second film layer 2042.
Specifically, the thickness of first film layer 2041 is greater than the thickness of second film layer 2042.As an example, described
The thickness range of first film layer 2041 is 20~500nm, and the thickness range of second film layer 2042 is 3~30nm.
As shown in figure 22, it executes step S204: forming the through-hole 205 of multiple discrete settings in the hard mask layer 204,
The position of each through-hole 205 is corresponding with the position of an engagement pad 202 respectively, and the through-hole 205 is to downward
It extends in the isolated insulation layer 203 to expose 202 upper surface of engagement pad.
As an example, using plasma dry ecthing method, and be etch stop layer with the engagement pad 202, etching obtains
The through-hole 205 is in the hard mask layer 204.
As shown in figure 23, it is formed after the through-hole 205, further executes step S205: carried out wet etching, utilize institute
The first film layer 2041 wet etch rate different from second film layer 2042 is stated, rough through-hole side wall is obtained.
As an example, using concentration for the NH of 0.15wt%~15wt%4Etching solution of the OH aqueous solution as wet etching.
As shown in figure 24, it executes step S206: filling full capacitor lower electrode material in the through-hole 205, and remove institute
Capacitor lower electrode material extra on hard mask layer 204 is stated, the capacitor lower electrode plate 206 of multiple discrete settings is obtained.
Specifically, using atom deposition method (Atomic Layer Deposition, abbreviation ALD) or chemical vapor deposition
Method (Chemical Vapor Deposition, abbreviation CVD) deposited capacitances lower electrode material, then with the erosion of plasma dry method
It carves to the hard mask layer 204.
As shown in figure 25, it executes step S207: removing the hard mask layer 204 around the capacitor lower electrode plate 206.
As it can be seen that since aforementioned wet etching obtains rough through-hole side wall, so that the finally obtained capacitor lower electrode plate 206
Umbrella column is presented, including a columnar body 2061 and is connected at least one layer of annular shoulder of 2061 side wall of columnar body
2062。
It is done as an example, being removed the hard mask layer 204 around the capacitor lower electrode plate 206 with wet etching
Only.
Further, after removing the hard mask layer around the capacitor lower electrode plate, following steps are further included:
As shown in figure 26, it executes step S208: forming a capacitance dielectric layer 207 in multiple capacitor lower electrode plates 206
Surface.As an example, depositing the capacitive dielectric using atom deposition method (Atomic Layer Deposition, abbreviation ALD)
Layer 207.
As shown in figure 27, it executes step S209: forming a capacitor electric pole plate 208 on 207 surface of capacitor dielectric layer.
As an example, forming the capacitor electric pole plate using atom deposition method (Atomic Layer Deposition, abbreviation ALD)
208。
As shown in figure 28, it executes step S210: forming capacitor electric pole plate articulamentum 209 in the capacitor electric pole plate
208 surfaces, the capacitor electric pole plate articulamentum 209 fill the gap between the adjacent capacitor lower electrode plate 206.As showing
Example, deposits the polysilicon of doping, fills up the gap between each columnar capacitor, makes stable structure and by the top electrode of each capacitor
Plate links together.
As shown in figure 29, it executes step S211: forming line contact layer 210 in the capacitor electric pole plate articulamentum 209
On.As an example, the stop layer and line contact layer of deposited metal material subsequent.
So far, production obtains column capacitance structure.In the present embodiment when making hard mask layer, forms multiple pairs of wet processes and carve
Higher second film layer of erosion rate is carved after forming through-hole, then with wet process between lower first film layer of script wet etch rate
The higher multiple thin layers of etching rate are made lateral etch by erosion, form rough through-hole side wall, fill electricity under capacitor thereto
Pole material can form the biggish umbrella column capacitor lower electrode plate of surface area, and capacitor bottom crown can form rough surface,
Effective area is increased, thus can improve the storage charge capability of capacitor.
In conclusion capacitance structure provided by the utility model is simple, the processing step of some complexity can be saved, such as not
Additional processing procedure, which need to be increased, to be separated from each other between capacitor lower electrode plate, so as to reduce technology difficulty, save manufacturing cost,
Suitable for technique more lower than prior art node, such as 17nm or even its technology node below.Capacitor bottom crown can be formed
Rough surface, effective area are increased, thus can improve the storage charge capability of capacitor.So this is practical new
Type effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (15)
1. a kind of column capacitance structure, which is characterized in that the column capacitance structure includes:
Substrate；
Multiple engagement pads of discrete setting, array arrangement is in the substrate；
Multiple capacitor lower electrode plates of discrete setting, the capacitor lower electrode plate include a columnar body, and each column
Main body is connect with an engagement pad respectively；
Capacitance dielectric layer is coated on multiple capacitor lower electrode plate surfaces；
Capacitor electric pole plate is coated on the capacitive dielectric layer surface.
2. column capacitance structure according to claim 1, it is characterised in that: the width range of the columnar body is 35~
100nm。
3. column capacitance structure according to claim 1, it is characterised in that: the floor space of the columnar body is greater than described
The top area of engagement pad.
4. column capacitance structure according to claim 1, it is characterised in that: on the capacitor lower electrode plate and the capacitor
The resistivity of material range of electrode plate is 1 × 10-8Ω m to 1 × 102Ω m, the material dielectric constant range of the capacitance dielectric layer
It is 4~400.
5. column capacitance structure according to claim 1, it is characterised in that: the column capacitance structure further includes on capacitor
Electrode plate articulamentum, the capacitor top electrode articulamentum are coated on capacitor electric pole plate surface, and fill the adjacent electricity
Hold the gap between electrode plate.
6. column capacitance structure according to claim 5, it is characterised in that: the column capacitance structure further includes line and connects
Contact layer, the line contact layer are formed on the capacitor electric pole plate articulamentum.
7. column capacitance structure according to claim 1, it is characterised in that: it is exhausted that the column capacitance structure further includes isolation
Edge layer, the isolated insulation layer is coated on the substrate surface, and has in position corresponding with the engagement pad and expose
The bottom of the opening of the engagement pad, the columnar body is located in the opening, and connect with the engagement pad.
8. a kind of column capacitance structure, which is characterized in that the column capacitance structure includes:
Substrate；
Multiple engagement pads of discrete setting, array arrangement is in the substrate；
Multiple capacitor lower electrode plates of discrete setting, the capacitor lower electrode plate is including a columnar body and is connected to the column
The multi-layer annular flank of shape main body wall, the discrete setting of each layer annular shoulder, each columnar body (2061) is respectively
It is connect with an engagement pad；
Capacitance dielectric layer is coated on multiple capacitor lower electrode plate surfaces；
Capacitor electric pole plate is coated on the capacitive dielectric layer surface.
9. column capacitance structure according to claim 8, it is characterised in that: the thickness of the annular shoulder is less than adjacent institute
The spacing of annular shoulder is stated, the spacing range of the adjacent annular shoulder is 20~500nm.
10. column capacitance structure according to claim 8, it is characterised in that: the width range of the columnar body is 35
~100nm, the thickness range of the annular shoulder are 3~30nm, and width range is 40~105nm.
11. column capacitance structure according to claim 8, it is characterised in that: the floor space of the columnar body is greater than institute
State the top area of engagement pad.
12. column capacitance structure according to claim 8, it is characterised in that: the capacitor lower electrode plate and the capacitor
The resistivity of material range of electric pole plate is 1 × 10-8Ω m to 1 × 102Ω m, the material dielectric constant model of the capacitance dielectric layer
Enclose is 4~400.
13. column capacitance structure according to claim 8, it is characterised in that: the column capacitance structure further includes capacitor
Electric pole plate articulamentum, the capacitor top electrode articulamentum are coated on capacitor electric pole plate surface, and fill adjacent described
Gap between capacitor lower electrode plate.
14. column capacitance structure according to claim 13, it is characterised in that: the column capacitance structure further includes line
Contact layer, the line contact layer are formed on the capacitor electric pole plate articulamentum.
15. column capacitance structure according to claim 8, it is characterised in that: the column capacitance structure further includes isolation
Insulating layer, the isolated insulation layer is coated on the substrate surface, and has exposure in position corresponding with the engagement pad
The bottom of the opening of the engagement pad out, the columnar body is located in the opening, and connect with the engagement pad.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110459533A (en) * | 2018-05-08 | 2019-11-15 | 长鑫存储技术有限公司 | Column capacitance structure and preparation method thereof |
| US11961881B2 (en) | 2020-08-13 | 2024-04-16 | Changxin Memory Technologies, Inc. | Method for forming semiconductor structure and semiconductor structure |
-
2018
- 2018-05-08 CN CN201820677169.4U patent/CN208189581U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110459533A (en) * | 2018-05-08 | 2019-11-15 | 长鑫存储技术有限公司 | Column capacitance structure and preparation method thereof |
| US11961881B2 (en) | 2020-08-13 | 2024-04-16 | Changxin Memory Technologies, Inc. | Method for forming semiconductor structure and semiconductor structure |
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