KR20090027425A - Method for fabricating minute pattern in semiconductor device - Google Patents

Abstract

A method of manufacturing the micro-pattern of the semiconductor device is provided to improve the double patterning technology using photoresist and to implement the pattern having precision. The hard mask layer(23) is formed on the etch target layer(21). The sacrificial layer pattern(24A) is formed on the hard mask layer. The spacer(28A) is formed in the side wall of the sacrificial layer pattern. The sacrificial layer pattern is removed. The hard mask layer is etched by using the spacer as the etch barrier. By using the hard mask layer as the etch barrier, it is the etch target layer is etched to form the pattern.

Description

METHOD FOR FABRICATING MINUTE PATTERN IN SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device manufacturing technology, and more particularly to a method of forming a fine pattern of a semiconductor device.

With high integration of semiconductor devices, finer patterns are essential. However, a pattern required for the implementation of a semiconductor device, for example, a line and space pattern (hereinafter, referred to as an L / S pattern), is limited to be minutely formed due to the limitation of photolithography equipment.

In order to solve this problem, a double patterning technique for forming a pattern using two photomasks has recently been proposed, which facilitates the formation of a fine L / S pattern while using a commercially available photolithography apparatus. Hereinafter, with reference to Figure 1 will be described in more detail.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, after applying the first photoresist PR1 on the etched layer 10 and patterning the first photoresist PR1 by an exposure and development process, the patterned first photoresist PR1 is formed. ) To be etched (10).

As shown in FIG. 1B, after the first photoresist PR1 is removed, the second photoresist PR2 is applied over the entire structure of the resultant product, and the second photoresist PR2 is patterned by an exposure and development process. . In this case, the openings of the patterned second photoresist PR2 do not overlap the openings of the patterned first photoresist PR1.

As illustrated in FIG. 1C, by etching the etched layer 10 again using the patterned second photoresist PR2 as a mask, a fine pattern having a small line / space width may be formed.

However, even when using such a double patterning method, it is difficult to make the line / space width of the pattern below a certain value. This is because the current process technology makes it difficult to make the line / space width below a certain value with two photomasks, and when more photomasks are used, it is difficult to control the overlay accuracy during the exposure process.

Therefore, it is required to implement a fine pattern that can make the line / space width below a predetermined value (for example, a design rule of 35 nm or less) in response to the tendency of high integration of semiconductor devices.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of realizing an accurate and accurate pattern by improving a double patterning technique using a photoresist.

Method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a hard mask layer on the etching target layer; Forming a sacrificial layer pattern on the hard mask layer; Forming a spacer on sidewalls of the sacrificial layer pattern; Removing the sacrificial layer pattern; Etching the hard mask layer using the spacer as an etch barrier; And forming the etching target layer using the hard mask layer as an etching barrier.

In addition, the manufacturing method of the semiconductor device according to the first embodiment of the present invention comprises the steps of forming a hard mask layer on the etching target layer; Forming a sacrificial oxide film pattern on the hard mask layer; Forming a polysilicon spacer on sidewalls of the sacrificial oxide film pattern; Removing the sacrificial oxide film pattern; Etching the hard mask layer with the polysilicon spacer into an etch barrier; And etching the etching target layer by using the hard mask layer as an etching barrier to form a pattern.

In addition, the manufacturing method of the semiconductor device according to the second embodiment of the present invention comprises the steps of forming a hard mask layer on the etching target layer; Forming a sacrificial amorphous carbon pattern on the hard mask layer; Forming an oxide film spacer on sidewalls of the sacrificial amorphous carbon pattern; Removing the sacrificial amorphous carbon pattern; Etching the hard mask layer using the oxide spacer as an etching barrier; And etching the etching target layer by using the hard mask layer as an etching barrier to form a pattern.

In addition, the manufacturing method of the semiconductor device according to the third embodiment of the present invention comprises the steps of forming a hard mask layer on the etching target layer; Forming a sacrificial polysilicon pattern on the hard mask layer; Forming an oxide film spacer on sidewalls of the sacrificial polysilicon pattern; Removing the sacrificial polysilicon pattern; Etching the hard mask layer using the oxide spacer as an etching barrier; And etching the etching target layer by using the hard mask layer as an etching barrier to form a pattern.

Since the semiconductor device manufacturing method according to the present invention described above performs only one exposure, the CD deviation between lines due to misalignment between the first exposure and the second exposure can be reduced, and the one exposure process is performed. This omission has the effect of reducing costs.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

(Example 1)

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 2A, an amorphous carbon layer 22 and a silicon oxynitride film 23 are formed on the etching target layer 21. The amorphous carbon layer 22 may be used as an etching barrier for etching the etching target layer 21, and the silicon oxynitride layer 23 may be used as an etching barrier for etching the amorphous carbon layer 22, and the first silicon oxynitride layer 43 may be used as an etching barrier for etching the amorphous carbon layer 22. In addition, a nitride film can be formed.

Subsequently, a sacrificial oxide film 24 is formed on the silicon oxynitride film 23. The sacrificial oxide film 24 is intended to be used as a sacrificial layer for subsequent double patterning. The sacrificial oxide film 24 may be a silicon oxide (SiO ₂ ) -based film that is well etched in HF, and may be TEOS (Tetra Ethyle Ortho Silicate) or HARP (High Aspect Ratio Process). ), SOD (Spin On Dielectric) and SOG (Spin On Glass) may be any one selected from the group consisting of. In addition, the sacrificial oxide film 24 may be formed to a thickness sufficient to etch the lower silicon oxynitride film 23, but may be formed to be 500 kPa to 2000 kPa.

Subsequently, the first polysilicon layer 25 is formed on the sacrificial oxide film 24. The first polysilicon layer 25 is for etching the sacrificial oxide layer 24. When the sacrificial oxide layer 24 is etched with the photoresist layer, the first polysilicon layer 25 prevents pattern defects due to pattern deformation and reduced selectivity. Can be used for In this case, the thickness of the first polysilicon layer 25 may be adjusted in consideration of an etching selectivity with the sacrificial oxide layer 24, but may be 200 μs to 1000 μs.

Subsequently, an antireflection layer 26 is formed on the first polysilicon layer 25. The anti-reflective layer 26 is intended to be anti-reflective upon subsequent photoresist exposure with Anti Reflection Coating.

Subsequently, a photosensitive film pattern 27 is formed on the antireflection layer 26. The photoresist layer pattern 27 may be formed by coating a photoresist layer on the antireflection layer 26 and patterning the photoresist layer by exposure and development. In particular, the photoresist pattern 27 may be patterned by an emulsion lithography technique, which fills an arbitrary layer of emulsion material between the final projection lens of the projection lens portion and the wafer and forms the layer of emulsion material. It is a technique of improving the resolution of a lithographic apparatus by increasing the numerical aperture (NA) of the optical system by the refractive index of. In this case, the wavelength of the light source propagating in the emulsion material layer corresponds to a value obtained by dividing the wavelength of the light source propagating in the air, which is the actual wavelength, by the refractive index of the emulsion material layer.

In addition, the photoresist pattern 27 is patterned in a line type. The space between the lines is 1: 2.5 to 3.5 in consideration of the final CD (Target) target after the final patterning. It can be patterned to have.

As shown in FIG. 2B, the anti-reflection layer 26 and the first polysilicon layer 25 are etched using the photoresist pattern 27 as an etching barrier. When the etching of the first polysilicon layer 25 is completed, the photoresist pattern 27 and the antireflection layer 26 are all removed, or the photoresist pattern 27 and the photoresist layer 27 are subjected to a strip process after etching the first polysilicon layer 25. The antireflective layer 26 can be removed.

The patterned first polysilicon layer 25 is referred to as a 'first polysilicon pattern 25A'.

Subsequently, the sacrificial oxide film 24 is etched using the first polysilicon pattern 25A as an etching barrier to form the sacrificial oxide film pattern 24A. The sacrificial oxide film 24 may be etched under conditions having an etching selectivity with the first polysilicon pattern 25A, but may be performed by adding CF gas as the main gas and adding oxygen gas.

Next, the second polysilicon layer 28 is formed on the entire structure including the sacrificial oxide film pattern 24A. The second polysilicon layer 28 is formed such that the step coverage (the thickness ratio of the top and sidewalls or the thickness ratio of the top and bottom) is at least 90% or more (90% to 100%), and the lower amorphous carbon layer 22 It is formed at a temperature of at least 550 ° C. (30 ° C. to 550 ° C.) so as not to affect the physical properties of the c. Preferably, it may be formed by atomic layer deposition. In addition to the polysilicon layer, an aluminum oxide film (Al ₂ O ₃ ) using an atomic layer deposition method or a nitride film using an atomic layer deposition method may be formed.

As shown in FIG. 2C, the second polysilicon layer 28 is etched. When the second polysilicon layer 28 is etched, the first polysilicon pattern 25A formed on the sacrificial oxide pattern 24A is etched together to complete the etching of the second polysilicon layer 28. The upper part of the pattern 24A is opened. The second polysilicon layer 28 may be etched by full etching or etch back, but may be performed using a mixed gas of BCl ₃ , C ₂ F _6, and Ar to have physical etching characteristics rather than chemical etching characteristics. This is to prevent the CD of the remaining second polysilicon layer 28 from decreasing when the chemical etching characteristic is strongly acted on.

In addition, in order to minimize the attack of the lower layer (eg, silicon oxynitride layer 23) due to physical etching characteristics, the excessive etching of the second polysilicon layer 28 may be performed using HBr having an etching selectivity with the lower layer. It can be carried out.

Accordingly, the second polysilicon pattern 28A remains on the sidewall of the sacrificial oxide pattern 24A in the form of a spacer.

As described above, by enabling fine patterning in one exposure process, it is possible to improve the overlap accuracy defect due to the two exposure processes. That is, the CD deviation between the lines due to misalignment between the first exposure and the second exposure can be reduced. Moreover, cost reduction can be achieved because one exposure process is omitted.

As shown in FIG. 2D, the sacrificial oxide film pattern 24A is removed. The sacrificial oxide layer pattern 24A may be removed by wet etching. In this case, the wet etching may be performed using HF or BOE (Buffered Oxide Etchant), and preferably, the second polysilicon pattern 28A and the silicon oxynitride layer 23 and HF having high etching selectivity may be used. .

Therefore, the sacrificial oxide film pattern 24A is removed, and the second polysilicon pattern 28A remains on the silicon oxynitride film 23.

As shown in FIG. 2E, the silicon oxynitride layer 23 and the amorphous carbon layer 22 are etched using the second polysilicon pattern 28A as an etching barrier. The silicon oxynitride film 23 and the amorphous carbon layer 22 are separately etched, but the silicon oxynitride film 23 can be performed using plasma using CHF ₃ or CF ₄ as the main gas, and the amorphous carbon layer 22 ) May be etched using a plasma using a mixed gas of O ₂ and N ₂ .

The etched silicon oxynitride layer 23 is referred to as a 'silicon oxynitride layer pattern 23A', and the etched amorphous carbon layer 22 is referred to as an 'amorphous carbon pattern 22A'.

As shown in FIG. 2F, the second polysilicon pattern 28A and the silicon oxynitride film pattern 23A are removed.

Subsequently, the etching target layer 21 is etched using the amorphous carbon pattern 22A as an etching barrier to form the pattern 21A.

(Example 2)

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 3A, the first amorphous carbon layer 32 and the first silicon oxynitride layer 33 are formed on the etching target layer 31. The first amorphous carbon layer 32 may be used as an etching barrier for etching the etching target layer 31, and the first silicon oxynitride layer 33 may be used as an etching barrier for etching the first amorphous carbon layer 32. A nitride film may be formed in addition to the silicon oxynitride film 43.

Next, a polysilicon layer 34 is formed on the first silicon oxynitride film 33. The polysilicon layer 34 is intended to be used as an etch stop layer by securing an etching selectivity in a subsequent process.

Next, the second amorphous carbon layer 35 is formed on the polysilicon layer 34. The second amorphous carbon layer 35 is intended to be used as a sacrificial layer for forming double patterning. The second amorphous carbon layer 35 is easily removed by a photoresist stripper and does not attack the lower layer by securing an etching selectivity. The second amorphous carbon layer 35 for use as a sacrificial layer can be formed to a thickness of 500 kPa to 2000 kPa.

Next, a second silicon oxynitride film 36 is formed on the second amorphous carbon layer 35. The second silicon oxynitride layer 36 is intended to be used as an etching barrier when etching the second amorphous carbon layer 32.

Subsequently, an antireflection layer 37 is formed on the second silicon oxynitride film 36. The anti-reflection layer 37 is intended to reflect the anti-reflective layer upon subsequent photoresist exposure with Anti Reflection Coating.

Subsequently, a photosensitive film pattern 38 is formed on the antireflection layer 37. The photoresist pattern 38 may be formed by coating a photoresist on the antireflection layer 37 and patterning the photoresist with exposure and development. In particular, the photoresist pattern 38 may be patterned by an emulsion lithography technique, which fills an arbitrary layer of emulsion material between the final projection lens of the projection lens portion and the wafer and that layer of emulsion material. This technique improves the resolution of the lithographic apparatus by increasing the numerical aperture (NA) of the optical system by the refractive index of. In this case, the wavelength of the light source propagating in the emulsion material layer corresponds to a value obtained by dividing the wavelength of the light source propagating in the air, which is the actual wavelength, by the refractive index of the emulsion material layer.

In addition, the photoresist pattern 38 is patterned in a line type, and the ratio between the lines and the lines is 1: 2.5 to 3.5 in consideration of the final CD (Target) target after the final patterning. It can be patterned to have.

As shown in FIG. 3B, the anti-reflection layer 37 and the second silicon oxynitride layer 36 are etched using the photoresist pattern 38. The etched second silicon oxynitride layer 36 is referred to as a 'second silicon oxynitride pattern 36A'.

Subsequently, the second amorphous carbon layer 35 is etched using the second silicon oxynitride pattern 36A as an etching barrier to form the second amorphous carbon pattern 35A. The second amorphous carbon layer 35 is a mixed gas selected from the group consisting of a mixed gas of O ₂ , N ₂ , a mixed gas of CO and H ₂ , and a mixed gas of O ₂ , N ₂ , CO, and H ₂ . And the photoresist pattern 38 and the anti-reflection layer 37 are all removed when the etching of the second amorphous carbon pattern 35A is completed.

Subsequently, an oxide film 39 is formed over the entire structure including the second amorphous carbon pattern 35A. The oxide film 39 is formed such that the step coverage (the thickness ratio of the top and sidewalls or the thickness ratio of the top and the bottom) is at least 90% (90% to 100%), and the first amorphous carbon layer 32 and the first It is formed at a temperature of at least 550 ° C. or less (30 ° C. to 550 ° C.) so as not to affect the physical properties of the amorphous carbon pattern 35A. Preferably, it may be formed by atomic layer deposition. In addition to the oxide film, a nitride film using an atomic layer deposition method can be formed.

As shown in FIG. 3C, the oxide film 39 is etched. When the etching of the oxide film 39 is completed, the second silicon oxynitride pattern 36A is lost, or when the oxide film 39 is etched, the second silicon oxynitride pattern 36A is removed to remove the second amorphous carbon pattern 35A. Open the top of the

The etching of the oxide film 39 may be performed by full etching or etch back, and the etching of the second silicon oxynitride pattern 36A may be performed using CF ₄ or CHF ₃ having a small etching selectivity of the oxide and silicon oxynitride film. Can be. In this case, since the polysilicon layer 34 formed on the lower layer of the second amorphous carbon pattern 35A serves as a etch stop layer, the attack of the lower layer may be prevented when the insulating layer 39 is etched.

Accordingly, the second silicon oxynitride pattern 36A is removed, and the oxide film pattern 39A remains on the sidewall of the second amorphous carbon pattern 35A in the form of a spacer.

As shown in FIG. 3D, the second amorphous carbon pattern 35A is removed. The second amorphous carbon pattern 35A may be removed by dry etching, but may be removed by a photosensitive film strip process using oxygen plasma. Therefore, only the second amorphous carbon pattern 35A may be selectively removed without an attack on the lower layer.

By removing the second amorphous carbon pattern 35A, only the oxide film pattern 39A remains on the polysilicon layer 34.

As described above, by enabling fine patterning in one exposure process, it is possible to improve the overlap accuracy defect due to the two exposure processes. That is, the CD deviation between the lines due to misalignment between the first exposure and the second exposure can be reduced. Moreover, cost reduction can be achieved because one exposure process is omitted.

As shown in FIG. 3E, the polysilicon layer 34, the first silicon oxynitride layer 33, and the first amorphous carbon layer 32 are etched using the oxide layer pattern 39A as an etching barrier. The first amorphous carbon layer 32 may be etched under the same conditions as the second amorphous carbon pattern 35A, and the mixed gas of O ₂ and N _2, the mixed gas of CO and H ₂ , and the O ₂ , N ₂ , CO And it can be etched using any one of the mixed gas selected from the group consisting of a mixed gas of H ₂ .

The etched polysilicon layer 34 is a 'polysilicon pattern 34A', the etched first silicon oxynitride layer 33 is a 'first silicon oxynitride layer pattern 33A', and the etched first amorphous carbon layer 32 ) Is referred to as a 'first amorphous carbon pattern 32A'.

As shown in FIG. 3F, the oxide film pattern 39A, the polysilicon pattern 34A, and the first silicon oxynitride film pattern 33A are removed.

Subsequently, the etching target layer 31 is etched using the first amorphous carbon pattern 32A as an etching barrier to form the pattern 21A.

(Example 3)

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.

As shown in FIG. 4A, the amorphous carbon layer 42 and the first silicon oxynitride layer 43 are formed on the etching target layer 41. The amorphous carbon layer 42 may be used as an etching barrier for etching the etching target layer 41, and the first silicon oxynitride layer 43 may be used as an etching barrier for etching the amorphous carbon layer 42, and the first silicon oxynitride layer ( 43) in addition to this, a nitride film can be formed.

Subsequently, a sacrificial polysilicon layer 44 is formed on the first silicon oxynitride layer 43. The sacrificial polysilicon layer 44 is to be used as a sacrificial layer for subsequent double patterning, and the thickness of the sacrificial polysilicon layer 44 is formed to a sufficient thickness to etch the lower first silicon oxynitride layer 43. It can be formed from 500 kV to 2000 kV.

Subsequently, a second silicon oxynitride layer 45 is formed on the sacrificial polysilicon layer 44. The second silicon oxynitride layer 45 is used to etch the sacrificial polysilicon layer 44. When the sacrificial polysilicon layer 44 is etched using the photoresist layer, pattern defects due to pattern deformation and reduced selectivity are prevented. Can be used to prevent this from happening. In this case, the thickness of the second silicon oxynitride layer 45 may be adjusted in consideration of an etching selectivity with the sacrificial polysilicon layer 44, but may be 200 μs to 600 μs. In particular, it may be formed of an oxide film instead of the second silicon oxynitride film 45.

Subsequently, an antireflection layer 46 is formed on the second silicon oxynitride film 45. The anti-reflection layer 46 is intended to reflect the area upon subsequent photoresist exposure with Anti Reflection Coating.

Subsequently, a photosensitive film pattern 47 is formed on the antireflection layer 46. The photoresist layer pattern 47 may be formed by coating a photoresist layer on the antireflection layer 46 and patterning the photoresist layer by exposure and development. In particular, the photoresist pattern 47 may be patterned by an emulsion lithography technique, which fills an arbitrary layer of emulsion material between the final projection lens of the projection lens portion and the wafer and that layer of emulsion material. It is a technique of improving the resolution of a lithographic apparatus by increasing the numerical aperture (NA) of the optical system by the refractive index of. In this case, the wavelength of the light source propagating in the emulsion material layer corresponds to a value obtained by dividing the wavelength of the light source propagating in the air, which is the actual wavelength, by the refractive index of the emulsion material layer.

In addition, the photoresist pattern 47 is patterned in a line type. The space between the lines is 1: 2.5 to 3.5 in consideration of the final CD (Target) target after the final patterning. It can be patterned to have.

As shown in FIG. 4B, the anti-reflection layer 46 and the second silicon oxynitride layer 45 are etched using the photoresist pattern 47 as an etching barrier. When the etching of the second silicon oxynitride film 45 is completed, all of the photoresist pattern 47 and the anti-reflection layer 46 are removed, or the photoresist pattern 47 and the strip process are performed after etching the second silicon oxynitride film 45. The antireflection layer 46 can be removed.

The patterned second silicon oxynitride layer 45 is referred to as a 'second silicon oxynitride layer pattern 45A'.

Subsequently, the sacrificial polysilicon layer 44 is etched using the second silicon oxynitride layer pattern 45A as an etching barrier to form the sacrificial polysilicon pattern 44A. Etching of the sacrificial polysilicon layer 44 is performed under conditions having an etching selectivity with the first silicon oxynitride layer 43 and the second silicon oxynitride layer pattern 45A, but the mixed gas of Cl ₂ and HBr is used as the main gas. It can be used.

Next, an oxide film 48 is formed on the entire structure including the sacrificial polysilicon pattern 44A. The oxide film 48 is formed such that step coverage (thickness ratio of the top and sidewalls or thickness ratio of the top and the bottom) is at least 90% or more (90% to 100%), and the physical properties of the lower amorphous carbon layer 42 It is formed at a temperature of at least 550 ° C. or less (30 ° C. to 550 ° C.) so as not to affect. Preferably, it may be formed by atomic layer deposition. In addition to the oxide film 48, an aluminum oxide film (Al ₂ O ₃ ) using an atomic layer deposition method or a nitride film using an atomic layer deposition method can be formed.

As shown in FIG. 4C, the oxide film 48 is etched. When the oxide film 48 is etched, the second silicon oxynitride pattern 45A formed on the sacrificial polysilicon pattern 44A is etched together to complete the etching of the oxide film 48. The top is open. The etching of the oxide film 48 may be performed by full etching or etch back, and selected from the group consisting of C ₄ F ₆ , C ₄ F ₈ , CF ₄ and CHF ₃ under high power conditions to have physical etching characteristics rather than chemical etching characteristics. It may be carried out using one or more mixed gases. This is to prevent the CD of the oxide layer 48 from remaining small when the chemical etching characteristic is strongly applied.

In addition, an etch stop layer may be further formed on the first silicon oxynitride layer 43 to minimize the attack of the lower layer (eg, the first silicon oxynitride layer 43) due to the physical etching characteristic.

Therefore, the oxide film pattern 48A remains on the sidewall of the sacrificial polysilicon pattern 44A in the form of a spacer.

As described above, by enabling fine patterning in one exposure process, fine patterning is possible while improving overlap accuracy defects caused by two exposure processes. That is, the CD deviation between the lines due to misalignment between the first exposure and the second exposure can be reduced. Moreover, cost reduction can be achieved because one exposure process is omitted.

As shown in FIG. 4D, the sacrificial polysilicon pattern 44A is removed. The sacrificial polysilicon pattern 44A may be removed by wet etching. In this case, the wet etching may be performed using a mixed solution of HF and HNO _{3. In} particular, the wet etching may be performed by adjusting the concentration of HF in the mixed solution to at least 0.1% to prevent loss of the oxide layer pattern 48A. can do.

The sacrificial polysilicon pattern 44A is removed by wet etching, and the oxide layer pattern 48A remains on the first silicon oxynitride layer 43.

As shown in FIG. 4E, the first silicon oxynitride layer 43 and the amorphous carbon layer 42 are etched using the oxide layer pattern 48A as an etching barrier. The first silicon oxynitride layer 43 and the amorphous carbon layer 42 are separately etched, but the first silicon oxynitride layer 43 may be performed using plasma using CHF ₃ or CF ₄ as the main gas, and amorphous. The carbon layer 42 may be etched using a plasma using a mixed gas of O ₂ / N ₂ .

The etched first silicon oxynitride layer 43 is referred to as a 'first silicon oxynitride pattern 43A', and the etched amorphous carbon layer 42 is referred to as an amorphous carbon pattern 42A.

As shown in FIG. 4F, the oxide film pattern 48A and the first silicon oxynitride pattern 43A are removed.

Subsequently, the etching target layer 41 is etched using the amorphous carbon pattern 42A as an etching barrier to form the pattern 41A.

5A to 5C are SEM photographs illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

Referring to FIG. 5A, it can be seen that after the sacrificial oxide film is etched using the polysilicon hard mask as an etching barrier.

Referring to FIG. 5B, it can be seen that a polysilicon layer for double patterning is formed on the sacrificial oxide film. It can be seen that the polysilicon layer has a step coverage of at least 90% or more (90% to 100%) and is formed to the same thickness on the sidewalls and the top of the sacrificial oxide film.

Referring to FIG. 5C, the polysilicon layer may be etched after spacer etching and the sacrificial oxide layer is removed.

As such, by enabling fine patterning in one exposure process, overlap alignment failure due to two exposures can be prevented and cost reduction can be achieved by omitting one exposure process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention;

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention;

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention;

5A to 5C are SEM photographs showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21: etching target layer 22: amorphous carbon layer

23 silicon oxynitride film 24 sacrificial oxide film

25: first polysilicon layer 25: antireflection layer

26: photosensitive film pattern 27: second polysilicon layer

Claims (31)

Forming a hard mask layer on the etching target layer; Forming a sacrificial layer pattern on the hard mask layer; Forming a spacer on sidewalls of the sacrificial layer pattern; Removing the sacrificial layer pattern; Etching the hard mask layer using the spacer as an etch barrier; And Etching the etching target layer by using the hard mask layer as an etching barrier to form a pattern Micropattern manufacturing method of a semiconductor device comprising a. The method of claim 1, Forming the spacers, Forming an insulating film on the entire structure including the sacrificial layer pattern; And Etching the insulating film and remaining on the sidewalls of the sacrificial layer pattern Micropattern manufacturing method of a semiconductor device comprising a. The method of claim 2, The insulating film is any one selected from the group consisting of a polysilicon film, an oxide film and an amorphous carbon layer. The method of claim 2, Etching of the insulating film, A method of manufacturing a fine pattern of a semiconductor device which is an entire surface etching or etch back. Forming a hard mask layer on the etching target layer; Forming a sacrificial oxide film pattern on the hard mask layer; Forming a polysilicon spacer on sidewalls of the sacrificial oxide film pattern; Removing the sacrificial oxide film pattern; Etching the hard mask layer with the polysilicon spacer into an etch barrier; And Etching the etching target layer by using the hard mask layer as an etching barrier to form a pattern Micropattern manufacturing method of a semiconductor device comprising a. The method of claim 5, Forming the polysilicon spacer, Forming a polysilicon layer on the entire structure including the sacrificial oxide film pattern; And Etching the polysilicon layer and remaining on sidewalls of the sacrificial oxide layer pattern Micropattern manufacturing method of a semiconductor device comprising a. The method of claim 6, Forming the polysilicon layer, Micropattern manufacturing method of a semiconductor element performed at the temperature of 30 degreeC-550 degreeC. The method of claim 6, Etching of the polysilicon layer, A method of manufacturing a fine pattern of a semiconductor device which is an entire surface etching or etch back. The method of claim 8, The polysilicon layer is etched using a plasma using a mixed gas of BCl ₃ , C ₂ F ₆ and Ar is a method of manufacturing a fine pattern of a semiconductor device. The method of claim 6, After the etching of the polysilicon layer is subjected to the transient etching, the transient etching is performed using a HBr fine pattern of a semiconductor device. The method of claim 5, The sacrificial oxide pattern is a silicon oxide film fine pattern manufacturing method of a semiconductor device. The method of claim 11, The silicon oxide film is any one selected from the group consisting of TEOS (Tetra Ethyle Ortho Silicate), HARP (High Aspect Ratio Process) oxide, SOD (Spin On Dielectric) and SOG (Spin On Glass). The method of claim 11, Removing the sacrificial oxide film pattern, Method for manufacturing a fine pattern of a semiconductor device performed by wet etching. The method of claim 13, The wet etching is a method of manufacturing a fine pattern of a semiconductor device performed by HF or BOE (Buffered Oxide Etchant). The method of claim 5, The hard mask layer is a method of manufacturing a fine pattern of a semiconductor device which is a laminated structure of an amorphous carbon layer and a silicon oxynitride film. Forming a hard mask layer on the etching target layer; Forming a sacrificial amorphous carbon pattern on the hard mask layer; Forming an oxide film spacer on sidewalls of the sacrificial amorphous carbon pattern; Removing the sacrificial amorphous carbon pattern; Etching the hard mask layer using the oxide spacer as an etching barrier; And Etching the etching target layer by using the hard mask layer as an etching barrier to form a pattern Micropattern manufacturing method of a semiconductor device comprising a. The method of claim 16, Forming the oxide film spacer, Forming an oxide film on the entire structure including the sacrificial amorphous carbon pattern; And Etching the oxide layer and remaining on sidewalls of the sacrificial amorphous carbon pattern Micropattern manufacturing method of a semiconductor device comprising a. The method of claim 17, Forming the oxide film, Micropattern manufacturing method of a semiconductor element performed at the temperature of 30 degreeC-550 degreeC. The method of claim 17, Etching of the oxide film, A method of manufacturing a fine pattern of a semiconductor device which is an entire surface etching or etch back. The method of claim 19, The etching of the oxide film is a method of manufacturing a fine pattern of a semiconductor device performed using CF ₄ or CHF ₃ . The method of claim 16, Removing the sacrificial oxide film pattern, A fine pattern manufacturing method of a semiconductor device performed by dry etching. The method of claim 21, The dry etching is a fine pattern manufacturing method of a semiconductor device performed by oxygen strip. The method of claim 16, The hard mask layer is a method of manufacturing a fine pattern of a semiconductor device which is a laminated structure of an amorphous carbon layer and a silicon oxynitride film. Forming a hard mask layer on the etching target layer; Forming a sacrificial polysilicon pattern on the hard mask layer; Forming an oxide film spacer on sidewalls of the sacrificial polysilicon pattern; Removing the sacrificial polysilicon pattern; Etching the hard mask layer using the oxide spacer as an etching barrier; And Etching the etching target layer by using the hard mask layer as an etching barrier to form a pattern Micropattern manufacturing method of a semiconductor device comprising a. The method of claim 24, Forming the oxide film spacer, Forming an oxide film on the entire structure including the sacrificial polysilicon pattern; And Etching the oxide layer and remaining on the sidewalls of the sacrificial polysilicon pattern Micropattern manufacturing method of a semiconductor device comprising a. The method of claim 25, Forming the oxide film, Micropattern manufacturing method of a semiconductor element performed at the temperature of 30 degreeC-550 degreeC. The method of claim 25, Etching of the oxide film, A method of manufacturing a fine pattern of a semiconductor device which is an entire surface etching or etch back. The method of claim 27, The etching of the oxide film is a method for manufacturing a fine pattern of a semiconductor device using any one or two or more mixed gas selected from the group consisting of C ₄ F ₆ , C ₄ F ₈ , CF ₄ and CHF ₃ . The method of claim 24, Removing the sacrificial polysilicon pattern, Method for manufacturing a fine pattern of a semiconductor device performed by wet etching. The method of claim 29, The wet etching method of manufacturing a fine pattern of a semiconductor device is performed using a mixed solution of HF and HNO ₃ . The method of claim 24, The hard mask layer is a method of manufacturing a fine pattern of a semiconductor device which is a laminated structure of an amorphous carbon layer and a silicon oxynitride film.

Images