CN110098109B - Metal gate and method of making the same - Google Patents

Metal gate and method of making the same Download PDF

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CN110098109B
CN110098109B CN201910399038.3A CN201910399038A CN110098109B CN 110098109 B CN110098109 B CN 110098109B CN 201910399038 A CN201910399038 A CN 201910399038A CN 110098109 B CN110098109 B CN 110098109B
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patterned
photoresist
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CN110098109A (en
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杨渝书
伍强
李艳丽
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Shanghai IC R&D Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out

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Abstract

The invention provides a metal grid and a manufacturing method thereof, and provides a substrate, wherein the substrate comprises a first area and a second area, a grid film layer, a first hard mask layer, a silicon material layer, a composite organic layer barrier layer and a graphical first photoresist layer are formed on the substrate, the graphical first photoresist layer is provided with an initial first graph and an initial second graph, the initial first graph is provided with a first opening, and the initial second graph is provided with a second opening; forming a patterned silicon material layer; generating a first graph; forming a second patterned photoresist on the substrate, and etching the silicon material layer in the second region by taking the second patterned photoresist as a mask to generate a second pattern and form a second patterned hard mask layer; the patterned grid film layer is formed, so that the photoetching process is optimized, the process difficulty is reduced, the production cost is reduced, the influence of the process on the appearance of the subsequently formed first graph and the second graph of the grid is reduced, the process difficulty is reduced, and the process stability is improved.

Description

Metal gate and method of making the same
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a metal gate and a method for manufacturing the same.
Background
With the development of semiconductor technology, advanced logic chip processes have reached process processes below the 28nm node. The gate process is used as a core technology of an advanced logic chip process, and after a 28nm technology node is entered, the gate process is converted from a traditional polysilicon gate into a Metal Gate (MG) with a high dielectric constant (HK) gate dielectric layer, which is generally referred to as HKMG for short. In the forming process of the HKMG, a polysilicon dummy gate morphology (dummy gate) needs to be generated first, polysilicon is removed after the silicon oxide isolation layer is filled, then metal is filled, and finally a metal gate is formed (i.e. a gate last technology), and the whole process is very complicated.
With the further scaling of chip size, for example, after entering the 14nm Finfet technology node, especially starting from the 12/10nm node, since the polysilicon dummy gate pattern period has exceeded the exposure limit of the conventional lithography machine (for example, 193 nm immersion lithography machine), the Self-Aligned dual imaging (SADP) technique has been introduced to define the gate line pattern, but the gate line size in the gate pattern formed by this technique has limitations. Therefore, other process steps must be used to break its limitations and to form gate lines of different sizes to meet the requirements of various devices on the chip.
In order to obtain gate lines with different dimensions, a silicon oxide hard mask line is usually formed in a device region with a dense pattern by SADP, then an organic composite mask line pattern in a logic region is formed by using an organic composite barrier layer (tri-layer mask), the pattern is transferred to a silicon nitride hard mask layer by dry etching, and finally gate lines with different dimensions are formed by using the silicon nitride hard mask layer as a mask, and finally a metal gate is formed. The whole process has the following problems:
a. the process steps are complicated;
b. the difficulty of the process is high, so that the grid pattern cannot be accurately copied, the process window of the whole process is narrow, and the stability of the process is not facilitated.
Disclosure of Invention
The invention aims to provide a metal grid and a manufacturing method thereof, which can optimize the process, reduce the process difficulty and improve the process window, thereby achieving the purposes of reducing the cost and improving the process stability.
In order to solve the above problems, the present invention provides a method for manufacturing a metal gate, comprising the steps of:
providing a substrate, wherein the substrate comprises a first area and a second area, a grid film layer, a first hard mask layer, a silicon material layer, a composite organic layer barrier layer and a patterned first photoresist layer are formed on the substrate, the patterned first photoresist layer is provided with an initial first pattern in the first area, the patterned first photoresist layer is provided with an initial second pattern in the second area, the initial first pattern is provided with a first opening, and the initial second pattern is provided with a second opening;
sequentially etching the composite organic layer barrier layer and the silicon material layer by taking the patterned first photoresist layer as a mask, and copying the initial first pattern and the initial second pattern into the silicon material layer to form a patterned silicon material layer;
forming a second hard mask layer on the substrate, wherein the second hard mask layer covers the surface of the silicon material layer and the side walls of the first opening and the second opening, and etching the second hard mask layer on the surface of the silicon material layer to generate a first pattern;
forming a second patterned photoresist on the substrate, and etching the silicon material layer in the second region by using the second patterned photoresist as a mask to generate a second pattern and form a second patterned hard mask layer; and
and taking the silicon material layer and the patterned second hard mask layer as masks, sequentially etching the first hard mask layer and the gate film layer, stopping in the gate film layer with partial depth, and copying the first pattern and the second pattern into the gate film layer to form the patterned gate film layer.
Optionally, forming a patterned second photoresist on the substrate, etching the silicon material layer in the second region by using the patterned second photoresist as a mask to generate a second pattern, and forming a patterned second hard mask layer includes the following steps:
forming a second photoresist on the substrate;
forming a second patterned photoresist, wherein the second patterned photoresist exposes the second region and covers the first pattern of the first region;
etching the silicon material layer of the second area by taking the patterned second photoresist as a mask; and
and removing the residual second photoresist by an ashing mode and a cleaning process.
Furthermore, the second photoresist is KrF photoresist with lower cost.
Further, the thickness of the second photoresist is
Figure BDA0002059129810000031
Further, the first hard mask layer comprises a silicon oxide layer and a silicon nitride layer which are sequentially formed on the gate film layer; the material of the silicon material layer is polysilicon.
Further, the thickness of the silicon oxide layer is
Figure BDA0002059129810000032
The thickness of the silicon nitride layer is
Figure BDA0002059129810000033
The thickness of the silicon material layer is
Figure BDA0002059129810000034
Further, the thickness of the first photoresist layer is
Figure BDA0002059129810000035
Further, forming a second hard mask layer on the substrate, where the second hard mask layer covers the surface of the silicon material layer and the sidewalls of the first opening and the second opening, and etching the second hard mask layer on the surface of the silicon material layer to generate a first pattern includes:
depositing a second hard mask layer with uniform thickness on the substrate by adopting an ALD (atomic layer deposition) process, wherein the second hard mask layer covers the surface of the silicon material layer and the side walls of the first opening and the second opening; and
and dry etching the second hard mask layer on the surface of the silicon material layer to generate a first pattern.
Further, the thickness of the second hard mask layer is 16nm-20 nm.
The invention also provides a metal grid which is prepared by adopting the manufacturing method.
Compared with the prior art, the method has the following beneficial effects:
according to the metal gate and the manufacturing method thereof, in the manufacturing method of the metal gate, when the graphical second hard mask layer is formed, only the graphical second photoresist is used as the mask to carry out the etching process, so that the photoetching process is optimized, the process difficulty is reduced, and the production cost is also reduced; when the patterned grid film layer is formed, the silicon medium layer which is made of silicon material and the patterned second hard mask layer are used as masks, so that the materials of polymers generated in the etching process of the first area and the second area are completely the same, therefore, the residues do not influence the appearance of the subsequently formed first graph and the second graph of the grid, the process difficulty is reduced, and the process stability is improved. In addition, when the second pattern is generated, because the second area of the large area is only required to be exposed when the patterned second photoresist is formed, the photomask grade in the whole process is low, the second photoresist adopts the KrF photoresist with low cost, and the cost is reduced.
Drawings
FIGS. 1a-1g are schematic structural diagrams of steps of a method for fabricating a metal gate;
FIG. 2 is a flow chart illustrating a method for fabricating a metal gate according to an embodiment of the present invention;
fig. 3a to 3g are schematic structural diagrams of steps of a method for manufacturing a metal gate according to an embodiment of the invention.
Description of reference numerals:
in FIGS. 1a-1 g:
10-a silicon substrate; 11-a first polysilicon layer; 12-a first oxide layer; 13-a silicon nitride layer; 14-a second polysilicon layer; 20-a second oxide layer; 30-a second composite organic layer barrier layer; 40-a second photoresist layer; a-an opening;
in FIGS. 3a-3 g:
i-a first region; II-a second region; a-a first opening; b-a second opening;
100-a substrate; 110-a gate film layer; 120-a first hard mask layer; 130-a layer of silicon material; 140-organic composite layer; 150-a first photoresist layer;
200-a second hard mask layer;
300-second photoresist.
Detailed Description
The conventional method for manufacturing the metal gate comprises the following steps:
step S11: referring to fig. 1a, a silicon substrate 10 is provided, a first polysilicon layer 11, a first oxide layer 12, a silicon nitride layer 13, a second polysilicon layer 14, a first composite organic layer barrier layer and a patterned first photoresist layer are sequentially formed on the silicon substrate 10, the silicon substrate 10 includes a logic region I and a device region II, the patterned first photoresist layer has an initial second pattern in the device region II, the first composite organic layer barrier layer and the second polysilicon layer 14 are sequentially etched using the patterned first photoresist layer as a mask, the initial second pattern is copied to the second polysilicon layer 14 to form a patterned second polysilicon layer 14, and the patterned second polysilicon layer 14 has an opening a at the position where the device region II has the initial second pattern and exposes the second polysilicon layer 14 in the logic region I, wherein the first photoresist adopts ArF photoresist;
step S12: referring to fig. 1b, a second oxide layer 20 is formed on the second polysilicon layer 14, wherein the second oxide layer 20 further covers the bottom and the sidewall of the opening a;
step S13: referring to fig. 1c, the second oxide layer 20 and the second polysilicon layer 14 are sequentially etched to leave the second oxide layer 20 on the sidewall of the opening s, so as to form a second pattern, and a patterned second oxide layer 20 is formed;
step S14: referring to fig. 1d, a second composite organic layer barrier layer 30 is formed on the silicon nitride layer 13, and a patterned second photoresist layer 40 is formed on the second composite organic layer barrier layer 30 in the logic region I, wherein the second composite organic layer barrier layer 30 covers the second oxide layer 20, and the patterned second photoresist layer 40 has a first pattern in the logic region I;
step S15: referring to fig. 1e, the second composite organic layer barrier layer 30 is etched using the patterned second photoresist layer 40 as a mask, and the first pattern is copied into the second composite organic layer barrier layer 30 to form the patterned second composite organic layer barrier layer 30 and expose the first pattern, wherein the first photoresist is ArF photoresist;
step S16: referring to fig. 1f, in the logic region I, the silicon nitride layer 13 is further etched by using the patterned second photoresist layer 40 and the second composite organic layer blocking layer 30 as masks, the second pattern is copied into the silicon nitride layer 13, in the device region II, the silicon nitride layer 13 is further etched by using the second oxide layer 20 as masks, the first pattern is copied into the silicon nitride layer 13 to form the patterned silicon nitride layer 13, the first oxide layer 12 is exposed, and then the second oxide layer 20 and the second composite organic layer blocking layer 30 are removed; and
step S17: referring to fig. 1g, the patterned silicon nitride layer 13 is used as a mask to further etch the first oxide layer 12 and the first polysilicon layer 11, and the etching is stopped in the first polysilicon layer 11, and the first pattern and the second pattern are copied to the first polysilicon layer 11 to form a gate pattern, and finally a metal gate is formed.
The inventor researches and discovers that in the manufacturing method, 2 times of photoetching processes are needed, the two times of photoetching processes need to adopt an organic composite barrier layer structure, meanwhile, the photoresist adopts ArF photoresist, the photoresist has high requirement on the mask level precision, the whole process is complex, and the production cost is high. In the logic area of the step S16, further etching is performed by using the patterned second photoresist layer and the composite organic layer barrier layer as masks, and the process mask material is an organic material; and further etching the device region by using the second oxide layer as a mask, wherein the mask material in the process is an oxide, the materials of polymers generated in the two regions in the whole etching process are completely different, and the completely different polymers increase the difficulty degree of pattern precision transfer (including accurate size and vertical side wall appearance), so that the size of the gate pattern is not accurate enough and/or the gate pattern has an inclination angle in the vertical direction, and the process window of the whole process is narrow, which is not favorable for process stability.
Based on the research, the core idea of the metal gate and the manufacturing method thereof is that in the manufacturing method of the metal gate, when a graphical second hard mask layer is formed, only a graphical second photoresist is used as a mask to perform an etching process, so that the photoetching process is optimized, the process difficulty is reduced, and the production cost is also reduced; when the patterned grid film layer is formed, the silicon medium layer which is made of silicon material and the patterned second hard mask layer are used as masks, so that the materials of polymers generated in the etching process of the first area and the second area are completely the same, therefore, the residues do not influence the appearance of the subsequently formed first graph and the second graph of the grid, the process difficulty is reduced, and the process stability is improved. In addition, when the second pattern is generated, because the second area of the large area is only required to be exposed when the patterned second photoresist is formed, the photomask grade in the whole process is low, the second photoresist adopts the KrF photoresist with low cost, and the cost is reduced.
A metal gate and a method of fabricating the same of the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
The present embodiment provides a method for manufacturing a metal gate. Fig. 2 is a schematic flow chart illustrating a method for manufacturing a metal gate according to the present embodiment. As shown in fig. 2, the manufacturing method includes the steps of:
step S21: providing a substrate, wherein the substrate comprises a first area and a second area, a grid film layer, a first hard mask layer, a silicon material layer, a composite organic layer barrier layer and a patterned first photoresist layer are formed on the substrate, the patterned first photoresist layer is provided with an initial first pattern in the first area, the patterned first photoresist layer is provided with an initial second pattern in the second area, the initial first pattern is provided with a first opening, and the initial second pattern is provided with a second opening;
step S22: sequentially etching the composite organic layer barrier layer and the silicon material layer by taking the patterned first photoresist layer as a mask, and copying the initial first pattern and the initial second pattern into the silicon material layer to form a patterned silicon material layer;
step S23: forming a second hard mask layer on the substrate, wherein the second hard mask layer covers the surface of the silicon material layer and the side walls of the first opening and the second opening, and etching the second hard mask layer on the surface of the silicon material layer to generate a first pattern;
step S24: forming a second patterned photoresist on the substrate, and etching the silicon material layer in the second region by using the second patterned photoresist as a mask to generate a second pattern and form a second patterned hard mask layer; and
step S25: and taking the silicon material layer and the patterned second hard mask layer as masks, sequentially etching the first hard mask layer and the gate film layer, stopping in the gate film layer with partial depth, and copying the first pattern and the second pattern into the gate film layer to form the patterned gate film layer.
The method of fabricating a metal gate according to the present invention will be described in detail with reference to the following embodiments and fig. 3a to 3 g.
As shown in fig. 3a, step S21 is performed first, a substrate 100 is provided, the substrate 100 includes a first region I and a second region II, the substrate 100 is formed with a gate film layer 110, a first hard mask layer 120, a silicon material layer 130, a composite organic layer barrier layer 140, and a patterned first photoresist layer 150, the patterned first photoresist layer 150 has an initial first pattern in the first region I, and has an initial second pattern in the second region II, the initial first pattern has a first opening a, and the initial second pattern has a second opening b.
The method specifically comprises the following steps:
specifically, first, a substrate 100 is provided, and a gate film layer 110, a first hard mask layer 120, a silicon material layer 130 and an organic composite layer 140 are sequentially formed on the substrate 100. In this embodiment, the substrate 100 is a planar substrate, and the material of the substrate 100 is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate). In another embodiment, the base includes a substrate and a fin portion on a surface of the substrate, and may further include: the isolation layer is positioned on the surface of the substrate, covers partial side walls of the fin portion, and the surface of the isolation layer is lower than the top surface of the fin portion. And the subsequently formed gate film covers the top surface and the side wall surface of the fin part, and the gate film also covers the surface of the isolation layer.
The substrate 100 includes a plurality of first regions I and second regions II, where the first regions I are, for example, logic regions with relatively sparse patterns, and the second regions II are, for example, device regions with relatively dense patterns, such as storage regions of a memory. The gate film layer 110 provides a process foundation for the subsequent formation of a gate; the gate film layer 110 is made of polysilicon or doped polysilicon; the gate film layer 110 is formed by a chemical vapor deposition method, a physical vapor deposition method, or an atomic layer deposition method. The substrate 100 further has a gate dielectric film (not shown in the figure), and the gate dielectric film is used for forming a gate dielectric layer subsequently; the gate dielectric film is made of silicon oxide, silicon nitride or silicon oxynitride. The first hard mask layer 120 and the silicon material layer 130 are in subsequent shapesThe grid forming pattern layer provides a process foundation. The first hard mask layer 120 is made of one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride or amorphous carbon; the material of the silicon material layer 130 is monocrystalline silicon, polycrystalline silicon or amorphous silicon. In the present embodiment, the first hard mask layer 120 includes a silicon oxide layer and a silicon nitride layer sequentially formed on the gate film layer 110; the material of the silicon material layer 130 is polysilicon. The thickness of the silicon oxide layer is
Figure BDA0002059129810000081
The thickness of the silicon nitride layer is
Figure BDA0002059129810000082
The thickness of the silicon material layer 130 is
Figure BDA0002059129810000083
The organic composite Layer 140 includes, but is not limited to, an organic material Layer (SOC) and a Silicon-Containing Anti-Reflective Coating (Silicon-insulating-Anti-Reflective-Coating-Layer, SiARC), for example. The thickness of the organic material layer is
Figure BDA0002059129810000084
The silicon-containing anti-reflective coating has a thickness of
Figure BDA0002059129810000085
Figure BDA0002059129810000086
Next, a first photoresist layer 150 is formed on the organic composite layer 140, and a patterned first photoresist layer 150 is formed, wherein the patterned first photoresist layer 150 has an initial first pattern in the first region I, and has an initial second pattern in the second region II, the initial first pattern has a first opening a, and the initial second pattern has a second opening b.
Wherein, the first photoresist layer 150 is, for example, ArF photoresist, and the thickness of the first photoresist layer 150 is
Figure BDA0002059129810000091
As shown in fig. 3b, step S22 is performed to sequentially etch the composite organic layer barrier layer 140 and the silicon material layer 130 using the patterned first photoresist layer 150 as a mask, and copy the initial first pattern and the initial second pattern into the silicon material layer 130 to form the patterned silicon material layer 130.
In this step, the patterned silicon material layer 130 exposes the first hard mask layer 120.
Next, the remaining organic composite layer 140 is removed by ashing and a cleaning process.
As shown in fig. 3c and 3d, next, step S23 is performed, a second hard mask layer 200 is formed on the substrate 100, the second hard mask layer 200 covers the surface of the silicon material layer 130 and the sidewalls of the first opening a and the second opening b, and the second hard mask layer 200 on the surface of the silicon material layer 130 is etched to generate a first pattern.
The method specifically comprises the following steps:
as shown in fig. 3c, first, an ald (atomic Layer deposition) atomic Layer deposition process is used to deposit a second hard mask Layer 200 with a uniform thickness on the substrate 100, in which the second hard mask Layer 200 covers not only the upper surface of the silicon material Layer 130, but also the sidewalls and the bottom of the opening a and the second opening b. Wherein the thickness of the second hard mask layer 200 is 16nm to 20 nm.
As shown in fig. 3d, the second hard mask layer 200 on the surface of the silicon material layer 130 is then dry etched to form a first pattern.
In this step, the second hard mask layer 200 on the surface of the silicon material layer 130 is dry etched, and the surface of the silicon material layer 130 covered by the second hard mask layer 200 is exposed, and the second hard mask layer 200 with a partial height on the sidewalls of the first opening a and the second opening b is remained.
As shown in fig. 3e and 3f, step S24 is performed to form a patterned second photoresist 300 on the substrate 100, and the patterned second photoresist 300 is used as a mask to etch the silicon material layer 130 in the second region II to generate a second pattern, so as to form a patterned second hard mask layer 200. As can be seen, the mask for forming the patterned second hard mask layer 200 is only the patterned second photoresist 300, which optimizes the photolithography process, reduces the process difficulty, and also reduces the production cost compared to the prior art in which the photoresist and the composite organic layer barrier layer are used as masks.
First, as shown in fig. 3e, a second photoresist 300 is formed on the substrate 100, wherein the second photoresist 300 has a thickness of
Figure BDA0002059129810000101
Then, the second photoresist 300 is patterned. The second patterned photoresist 300 exposes the second region II, and covers the first pattern of the first region I, and since the second patterned photoresist only needs to expose the second region of the large region, the photomask grade in the whole process is low, the second patterned photoresist 300 uses KrF photoresist with low cost, so as to reduce the cost.
Next, as shown in fig. 3f, the patterned second photoresist 300 is used as a mask to etch the silicon material layer 130 in the second region II, and due to the high etching selectivity of the silicon material layer 130 to the first hard mask layer 120 and the silicon material layer 130 to the second hard mask layer 200, the consumption of the first hard mask layer 120 and the second hard mask layer 200 is very small and almost no loss occurs when etching the silicon material layer 130, so that the topography and the size of the second pattern are hardly affected when forming the second pattern.
Then, the second photoresist 300 is removed by ashing and cleaning processes, and the first pattern of the first region I is exposed.
As shown in fig. 3g, step S25 is performed, and the silicon dielectric layer 130 and the patterned second hard mask layer 200 are used as masks, the first hard mask layer 120 and the gate film layer 110 are sequentially etched and stopped in the gate film layer 110 with a partial depth, and the first pattern and the second pattern are copied into the gate film layer 110 to form a patterned gate film layer. It can be seen that, when the first pattern and the second pattern are copied to the gate film layer 110 in this step, since the silicon dielectric layer 130 and the patterned second hard mask layer 200 are both made of silicon material, and the materials of the polymers generated in this etching process are completely the same, the polymers do not affect the appearance of the subsequently formed first pattern and second pattern of the gate, thereby reducing the process difficulty and improving the process stability.
The method specifically comprises the following steps:
first, the silicon dielectric layer 130 and the patterned second hard mask layer 200 are used as masks, the first hard mask layer 120 is etched, the first hard mask layer 120 is stopped in a part of the depth, and the first pattern and the second pattern are copied to the first hard mask layer 120 to form the patterned first hard mask layer 120. At this time, a portion of the silicon dielectric layer 130 and the second hard mask layer 200 in the first region I still remains, and a portion of the second hard mask layer 200 in the second region II also remains.
Then, the silicon dielectric layer 130 and the patterned second hard mask layer 200 are used as masks, the gate film layer 110 is etched, the gate film layer 110 stops at a part of the depth, and the first pattern and the second pattern are copied to the gate film layer 110 to form the patterned gate film layer 110, so that the metal gate is formed.
The embodiment also provides a metal gate which is prepared by adopting the manufacturing method.
In summary, according to the metal gate and the manufacturing method thereof provided by the invention, in the manufacturing method of the metal gate, when the patterned second hard mask layer is formed, only the patterned second photoresist is used as a mask to perform an etching process, so that the photolithography process is optimized, the process difficulty is reduced, and the production cost is also reduced; when the patterned grid film layer is formed, the silicon medium layer which is made of silicon material and the patterned second hard mask layer are used as masks, so that the materials of polymers generated in the etching process of the first area and the second area are completely the same, therefore, the residues do not influence the appearance of the subsequently formed first graph and the second graph of the grid, the process difficulty is reduced, and the process stability is improved. In addition, when the second pattern is generated, because the second area of the large area is only required to be exposed when the patterned second photoresist is formed, the photomask grade in the whole process is low, the second photoresist adopts the KrF photoresist with low cost, and the cost is reduced.
In addition, it should be noted that the description of the terms "first", "second", and the like in the specification is only used for distinguishing each component, element, step, and the like in the specification, and is not used for representing a logical relationship or a sequential relationship between each component, element, step, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (10)

1. A method for manufacturing a metal gate electrode comprises the following steps:
providing a substrate, wherein the substrate comprises a first area and a second area, a grid film layer, a first hard mask layer, a silicon material layer, a composite organic layer barrier layer and a patterned first photoresist layer are formed on the substrate, the patterned first photoresist layer is provided with an initial first pattern in the first area, the patterned first photoresist layer is provided with an initial second pattern in the second area, the initial first pattern is provided with a first opening, and the initial second pattern is provided with a second opening;
sequentially etching the composite organic layer barrier layer and the silicon material layer by taking the patterned first photoresist layer as a mask, and copying the initial first pattern and the initial second pattern into the silicon material layer to form a patterned silicon material layer;
forming a second hard mask layer on the substrate, wherein the second hard mask layer covers the surface of the silicon material layer and the side walls of the first opening and the second opening, and etching the second hard mask layer on the surface of the silicon material layer to generate a first pattern in both the first area and the second area;
forming a second patterned photoresist on the substrate, wherein the second patterned photoresist exposes the second region and covers the first pattern of the first region, and etching the silicon material layer of the second region by using the second patterned photoresist as a mask so as to generate a second pattern in the second region and form a second patterned hard mask layer; and
and taking the silicon material layer and the patterned second hard mask layer as masks, sequentially etching the first hard mask layer and the gate film layer, stopping in the gate film layer with partial depth, and copying the first pattern of the first region and the second pattern of the second region into the gate film layer to form the patterned gate film layer.
2. The method of manufacturing of claim 1, wherein forming a patterned second photoresist on the substrate, the patterned second photoresist exposing the second region, covering the first pattern of the first region, and etching the silicon material layer of the second region using the patterned second photoresist as a mask to create a second pattern in the second region, the forming of the patterned second hard mask layer comprising:
forming a second photoresist on the substrate;
forming a second patterned photoresist, wherein the second patterned photoresist exposes the second region and covers the first pattern of the first region;
etching the silicon material layer of the second area by taking the patterned second photoresist as a mask; and
and removing the residual second photoresist by an ashing mode and a cleaning process.
3. The method of claim 2, wherein the second photoresist is a low cost KrF photoresist.
4. The method of claim 3, wherein the second photoresist has a thickness of
Figure FDA0002841654630000021
5. The manufacturing method according to any one of claims 1 to 3, wherein the first hard mask layer comprises a silicon oxide layer and a silicon nitride layer formed on the gate film layer in this order; the material of the silicon material layer is polysilicon.
6. The method of claim 5, wherein the silicon oxide layer has a thickness of
Figure FDA0002841654630000023
The thickness of the silicon nitride layer is
Figure FDA0002841654630000022
The thickness of the silicon material layer is
Figure FDA0002841654630000024
7. The manufacturing method according to any one of claims 1 to 3, wherein the first photoresist layer has a thickness of
Figure FDA0002841654630000025
8. The method of any of claims 1-3, wherein forming a second hard mask layer on the substrate, the second hard mask layer covering a surface of the silicon material layer and sidewalls of the first and second openings, and etching the second hard mask layer on the surface of the silicon material layer to create a first pattern in both the first and second regions comprises:
depositing a second hard mask layer with uniform thickness on the substrate by adopting an ALD (atomic layer deposition) process, wherein the second hard mask layer covers the surface of the silicon material layer and the side walls of the first opening and the second opening; and
and dry etching the second hard mask layer on the surface of the silicon material layer to generate a first pattern in the first region and the second region.
9. The manufacturing method according to claim 8, wherein a thickness of the second hard mask layer is 16nm to 20 nm.
10. A metal gate electrode produced by the production method according to any one of claims 1 to 9.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050040579A (en) * 2003-10-29 2005-05-03 주식회사 하이닉스반도체 Method for fabricating semiconductor devcie having tungsten poly metal gate-electrode
KR20080002487A (en) * 2006-06-30 2008-01-04 주식회사 하이닉스반도체 Method for forming landing plug of semiconductor device
CN101217106A (en) * 2007-01-04 2008-07-09 海力士半导体有限公司 Method for fabricating semiconductor device
CN106206687A (en) * 2015-05-29 2016-12-07 台湾积体电路制造股份有限公司 The structure of semiconductor device structure and forming method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977181B2 (en) * 2008-10-06 2011-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for gate height control in a gate last process
KR20110012458A (en) * 2009-07-30 2011-02-09 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050040579A (en) * 2003-10-29 2005-05-03 주식회사 하이닉스반도체 Method for fabricating semiconductor devcie having tungsten poly metal gate-electrode
KR20080002487A (en) * 2006-06-30 2008-01-04 주식회사 하이닉스반도체 Method for forming landing plug of semiconductor device
CN101217106A (en) * 2007-01-04 2008-07-09 海力士半导体有限公司 Method for fabricating semiconductor device
CN106206687A (en) * 2015-05-29 2016-12-07 台湾积体电路制造股份有限公司 The structure of semiconductor device structure and forming method

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