TWI518743B - Method for fabricating patterned structure of semiconductor device - Google Patents

Description

Semiconductor device patterned structure manufacturing method

This invention relates to the field of patterned structures, and more particularly to a method of fabricating a patterned structure for a semiconductor device.

An integrated circuit (IC) is constructed in such a manner as to form patterned features in a substrate or in different layers to form a component device and an interconnect structure. In the production process of IC, photolithography is an indispensable technology, which is mainly to form the designed pattern on one or more masks, and then by exposure and development. The development step transfers the pattern on the reticle to the photoresist layer on a film layer. Complicated IC structures can be completed with subsequent semiconductor processing steps such as etching processes, ion implantation processes, and deposition processes.

With the continued miniaturization of semiconductor components and advances in semiconductor fabrication technology, double patterning technology (DPT) is often used in the industry as a main linewidth technology of 32 nanometers (nm) and 22 nm. A common double patterning technique involves a photolithography-etch-photolithography-etch (2P2E) approach. For example, in a 2P2E process, an etch stop layer is first overlaid on a target layer, such as a polysilicon layer, to define the area where the pattern is to be formed. A plurality of strip-shaped target layer patterns parallel to each other are then formed by the first lithography-etching. Finally, a second lithography-etch is used to break the individual strip target layer patterns. However, through this 2P2E process, there are still many shortcomings. For example, there may still be an incompletely etched target layer (or polysilicon) between the strip target layer patterns, or the etch barrier layer may not completely cover each strip target layer pattern (or strip polysilicon pattern) The strip target layer pattern is exposed, which is not conducive to the subsequent process. For example, in a subsequent epitaxial growth process, the epitaxial structure may grow on the polysilicon remaining or exposed to the etch barrier, resulting in a decrease in process yield.

Therefore, in order to overcome many of the shortcomings in the prior art and to improve process yield, it is necessary to propose an improved patterning technique to obtain the desired patterned structure.

It is an object of the present invention to provide a method of fabricating a patterned structure that solves the problems of the prior art that the target layer remains or cannot be completely shielded.

According to a preferred embodiment of the present invention, a method of fabricating a patterned structure of a semiconductor device is provided, which includes the following steps. First, a target layer, a first mask layer and a first patterned mask layer are sequentially formed on a substrate. Then performing a first etching process, using the first patterned mask layer as an etch mask, removing the first mask layer and a portion of the target layer to form a plurality of features on the substrate, wherein each feature structure includes a The first mask and a patterned target layer are patterned. A second patterned mask is then formed over the substrate that covers a portion of the features and exposes a predetermined area. Following a second etching process, the features in the predetermined area are completely removed to form a first trench in the predetermined area. Finally, a third etching process is performed to completely remove the target layer that is not masked by the patterned first mask layer by patterning the first mask layer as an etch mask.

Therefore, the present invention separately removes a portion of the target layer exposed to the mask layer by using a first etching process and a third etching process, and then completely removes the target layer not masked by the patterned first mask layer. . Therefore, the target layer is no longer left between the various features, and the problem that the feature structure is exposed to the upper mask layer is not generated, so that the process yield can be greatly improved.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to FIG. 1. FIG. 1 is a flow chart showing a method for fabricating a patterned structure of a semiconductor device according to a preferred embodiment of the double patterning technique (DPT) of the present invention. The flow of the present invention is as follows: First, starting from step S1, at least one target layer, a first mask layer and a first patterned mask layer are sequentially formed on a substrate by using step S2. Next, in step S3, a plurality of features are formed on the substrate by a first etching process, wherein each feature structure includes a patterned first mask and a patterned target layer. Then, step S4 is performed to form a second patterned mask covering most of the features and exposing features in a predetermined area. Following step S5, a plurality of features and a second patterned mask in the predetermined area are completely removed by a second etching process. Finally, in step S6, a third etching process is performed, and the patterned first mask layer is used as an etch mask to completely remove the target layer not masked by the patterned first mask layer. Thereafter, step S7 and subsequent processes can be performed.

The following is a further explanation of the gate pattern for the double patterning (DPT) process described above. Please refer to FIG. 2 to FIG. 6 and with reference to FIG. 1 , wherein FIG. 2 to FIG. 6 are schematic diagrams showing a patterned structure of a semiconductor device according to a preferred embodiment of the present invention. First, as shown in Fig. 2, a substrate 1 is provided which comprises a substrate 2 and an insulating layer 3 thereon. Then, a target layer 5, a first mask layer 7 and a first patterned mask layer 19 are sequentially formed on the substrate 1. The insulating layer 3 comprises cerium oxide or a high dielectric constant material or the like, which can be subjected to thermal oxidation, high density plasma CVD (HDPCVD) or sub-atmospheric chemical vapor deposition ( Sub atmosphere CVD, SACVD) and other processes are produced. In addition, the substrate 2 may comprise a semiconductor substrate such as a germanium substrate, a germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or the like. The target layer 5 may be a single crystal germanium layer, a polycrystalline germanium layer or an amorphous germanium layer. In the present embodiment, the target layer 5 is preferably a polycrystalline germanium layer. In addition, the first mask layer 7 may be a single layer or a multilayer structure. In the embodiment, the first mask layer 7 is a two-layer structure including tantalum nitride 7a and yttrium oxide 7b, but is not limited thereto. The first patterned mask layer 19 is sequentially stacked with an amorphous carbon layer 11 from bottom to top, such as an advanced patterning film (APF), and an anti-reflective layer 13, such as a dielectric material layer. (yttria, tantalum nitride, niobium oxynitride or a combination thereof); and a photoresist layer 15. In this embodiment, the pattern structure of the photoresist layer 15 in the mask layer 19 is patterned to define the position of the subsequent feature structure. It should be noted here that since the amorphous carbon layer 11 described above has good high aspect ratio (HAR), low edge line roughness (LER) and ashability (PR-like) Ashability), so it is often used in processes with line widths less than 60 nm. However, the first patterned mask layer 19 is not limited to the above-described constituent structure, and may also be a three-layer structure including a lower layer photoresist/antireflection layer/upper layer photoresist, such as an i-line photoresist/SHB layer/193. The structure of the PR, wherein the SHB layer is an abbreviation of a silicon-containing hard-mask bottom anti-reflection coating (SHB) layer. In addition, in the present embodiment, the target layer 5 preferably has a first thickness T1 of 600 angstroms to 1000 angstroms, but is not limited thereto. The thickness T3 of the first mask layer 7 is preferably thinner than the first thickness T1 of the target layer 5.

Next, reference is made to the third (A) and third (B) drawings. FIG. 3(A) is a top plan view showing a plurality of characteristic structures formed on the substrate after the first etching process is completed, and FIG. 3(B) is corresponding to the 3 (A) drawing along the line AA'. Schematic diagram of the structure. After the above structure is completed, a first etching process 21 is performed by using the photoresist layer 15 in the first patterned mask layer 19 as an etch mask to remove a portion of the anti-reflective layer 13 and a portion of the amorphous carbon. The layer 11, a portion of the first mask layer 7 and a portion of the target layer 5. The first etching process 21 may include a single etching recipe or a plurality of etching programs. In the embodiment, the first etching process 21 has only a single etching process, such as a main etch recipe (ME). . According to a preferred embodiment of the present invention, the etching gas system used is a mixed gas containing at least a tetrafluoromethane (CF ₄ ) gas, a hydrogen-containing fluorocarbon gas such as trifluoromethane. , CHF ₃ ) or an inert gas such as nitrogen or argon, but is not limited thereto. After the first etching process 21 described above is completed, a plurality of features 30 are formed on the substrate 1, which comprise a strip structure or a columnar structure, preferably a strip structure. Each feature structure 30 includes a patterned first mask 7' (including patterned tantalum nitride 7'a and patterned germanium oxide 7'b) and a patterned target layer 23, and the first pattern is covered by the first pattern. The cover layer 19 is covered. At this time, the first patterned mask layer 19 ′ includes the amorphous carbon layer 11 ′, the anti-reflective layer 13 ′ and the photoresist layer 15 in principle, but the first patterned mask layer is formed after the etching is completed depending on the etching conditions. It is also possible that only the amorphous carbon layer 11' remains, and the anti-reflection layer 13' and the photoresist layer 15 have been consumed.

It should be noted that, in the present invention, the first etching process 21 only etches a portion of the target layer 5 downward to a predetermined depth H1, but does not etch through the target layer 5, nor exposes the insulating layer 3. In other words, since the first etching process 21 etches only a portion of the target layer 5 exposed to the photoresist layer 15, the patterned target layer 23 in each feature 30 has a first height H1, and preferably The ratio of the first height H1 to the first thickness T1 of the target layer 5 may be less than one third. One feature of the present invention is that the first etching process 21 is used to remove a portion of the target layer 5 exposed to the photoresist layer 15 to a first predetermined depth H1, thereby avoiding patterning the first mask 7' in a subsequent etching process. The middle is over-etched.

After removing the remaining first patterned mask layer 19. Next, as shown in Fig. 4(A) and Fig. 4(B). Fig. 4(A) is a plan view showing a second patterned mask formed on the substrate, and Fig. 4(B) is a schematic view corresponding to a line taken along line BB' of Fig. 4(A). A second patterned mask 47 is formed on the substrate 1. In the embodiment, the second patterned mask 47 comprises a three-layer structure of a lower photoresist 41 / an anti-reflective layer 43 / an upper photoresist 45, for example, i -line PR/SHB layer / 193 PR structure. The following is an example of the structure of the i-line PR/SHB layer/193 PR as follows: First, a lower photoresist 41, such as i-line PR, is coated on the feature structure 30 by a general photoresist coating process. And filling the gap between each feature structure 30, and then optionally baking and curing. Next, an anti-reflection layer 43, such as an SHB layer, is formed, which is composed of an organosilicon polymer or a polysilane having at least one chromophore group and one cross. A crosslinkable group and a crosslinking agent enable the SHB layer to produce a cross-linking reaction after illumination. Finally, an upper layer of photoresist 45, such as 193 PR or ArF PR, is applied over the SHB layer. Since the primary function of the upper photoresist 45 is as a dry etching mask to transfer its pattern to the anti-reflective layer 43 below, its thickness does not need to be too thick. It should be noted here that in the present embodiment, the upper photoresist 45 of the second patterned mask 47 covers most of the features 30 and exposes the features 30 located within the predetermined region 49. Referring to FIG. 4(A), the predetermined regions 49 are distributed on the substrate 1 in a certain repeating unit array such that a portion of each of the characteristic patterns 30 is not covered by the upper photoresist 45.

Subsequently, reference is made to Figures 5(A) and 5(B). Figure 5(A) shows a top view of the feature structure in the predetermined area after the second etching process is completed, and Figure 5(B) corresponds to the line along the CC' of the 5(A) figure. Schematic. As shown in FIG. 5(A), a second etching process 51 is performed to completely remove the features 30 and a portion of the second patterned mask 47 in the predetermined region 49. The detailed steps are described as follows: First, an anti-reflective layer 43 and an underlying photoresist 41 exposed to the upper photoresist 45 are etched by an etching process until the feature 30 is quickly exposed. Then, using another etching process, the remaining underlying photoresist 41 and the exposed features 30 are simultaneously etched. Preferably, the etch rate ratio of the features 30 and the lower photoresist 41 is about 1.5 to 0.7, and It is preferably 1. Through the etching process described above, a first trench 53 having a flat bottom surface 55 is formed in the predetermined region 49. The second etching process 51 is a dry etching process comprising two etching programs. According to a preferred embodiment of the present invention, the etching gas used includes at least a tetrafluoromethane (CF ₄ ) gas. A hydrogen-containing fluorocarbon gas such as trifluoromethane (CHF ₃ ) or an inert gas such as nitrogen or argon, but is not limited thereto. According to other embodiments, the second etching process 51 may include two or more etching programs, but is not limited thereto. It should be noted that, in the present invention, the second etching process 51 etches only the features 30 to a second predetermined depth H2 in the predetermined region 49, but does not etch through the target layer 5, nor exposes the underlying insulating layer. 3. Preferably, the second predetermined depth H2 is less than or equal to one third of the first thickness T1. Therefore, after the second etching process 51 is completed, the target layer 5 in the predetermined region 49 will still have a second thickness T2. Preferably, the second thickness T2 is greater than 500 angstroms thick, and the first mask 7' is patterned. The thickness T3 is not reduced by the first etching process 21 and the second etching process 51.

After removing the remaining second patterned mask 47 (depending on the etching conditions, after the above etching is completed, the second patterned mask 47 may only have a portion of the underlying photoresist, and the anti-reflective layer and the upper photoresist have Exhausted.) Refer to Figures 6(A) and 6(B). Figure 6(A) shows a top view of the target layer in the predetermined area after the third etching process is completed, and Figure 6(B) corresponds to the line of DD' corresponding to the 6(A) figure. Schematic. Finally, a third etching process 61 is performed to completely remove the target layer 5 that is not shielded by the patterned first mask layer 7' by using the patterned first mask layer 7' as an etch mask, especially this The three etching process completely removes the target layer 5 in the predetermined region 49, and forms a plurality of broken features 30 on the substrate 1 and exposes the insulating layer 3 in the substrate 1. The third etching process 61 can also include various etching programs, such as a main etch recipe, a soft landing recipe, and an over etch recipe, but is not limited thereto. Among them, the soft landing etching program and the overetching program have a larger etching selectivity ratio to the target layer 5 than the main etching program, so that the insulating layer 3 is not over-etched and pitting is performed, thus ensuring The quality of the surface of the substrate 1 and the insulating layer 3 used as the gate oxide layer. Thus far, the process of the patterned structure of the present invention is completed. Before the third etching process 61 is performed, the present invention first etches a portion of the target layer 5 by the first etching process 21 and the second etching process 51, but does not etch through the target layer 5 to shorten the subsequent third etching process 61. The execution time, so the target layer 5 is not over-etched. Moreover, in the process of defining the secondary exposure and the second etching (the first etching process 21 and the second etching process 51) of the feature structure 30 and the predetermined region 49, the patterned first mask layers 7' are respectively patterned by the first patterning. The mask layer 19 is protected by the second patterned mask 47, so that the patterned first mask layer 7' is not over-etched in the comprehensive third etching process 61, and the complete contour shape can be maintained. Pattern transfer to the target layer 5. Compared with the conventional 2P2E double patterning technique, the width W of each patterned first mask layer 7' of the present invention is substantially equal to the width W of each of the patterned target layer 23, so that each patterned target layer 23 The upper surface is completely covered. In addition, since a portion of the target layer 5 has been etched away in the first etching process 21, the target layer 5 does not remain in the predetermined region 49 after the third etching process 61. As shown in Fig. 6(A), if subsequent sidewall deposition, active region 63 doping, epitaxial growth process, such as selective epitaxial growth (SEG) and etching, etc., The characteristic structure 30 of the invention can be used as a strip gate structure for controlling the switch of the carrier channel, and during the epitaxial growth process, there is no residual or exposed pattern of the patterned first mask layer 7'. The target layer 23 can be grown for a single crystal structure.

In summary, the present invention utilizes a first etching process 21 and a third etching process 61 to remove a portion of the target layer 5 exposed to the photoresist layer 15 and then completely remove the target layer in the predetermined region 49. 5. Therefore, the target layer 5 is no longer left between the features 30, and there is no doubt that the patterned target layer 23 is exposed to the patterned first mask 7'. Therefore, in the subsequent epitaxial growth process, the defect structure such as single crystal bump or single crystal protrusion is not generated on the feature structure 30, so that the process yield can be greatly improved. In addition, although the above embodiment is applied to the gate pattern by a double patterning (DPT) process, the present invention can also be applied to various high density and accumulation patterning processes, such as a fin gate. Semiconductor processes such as fin structures, contact holes, via holes, and the like.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1‧‧‧Substrate

2‧‧‧Base

3‧‧‧Insulation

5‧‧‧Target layer

7‧‧‧First mask layer

7a‧‧‧ nitride

7b‧‧‧Oxide

7’‧‧‧ patterned first mask

11‧‧‧Amorphous carbon layer

11'‧‧‧Amorphous carbon layer

13‧‧‧Anti-reflective layer

15‧‧‧ photoresist layer

19‧‧‧First patterned mask layer

19’‧‧‧First patterned mask layer

21‧‧‧First etching process

23‧‧‧ patterned target layer

30‧‧‧Characteristic structure

41‧‧‧lower photoresist

43‧‧‧Anti-reflective layer

45‧‧‧Upper photoresist

47‧‧‧Second patterned mask

49‧‧‧Predetermined area

51‧‧‧Second etching process

53‧‧‧First ditches

55‧‧‧flat bottom surface

61‧‧‧ Third etching process

63‧‧‧Active area

W‧‧‧Width

H1‧‧‧ first height

H2‧‧‧second predetermined depth

T1‧‧‧first thickness

T2‧‧‧second thickness

T3‧‧‧ thickness

S1‧‧‧ steps

S2‧‧‧ steps

S3‧‧‧ steps

S4‧‧‧ steps

S5‧‧ steps

S6‧‧ steps

S7‧‧ steps

AA’‧‧‧ Thread

BB’‧‧‧ cut line

CC’‧‧‧ cut line

DD’‧‧‧ cut line

13’‧‧‧Anti-reflective layer

7’a‧‧‧ patterned tantalum nitride

7’b‧‧‧ patterned cerium oxide

1 is a flow chart of a method of fabricating a patterned structure of a semiconductor device in accordance with a preferred embodiment of the present invention.

2 to 6 are schematic views showing a patterned structure of a semiconductor device according to a preferred embodiment of the present invention, wherein: FIG. 2 is a view showing a target layer, a first mask layer, and a substrate; A schematic diagram of a first patterned mask layer; FIGS. 3(A) and 3(B) are schematic diagrams showing a plurality of characteristic structures formed on a substrate after the first etching process is completed; 4th (A) FIG. 4 and FIG. 4B are schematic views showing a second patterned mask formed on the substrate; FIGS. 5(A) and 5(B) are diagrams showing the second etching process after the second etching process is completed. A schematic diagram in which the feature structure in the predetermined area is completely removed; and FIG. 6(A) and FIG. 6(B) are schematic views showing that the target layer in the predetermined region is completely removed after the third etching process is completed.

1‧‧‧Substrate

2‧‧‧Base

3‧‧‧Insulation

5‧‧‧Target layer

7’‧‧‧ patterned first mask

11'‧‧‧Amorphous carbon layer

13’‧‧‧Anti-reflective layer

15‧‧‧ photoresist layer

19’‧‧‧First patterned mask layer

21‧‧‧First etching process

23‧‧‧ patterned target layer

30‧‧‧Characteristic structure

H1‧‧‧ first height

T1‧‧‧first thickness

7’a‧‧‧ patterned tantalum nitride

7’b‧‧‧ patterned cerium oxide

Claims (17)

A method for fabricating a patterned structure of a semiconductor device, comprising: sequentially forming a target layer, a first mask layer, and a first patterned mask layer on a substrate; performing a first etching process, using the first a patterned mask layer is used as an etch mask to remove a portion of the first mask layer and a portion of the target layer to form a plurality of features on the substrate, wherein each of the features includes a patterned first mask a mask and a patterned target layer; forming a second patterned mask on the substrate, the second patterned mask covering a portion of the features and exposing a predetermined area; performing a second etching process to completely remove The plurality of features in the predetermined area to form a first trench in the predetermined region; and after forming the first trench, performing a third etching process, using the patterned first mask layer as an etch The mask completely removes the target layer that is not obscured by the patterned first mask layers. The method of claim 1, wherein the target layer comprises a single crystal germanium layer, a poly germanium layer or an amorphous germanium layer. The manufacturing method of claim 1, wherein the characteristic structures comprise a strip structure or a columnar structure. The manufacturing method of claim 1, wherein the first patterned mask layer or the second patterned mask layer comprises a multi-layer stack structure. The manufacturing method of claim 4, wherein the first patterned mask layer comprises an amorphous patterning film (APF), an anti-reflective layer and a photoresist layer. The manufacturing method of claim 4, wherein the second patterned mask layer comprises a lower photoresist layer, a germanium-containing anti-reflective layer and an upper photoresist layer. The manufacturing method of claim 1, wherein the first etching process etches a portion of the target layer downward to a first predetermined depth without etching through the target layer. The manufacturing method of claim 7, wherein the first predetermined depth is less than or equal to a thickness of one third of the target layer. The manufacturing method of claim 8, wherein the target layer has a thickness ranging from 600 angstroms to 1000 angstroms. The manufacturing method of claim 1, wherein the second patterned mask is provided between each of the features. The manufacturing method of claim 1, wherein before the forming the second patterned mask, the first patterned mask layer is completely removed. The manufacturing method of claim 1, wherein the second etching process etches a portion of the target layer downward to a second predetermined depth without etching through the target layer. The manufacturing method of claim 12, wherein the second predetermined depth is less than or equal to a thickness of one third of the target layer. The manufacturing method of claim 1, wherein the first trench has a flat bottom. The manufacturing method of claim 1, wherein the third etching process completely removes the target layer in the predetermined region. The manufacturing method of claim 1, wherein after the third etching process is completed, the method further comprises: performing an epitaxial growth process to form a single crystal structure, wherein the single crystal structure does not contact each of the patterns The target layer. The manufacturing method of claim 1, wherein the substrate further has an insulating layer disposed between the target layer and the substrate, and the third etching process etches through the target layer to expose the insulating layer. Floor.