CN104064474A - Method for manufacturing fin structure of double patterning fin-type transistor - Google Patents
Method for manufacturing fin structure of double patterning fin-type transistor Download PDFInfo
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- CN104064474A CN104064474A CN201410339109.8A CN201410339109A CN104064474A CN 104064474 A CN104064474 A CN 104064474A CN 201410339109 A CN201410339109 A CN 201410339109A CN 104064474 A CN104064474 A CN 104064474A
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000059 patterning Methods 0.000 title abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 93
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 58
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910003481 amorphous carbon Inorganic materials 0.000 claims abstract description 53
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 44
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 44
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 46
- 229910052757 nitrogen Inorganic materials 0.000 claims description 23
- 238000001312 dry etching Methods 0.000 claims description 21
- 230000009977 dual effect Effects 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 10
- 238000003384 imaging method Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000004528 spin coating Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 239000003595 mist Substances 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 151
- 239000012792 core layer Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The invention discloses a method for manufacturing a fin structure of a double patterning fin-type transistor. A second silicon nitride layer is protected by depositing silicon dioxide, then thickness losses of the second silicon nitride layer cannot be caused when a nitrogen-free anti-reflecting layer at the top of a second amorphous carbon layer is removed, the morphology and key size control problems caused by the existing method are solved, a follow-up patterning process window is accordingly enlarged, control over the key size and the morphology of the fin structure is facilitated, and electrical property indexes of the device are improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process technology field, relate in particular to a kind of manufacture method of utilizing the fin structure of side wall autoregistration Dual graphing fin transistor.
Background technology
According to international semiconductor technology path development blueprint, predict, in order to follow Moore's Law and to obtain required short-channel effect, improve the control to raceway groove of grid, new transistor arrangement has been proposed, it is fin formula field effect transistor FinFET (FinField Effect Transistor is called for short fin transistor).The formation of its active area fin is one and has challenging technique, because at 22nm and following fin formula field effect transistor, the width of fin is about 10～15nm left and right, so little dimension of picture has exceeded the resolution limit of current immersed photoetching machine, for this reason, need to adopt side wall self-alignment type Dual graphing technology to realize.First depositing on the silicon chip of various mask materials, utilize liquid immersion lithography and lithographic technique to produce the core graphic (sacrificial core pattern) of a sacrifice, then on this core graphic, utilize technique for atomic layer deposition, deposition one deck spacer material, then utilize anisotropic dry etch to form side wall, afterwards the core graphic of sacrificing is removed, so just formed fin (FIN) mask graph that needed pitch (pitch) reduces by half, here the width of the hard mask of FIN is to be determined by the thickness of atomic deposition layer, utilize afterwards this hard mask graph for the fin (FIN) of protective layer continuation etching formation fin formula field effect transistor.
Figure 1A to Fig. 1 H is the formation method of existing employing side wall autoregistration double-pattern fin.Particularly:
First, as shown in Figure 1A, on the silicon substrate 101 of a semiconductor active device, deposit silicon dioxide insulating layer 102, silicon nitride layer 103, ground floor amorphous carbon layer 104, silicon nitride etch stop layer 105, second layer amorphous carbon layer 106 and without nitrogen anti-reflecting layer 107 successively from bottom to top.Wherein, silicon nitride layer 103 is etch hardmasks that final fin structure forms.
Then, as shown in Figure 1B, at 107 layers of spun on top organic antireflection layer 108 and photoresist 109, then carry out core layer (core layer) photoetching.
Then, as shown in Figure 1 C, utilize photoresist 109 as mask dry etching, to form the sacrifice core layer line bar figure of the second amorphous carbon layer 106, so far formed amorphous carbon sacrifice core graphic and top thereof without nitrogen anti-reflecting layer 107.The amorphous carbon herein forming is sacrificed core pattern line because process technology limit can not form vertical sidewall pattern completely, and may produce near the second amorphous carbon layer 106 places, top in this figure the damage causing because of etching; This damage can cause follow-up sidewall to isolate hard mask near the pattern variation of amorphous carbon one side, thereby affects follow-up graphical definition.
After corresponding cleaning, as shown in Fig. 1 D, amorphous carbon sacrifice core graphic and without nitrogen anti-reflecting layer 107 above deposit one deck silicon oxide film hard mask layer 110.
As shown in Fig. 1 E, utilize this silicon oxide film hard mask layer of anisotropic dry etch, and stop at silicon nitride etch and stop layer 105 top to form monox lateral wall 110.
Afterwards, as shown in Fig. 1 F, utilize plasma dry etch process remove to sacrifice core layer line bar figure top without nitrogen anti-reflecting layer 107, make to come out without the sacrifice core layer amorphous carbon of nitrogen anti-reflecting layer 107 belows.In this step, in removing without nitrogen anti-reflecting layer 107 processes, because etching stop layer 105a is also exposed in plasma, make etching stop layer 105a have loss in this step.
As shown in Figure 1 G, with dry method degumming process, remove and sacrifice core layer, the etching stop layer 105b of its below is come out.Now, etching stop layer 105a and 105b are because the asynchronism(-nization) being exposed in plasma causes both thickness also not identical, the film thickness at etching stop layer 105a place continues attenuate, and the film thickness at etching stop layer 105b place still remains unchanged, both further amplify at difference in thickness, can cause utilizing the hard mask lines of monox lateral wall 110 to carry out after figure transmission, the further amplification of the inside and outside pattern difference of final side wall.
As shown in Fig. 1 H, continuing to utilize dry etching to take the hard mask of silicon dioxide side wall 110 is mask, the silicon nitride etch of removing its below stops the silicon nitride layer 103 of layer the 105, first amorphous carbon layer 104 and bottommost, form silicon nitride hard mask 113 bargraphss that pitch reduces by half, and etching stopping is in silicon dioxide insulating layer 102 tops.
After completing necessary wet clean process, as shown in Figure 1 I, carry out fin line top and cut off photoetching process, i.e. spin coating photoetching flatness layer 114, photoetching anti-reflecting layer 115 and photoresist layer 116 above silicon nitride hard mask 113, and exposure, developing to form needs the figure that cuts off.
As shown in Fig. 1 J, utilize dry etch process to take photoresist 116, photoetching anti-reflecting layer 115 and flatness layer 114 and be that mask is removed and need the silicon nitride lines that cut off, and etching stopping is on silicon dioxide insulating layer 102.Utilize afterwards dry method degumming process to remove the hard mask of amorphous carbon of silicon nitride hard mask 113 tops, 113 layers of silicon nitride hard mask are come out completely.
Afterwards, as shown in Fig. 1 K and Fig. 1 L, utilize silicon nitride hard mask 113 as hard mask, etching silicon dioxide insulating barrier 102 and silicon substrate 101 are to form fin structure 117.
In sum, in the method for existing formation fin structure, there is following defect:
1. in sacrificing core graphic APF etching process, core layer figure is difficult to form the very high lines (approaching 90 degree) of perpendicularity, because if core layer pattern side wall perpendicularity not directly can make the madial wall of the hard mask of follow-up side wall form the angle (being less than 90 degree) of an inclination along this core layer sidewall shape, in side wall inner side, form the sidewall pattern of an inverted trapezoidal simultaneously, this can cause in follow-up figure transmission, affect the control of the pattern of subsequent diagram and the critical size of subsequent diagram, as the silicon nitride hard mask lines of Fig. 1 H medium dip.And fin shape and critical size are most important for the definition of the electric property of fin formula field effect transistor.
2. after completing monox lateral wall dry etching, need to remove this and sacrifice core layer pattern, and generally this sacrifices core layer top due to patterned needs, at its top, there is one deck without nitrogen anti-reflecting layer (NFDARC), therefore, for remove sacrifice core layer APF need to first remove its top without nitrogen anti-reflecting layer, can not produce any negative effect to the hard mask graph of the side wall having produced, and the substrate film having come out is produced to minimum damage simultaneously; If directly applying an over etching (OE) after side wall dry etch step removes without nitrogen anti-reflecting layer, can cause the loss of the outer side-lower medium of side wall, after causing core layer to be removed, the thickness of the position that the thickness of the dielectric substrate material of below, core layer origin-location was not originally covered by core layer much larger than side wall outer lower side, therefore, when usining when side wall down carries out figure transmission as mask, can cause pattern and critical size control problem, also may be damaged to the height of side wall pattern or side wall simultaneously.
Summary of the invention
The object of the invention is to make up above-mentioned the deficiencies in the prior art, a kind of fin structure manufacture method of Dual graphing fin transistor is provided, to avoid the loss of etching stop layer when removing without nitrogen anti-reflecting layer, and reduce owing to sacrificing the impact of core layer sidewall slope on subsequent diagram, thereby control pattern and the critical size of fin structure, improve the electric property index of device.
For achieving the above object, the invention provides a kind of fin structure manufacture method of Dual graphing fin transistor, it comprises the following steps:
Step S01, provides semiconductor device substrate, and on this substrate deposit the first silicon dioxide layer, the first silicon nitride layer, the first amorphous carbon layer, the second silicon nitride layer, the second amorphous carbon layer and anti-reflecting layer successively from bottom to top;
Step S02 is coated with photoresist on top layer anti-reflecting layer, by exposure imaging technique, completes core sacrifice layer figure lithography step;
Step S03, take photoresist as mask etching anti-reflecting layer and the second amorphous carbon layer, forms the core sacrifice layer figure with the second amorphous carbon layer and top anti-reflective layer thereof;
Step S04, deposit one deck the second silicon dioxide layer above this core sacrifice layer figure;
Step S05, etching is removed second silicon dioxide layer at this core sacrifice layer figure top, to expose this anti-reflecting layer, and the second silicon dioxide layer of reservation core sacrifice layer figure both sides;
Step S06, etching is removed the anti-reflecting layer at this core sacrifice layer figure top;
Step S07, etching is removed this second silicon dioxide layer;
Step S08, deposit one deck the 3rd silicon dioxide layer above this core sacrifice layer figure;
Step S09, utilizes anisotropic etching the 3rd silicon dioxide layer, exposes the second amorphous carbon layer in core sacrifice layer figure, forms the silicon dioxide side wall of core sacrifice layer figure, afterwards, removes the second amorphous carbon layer in core sacrifice layer figure;
Step S10, take this silicon dioxide side wall as mask etching this this second silicon nitride layer, the first amorphous carbon layer and the first silicon nitride layer, and forming bottom is the hard mask lines of silicon nitride, and removes the amorphous carbon of silicon nitride top in these hard mask lines;
Step S11, the silicon nitride lines of take in these hard mask lines are mask etching this first silicon dioxide layer and substrate, form fin structure.
Further, step S03 is dry etching, step S05 is for utilizing the reverse etching of plasma dry (etch back), step S06 is dry etching, step S07 is wet etching, in step S09, form silicon dioxide side wall for utilizing anisotropic plasma dry etching, in step S09, removing the second amorphous carbon layer in core sacrifice layer figure is degumming process, in step S10, form hard mask lines for utilizing anisotropic plasma dry etching, in step S10, removing silicon nitride top amorphous carbon in the second hard mask lines is degumming process, step S11 is dry etching.
Further, step S06 also comprises over etching, to remove part second amorphous carbon layer of anti-reflecting layer below.
Further, this anti-reflecting layer comprises that lower floor is without nitrogen anti-reflecting layer and upper strata anti-reflecting layer.
Further, step S04 is spin coating the second silicon dioxide layer.
Further, the etching gas medium of step S05 is CF
4, or CF
4mist with Ar.
Further, this CF
4flow be 50sccm～200sccm, the flow of this Ar is 50sccm～300sccm, radio frequency source power is 200 watts～700 watts, substrate bias power is 50 volts～400 volts, air pressure is 5 millitorr～12 millitorrs.
Further, in step S10, the silicon nitride lines pitch in hard mask lines reduces by half.
Further, between step S10 and S11, also comprise, step S101 is coated with successively carbon hard mask layer, siliceous anti-reflecting layer and photoresist on these silicon nitride lines, by exposure imaging technique, produces the figure that will cut off on photoresist; Step S102, utilizes dry etching to remove the silicon nitride lines that need cut-out, and utilizes dry method degumming process to remove the amorphous carbon of remaining silicon nitride lines top, exposes silicon nitride lines.
Further, this anti-reflecting layer is without nitrogen anti-reflecting layer.
The fin structure manufacture method of Dual graphing fin transistor provided by the invention; owing to having utilized deposit silicon dioxide, protect the second silicon nitride layer; make can not cause the thickness loss of the second silicon nitride layer when removing the second amorphous carbon layer top without nitrogen anti-reflecting layer; pattern and the critical size control problem of having avoided existing method to produce; thereby expanded subsequent diagram metallization processes window; more be conducive to the control of critical size and the pattern of fin structure, realize the raising of device electric property index.
Accompanying drawing explanation
For can clearer understanding objects, features and advantages of the present invention, below with reference to accompanying drawing, preferred embodiment of the present invention is described in detail, wherein:
Figure 1A-Fig. 1 L is each step schematic diagram of existing double-pattern fin formation method;
Fig. 2 is the schematic flow sheet of the fin structure manufacture method of Dual graphing fin transistor of the present invention;
Fig. 3 A-Fig. 3 N is each step schematic diagram of manufacture method of the present invention.
Embodiment
Please refer to Fig. 2, Fig. 3 A to Fig. 3 N, the fin structure manufacture method of the Dual graphing fin transistor of the present embodiment, comprises the following steps:
Step S01, as shown in Figure 3A, semiconductor device substrate 201 is provided, and on this substrate 201 deposit the first silicon dioxide layer 202, the first silicon nitride layer 203, the first amorphous carbon layer 204, the second silicon nitride layer 205, the second amorphous carbon layer 206 and without nitrogen anti-reflecting layer 207 successively from bottom to top.
Step S02, as shown in Figure 3 B, top layer without nitrogen anti-reflecting layer 207 on deposit organic antireflection layer 208, and on organic antireflection layer 208, be coated with photoresist 209, by exposure imaging technique, on photoresist 209, produce the figure of core sacrifice layer to be prepared, complete core sacrifice layer figure lithography step.
Step S03, as shown in Figure 3 C, take photoresist 209 as mask etching organic antireflection layer 208, without nitrogen anti-reflecting layer 207 and the second amorphous carbon layer 206, and final formation has the second amorphous carbon layer 206 and top thereof without the core sacrifice layer figure of nitrogen anti-reflecting layer 207.
Wherein, this step is dry etching, can adopt this area conventional means, gas medium.
Step S04, as shown in Figure 3 D, spin coating one deck the second silicon dioxide layer 210 on core sacrifice layer figure.The thickness of this second silicon dioxide layer 210 take just over without nitrogen anti-reflecting layer 207 tops as good.
Step S05, as shown in Fig. 3 E, etching is removed second silicon dioxide layer 210 at core sacrifice layer figure top, to expose without nitrogen anti-reflecting layer 207, and the second silicon dioxide layer 210 of reservation core sacrifice layer figure both sides.
Wherein, this step is for utilizing the reverse etching of plasma dry, the preferred CF of etching gas
4, or CF
4with the mist of Ar, wherein, CF
4flow be 50sccm～200sccm, the flow of Ar is 50sccm～300sccm, radio frequency source power is 200 watts～700 watts, substrate bias power is 50 volts～400 volts, air pressure is 5 millitorr～12 millitorrs.
Step S06, as shown in Fig. 3 F, etching remove core sacrifice layer figure top without nitrogen anti-reflecting layer 207.
Wherein, this step is dry etching, can adopt this area conventional means, gas.Wherein, step S06 also preferably comprises over etching, to remove part second amorphous carbon layer of anti-reflecting layer below.Remove the damage layer that the second amorphous carbon layer part top causes because of etching, play the effect of adjusting the second amorphous carbon layer height, its top critical size is expanded, avoid, because perpendicularity causes the impact that its top critical size is too little not, being more conducive to the transmission of subsequent diagram.
Step S07, as shown in Fig. 3 G, etching is removed the second silicon dioxide layer 210 of spin coating.
Wherein, this step is wet etching, can adopt this area conventional means, medium.This step adopts wet etching to remove remaining spin coating silicon dioxide, can keep higher etching selection ratio, can not cause the loss of the second amorphous carbon layer 206 in core sacrifice layer figure and core sacrifice layer figure both sides the second silicon nitride layer 205, to guarantee pattern and the critical size of subsequent diagram.
Step S08, as shown in Fig. 3 H, deposit one deck the 3rd silicon dioxide layer 211 above core sacrifice layer figure.
Step S09, as shown in Fig. 3 I, utilize anisotropic etching the 3rd silicon dioxide layer 211, expose core sacrifice layer figure the second amorphous carbon layer 206, and form the silicon dioxide side wall 218 of core sacrifice layer figure, afterwards, remove the second amorphous carbon layer 206 in core sacrifice layer figure, namely whole core sacrifice layer figure is all removed.
Wherein, in this step, form silicon dioxide side wall for utilizing anisotropic plasma dry etching, can adopt this area conventional means, gas; Removing core sacrifice layer figure the second amorphous carbon layer is degumming process, can adopt this area conventional means, gas medium.
Step S10, as shown in Fig. 3 J, take silicon dioxide side wall 218 as mask etching the second silicon nitride layer 205, the first amorphous carbon layer 204 and the first silicon nitride layer 203, forming bottom is that silicon nitride, silicon nitride top are the hard mask lines of amorphous carbon, and removes the amorphous carbon of silicon nitride top in hard mask lines.
Wherein, in this step, form hard mask lines for utilizing anisotropic plasma dry etching, can adopt this area conventional means, gas; Removing silicon nitride top amorphous carbon in hard mask lines is degumming process, can adopt this area conventional means, gas.
Wherein, this step complete after silicon nitride lines pitch in the hard mask lines of formation reduce by half.
Step S11, as shown in Fig. 3 M, the silicon nitride lines of take in hard mask lines are mask etching the first silicon dioxide layer 202 and silicon substrate 201, form fin structure, two sidewalls, 216,217 symmetries of the silicon groove 215 of this fin structure, critical size is even.
Wherein, this step is dry etching, can adopt this area conventional means, gas.
In actual applications, need to carry out top Cutting process to fin line, between step S10 and S11, also comprise, step S101, as shown in Fig. 3 K, on silicon nitride lines, be coated with successively carbon hard mask layer 212, siliceous anti-reflecting layer 213 and photoresist 214, by exposure imaging technique, on photoresist 214, produce the figure that will cut off; Step S102, as shown in Fig. 3 L, utilizes dry etching to remove the silicon nitride lines that need cut-out, and utilizes dry method degumming process to remove the amorphous carbon of remaining silicon nitride lines top, exposes silicon nitride lines.The fin structure that final step S09 forms is as shown in Fig. 3 N.
Claims (9)
1. a fin structure manufacture method for Dual graphing fin transistor, is characterized in that, it comprises the following steps:
Step S01, provides semiconductor device substrate, and on this substrate deposit the first silicon dioxide layer, the first silicon nitride layer, the first amorphous carbon layer, the second silicon nitride layer, the second amorphous carbon layer and anti-reflecting layer successively from bottom to top;
Step S02 is coated with photoresist on top layer anti-reflecting layer, by exposure imaging technique, completes core sacrifice layer figure lithography step;
Step S03, take photoresist as mask etching anti-reflecting layer and the second amorphous carbon layer, forms the core sacrifice layer figure with the second amorphous carbon layer and top anti-reflective layer thereof;
Step S04, deposit one deck the second silicon dioxide layer above this core sacrifice layer figure;
Step S05, etching is removed second silicon dioxide layer at this core sacrifice layer figure top, to expose this without nitrogen anti-reflecting layer, and the second silicon dioxide layer of reservation core sacrifice layer figure both sides;
Step S06, etching is removed the anti-reflecting layer at this core sacrifice layer figure top;
Step S07, etching is removed this second silicon dioxide layer;
Step S08, deposit one deck the 3rd silicon dioxide layer above this core sacrifice layer figure;
Step S09, utilizes anisotropic etching the 3rd silicon dioxide layer, exposes the second amorphous carbon layer in core sacrifice layer figure, forms the silicon dioxide side wall of core sacrifice layer figure, afterwards, removes the second amorphous carbon layer in core sacrifice layer figure;
Step S10, take this silicon dioxide side wall as mask etching this this second silicon nitride layer, the first amorphous carbon layer and the first silicon nitride layer, and forming bottom is the hard mask lines of silicon nitride, and removes the amorphous carbon of silicon nitride top in these hard mask lines;
Step S11, the silicon nitride lines of take in these hard mask lines are mask etching this first silicon dioxide layer and substrate, form fin structure.
2. the fin structure manufacture method of Dual graphing fin transistor according to claim 1, it is characterized in that: step S03 is dry etching, step S05 is for utilizing the reverse etching of plasma dry, step S06 is dry etching, step S07 is wet etching, in step S09, form silicon dioxide side wall for utilizing anisotropic plasma dry etching, the second amorphous carbon layer of removing in step S09 in core sacrifice layer figure is degumming process, in step S10, form hard mask lines for utilizing anisotropic plasma dry etching, in step S10, removing silicon nitride top amorphous carbon in the second hard mask lines is degumming process, step S11 is dry etching.
3. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, is characterized in that: step S06 also comprises over etching, to remove part second amorphous carbon layer of anti-reflecting layer below.
4. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, it is characterized in that: this anti-reflecting layer comprises that lower floor is without nitrogen anti-reflecting layer and upper strata organic antireflection layer, and the core sacrifice layer figure top of step S03 is without nitrogen anti-reflecting layer.
5. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, is characterized in that: step S04 is spin coating the second silicon dioxide layer.
6. the fin structure manufacture method of Dual graphing fin transistor according to claim 2, is characterized in that: the etching gas medium of step S05 is CF
4, or CF
4mist with Ar.
7. the fin structure manufacture method of Dual graphing fin transistor according to claim 6, is characterized in that: this CF
4flow be 50sccm～200sccm, the flow of this Ar is 50sccm～300sccm, radio frequency source power is 200 watts～700 watts, substrate bias power is 50 volts～400 volts, air pressure is 5 millitorr～12 millitorrs.
8. the fin structure manufacture method of Dual graphing fin transistor according to claim 1, is characterized in that: the silicon nitride lines pitch in step S10 in hard mask lines reduces by half.
9. the fin structure manufacture method of Dual graphing fin transistor according to claim 1, it is characterized in that: between step S10 and S11, also comprise, step S101, on these silicon nitride lines, be coated with successively carbon hard mask layer, siliceous anti-reflecting layer and photoresist, by exposure imaging technique, on photoresist, produce the figure that will cut off; Step S102, utilizes dry etching to remove the silicon nitride lines that need cut-out, and utilizes dry method degumming process to remove the amorphous carbon of remaining silicon nitride lines top, exposes silicon nitride lines.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409444A (en) * | 2014-11-17 | 2015-03-11 | 上海集成电路研发中心有限公司 | Preparation method of fin layer photo-etching alignment mark |
| CN107785252A (en) * | 2016-08-26 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The method of Dual graphing |
| CN113363209A (en) * | 2020-05-22 | 2021-09-07 | 台湾积体电路制造股份有限公司 | Method of manufacturing semiconductor device and semiconductor device |
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| CN104409444A (en) * | 2014-11-17 | 2015-03-11 | 上海集成电路研发中心有限公司 | Preparation method of fin layer photo-etching alignment mark |
| CN104409444B (en) * | 2014-11-17 | 2018-01-02 | 上海集成电路研发中心有限公司 | The preparation method of fin layer photoetching alignment mark |
| CN107785252A (en) * | 2016-08-26 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The method of Dual graphing |
| CN113363209A (en) * | 2020-05-22 | 2021-09-07 | 台湾积体电路制造股份有限公司 | Method of manufacturing semiconductor device and semiconductor device |
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