CN107785252B - Double patterning method - Google Patents

Double patterning method Download PDF

Info

Publication number
CN107785252B
CN107785252B CN201610738863.8A CN201610738863A CN107785252B CN 107785252 B CN107785252 B CN 107785252B CN 201610738863 A CN201610738863 A CN 201610738863A CN 107785252 B CN107785252 B CN 107785252B
Authority
CN
China
Prior art keywords
layer
substrate
core layer
region
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610738863.8A
Other languages
Chinese (zh)
Other versions
CN107785252A (en
Inventor
王彦
张城龙
张海洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201610738863.8A priority Critical patent/CN107785252B/en
Publication of CN107785252A publication Critical patent/CN107785252A/en
Application granted granted Critical
Publication of CN107785252B publication Critical patent/CN107785252B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of double patterning, comprising: forming a sidewall layer on the top and sidewalls of the core layer and on the substrate of the second region; forming a sacrificial layer on the side wall layer of the second sub-area; carrying out planarization treatment on the top of the sacrificial layer and the top of the side wall layer to expose the top of the core layer; etching the sacrificial layer and the core layer by adopting a first etching process to enable the top of the residual core layer to be flush with the top of the residual sacrificial layer in the second subregion; etching and removing the residual core layer and the side wall layer positioned in the second subarea by adopting a second etching process to expose the first area substrate and the second subarea substrate; and etching the substrate by taking the side wall layer of the first sub-area as a mask to form a target pattern. The invention reduces the height difference of the surfaces of the residual substrates at the two sides of the target pattern and improves the quality of the formed target pattern.

Description

Double patterning method
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a double patterning method.
Background
Semiconductor technology continues to step toward smaller process nodes driven by moore's law. With the continuous progress of semiconductor technology, the functions of devices are becoming more powerful, but the difficulty of semiconductor manufacturing is increasing. The photolithography technique is the most critical production technique in the semiconductor manufacturing process, and with the continuous reduction of semiconductor process nodes, the existing light source photolithography technique cannot meet the requirements of semiconductor manufacturing, and the extreme ultraviolet lithography (EUV), the multi-beam maskless technique and the nanoimprint technique become the research hotspots of the next generation photolithography candidate technique. However, the above-mentioned next-generation lithography candidates still have inconveniences and drawbacks, and further improvement is needed.
While moore's law continues to make the forward extending step irreversible, Double-Patterning (DP) technology is certainly one of the best choices in the industry, and Double-Patterning technology can effectively fill the gap in lithography for smaller nodes and improve the minimum pitch (pitch) between adjacent semiconductor patterns with only minor modifications to the existing lithography infrastructure. The principle of the double patterning technique is to break a set of high density patterns into two separate sets of lower density patterns, which are then fabricated onto a wafer. The double patterning technology in the prior art mainly comprises the following steps: Self-Aligned Double Patterning (SADP: Self-Aligned Double-Patterning), Double lithography and etch process (LELE: Litho-Eth-Litho-Eth). Since the self-aligned double patterning process is simpler and lower in cost, the self-aligned double patterning process is often used in the process of forming a semiconductor device.
However, in the prior art, the substrate is etched by using a double patterning method, and the quality of a target pattern formed in the substrate after etching is poor, which affects the performance and yield of the formed semiconductor structure.
Disclosure of Invention
The invention provides a double patterning method, which improves the quality of a formed target pattern.
To solve the above problems, the present invention provides a double patterning method, comprising: providing a substrate, wherein the substrate comprises a first region and a second region which are sequentially arranged at intervals, the second region comprises first sub-regions which are adjacent to the adjacent first regions, and second sub-regions which are positioned between the adjacent first sub-regions, and a core layer is formed on the substrate of the first region; forming side wall layers on the top and the side walls of the core layer and on the substrate of a second area, wherein the side wall layer of the first sub-area is positioned on the side wall of the core layer, the top of the side wall layer of the second sub-area is lower than the top of the core layer, and the bottom of the side wall layer of the second sub-area is lower than the bottom of the core layer; forming a sacrificial layer on the side wall layer of the second subregion, wherein the top of the sacrificial layer is higher than the top of the core layer or is flush with the top of the core layer; carrying out planarization treatment on the top of the sacrificial layer and the top of the side wall layer, removing the sacrificial layer and the side wall layer which are higher than the top of the core layer, and exposing the top of the core layer; etching the sacrificial layer and the core layer by adopting a first etching process to enable the top of the residual core layer to be flush with the top of the residual sacrificial layer in the second subregion; etching and removing the residual core layer and the side wall layer positioned in the second subarea by adopting a second etching process to expose the first area substrate and the second subarea substrate; and etching the substrate by taking the side wall layer of the first sub-area as a mask to form a target pattern.
Optionally, in a direction parallel to the substrate surface, a width dimension of the first region is the same as a width dimension of the second sub-region.
Optionally, in the first etching process, the sacrificial layer with the whole thickness is removed by etching, so that the top of the remaining core layer is flush with the top of the second sub-region sidewall layer.
Optionally, in the first etching process, the sacrificial layer with a partial thickness is removed by etching, so that the top of the remaining core layer is flush with the top of the remaining sacrificial layer in the second sub-region.
Optionally, after the first etching process, the thickness of the remaining sacrificial layer in the second sub-region ranges from 100 angstroms to 200 angstroms.
Optionally, in the second etching process, before the side wall layer located in the second sub-region is etched and removed, the remaining sacrificial layer in the second sub-region is also etched and removed.
Optionally, before the first etching process is performed, the top of the sacrificial layer is flush with the top of the core layer; the thickness of the sacrificial layer etched and removed by the first etching process is equal to that of the core layer etched and removed.
Optionally, the etching rates of the sacrificial layer and the core layer by the first etching process are the same.
Optionally, the material of the sacrificial layer is the same as the material of the core layer.
Optionally, the material of the sacrificial layer is amorphous carbon, BARC material, ODL material or DARC material; the material of the core layer is amorphous carbon, BARC material, ODL material or DARC material.
Optionally, the material of the sidewall layer is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or silicon oxycarbonitride.
Optionally, after forming the core layer, the first regional substrate surface is higher than the second regional substrate surface; in the process of etching and removing the residual core layer, the second etching process also etches and removes the substrate with partial thickness in the first area, so that the substrate surface in the first area is flush with the substrate surface in the second sub-area after the second etching process.
Optionally, the second etching process has the same etching rate for the core layer, the sidewall layer and the substrate.
Optionally, the process of forming the core layer includes: forming a core film on the substrate; etching to remove the core film on the second regional substrate, and forming the core layer on the first regional substrate; and in the process of etching the core film on the substrate of the second area, the substrate of the second area is also over-etched.
Optionally, the over-etched thickness of the second area substrate is equal to the thickness of the first area substrate etched and removed by the second etching process.
Optionally, the method for determining the stop position for performing the planarization treatment on the top of the sacrificial layer and the top of the sidewall layer includes: until the top surface of the side wall layer of the first subregion is parallel to the surface of the substrate.
Optionally, the planarization process also removes a portion of the thickness of the core layer.
Optionally, the method for determining the stop position for performing the planarization treatment on the top of the sacrificial layer and the top of the sidewall layer includes: until the top surface of the core layer is exposed.
Optionally, the planarization method includes: carrying out a chemical mechanical polishing process on the sacrificial layer; and after the chemical mechanical grinding process, carrying out dry etching treatment on the sacrificial layer and the side wall layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme of the double patterning method, a core layer is formed on a first area substrate; side wall layers are formed on the top and the side walls of the core layer and on the substrate of the second area, the side wall layer of the first sub-area is positioned on the side wall of the core layer, and the top of the side wall layer of the second sub-area is lower than the top of the core layer; forming a sacrificial layer on the side wall layer of the second subregion, wherein the top of the sacrificial layer is higher than the top of the core layer or is flush with the top of the core layer; carrying out planarization treatment on the top of the sacrificial layer and the top of the side wall layer to expose the top of the core layer; then, etching the sacrificial layer and the core layer by adopting a first etching process to enable the top of the remaining core layer to be flush with the top of the remaining sacrificial layer of the second subregion, so that the top surfaces of the layers to be etched on the two sides of the side wall layer of the first subregion are flush after the first etching process; and then, etching and removing the residual core layer and the side wall layer positioned in the second sub-region by adopting a second etching process to expose the substrate of the first region and the substrate of the second sub-region, wherein the etching rate of the second etching process to the to-be-etched layers on the two sides of the first sub-region can be the same by adjusting the second etching process, so that the surface height difference of the residual substrate on the two sides of the first sub-region is smaller after the second etching process is finished, the surface height difference of the residual substrate on the two sides of the formed target pattern is smaller, and the quality of the formed target pattern is improved.
In an alternative scheme, in the direction parallel to the surface of the substrate, the width dimension of the first region is the same as the width dimension of the second sub-region, so that when the substrate is etched by using the side wall layers of the first sub-region as masks, the width dimensions between the side wall layers of the adjacent first sub-regions are the same, and the problem of etching load caused by different mask pattern densities is avoided.
In an alternative scheme, the first etching process etches and removes the sacrificial layer with partial thickness, so that the sacrificial layer is remained on the second sub-region side wall layer, the process controllability of the first etching process is high, the core layer is prevented from being over-etched by the first etching process, the top of the remaining core layer is enabled to be flush with the top of the remaining sacrificial layer, and the top of the remaining core layer is prevented from being lower than the top of the second sub-region side wall layer.
Optionally, over-etching the second region substrate during the process of forming the core layer to make the surface of the first region substrate higher than the surface of the second region substrate; correspondingly, the second etching process also etches and removes the substrate with partial thickness in the first area, so that the surface of the substrate in the first area is flush with the surface of the substrate in the second area after the second etching process, and the quality of the formed target pattern is further improved.
Drawings
FIGS. 1-5 are schematic cross-sectional views illustrating a process for forming a semiconductor structure by double patterning;
fig. 6 to 14 are schematic cross-sectional views illustrating a process of forming a semiconductor structure by using a double patterning method according to an embodiment of the invention.
Detailed Description
As known from the background art, in the prior art, a double patterning method is adopted to etch a substrate, and the quality of a pattern formed in the etched substrate is poor.
Fig. 1 to 5 are schematic cross-sectional views illustrating a process of forming a semiconductor structure by using a double patterning method.
Referring to fig. 1, a substrate 101 is provided, the substrate 101 having a plurality of discrete core layers 102 formed on a surface thereof.
And the process of forming the core layer 102 is liable to cause over etching (over etch) to the substrate 101 such that the top surface of the substrate 101 under the core layer 102 is higher than the top surface of the substrate 101 exposed by the core layer 102, and the minimum distance between the top of the substrate 101 under the core layer 102 and the top of the substrate 101 exposed by the core layer 102 is L1.
Referring to fig. 2, a side wall layer 103 is formed on the top and side wall surfaces of the core layer 102 and the surface of the substrate 101.
Referring to fig. 3, the side wall layer 103 is etched back by using a maskless etching process (refer to fig. 2), and the side wall layer 103 on the top surface of the core layer 102 and a part of the side wall layer 103 on the surface of the substrate 101 are etched and removed until a part of the surface of the substrate 101 is exposed, so as to form a side wall 104 covering the surface of the side wall of the core layer 102.
In the process of etching the side wall layer 103 by using the maskless etching process, the etching process is prone to further over-etching the surface of the substrate 101, and the thickness of the substrate 101 removed by etching in the process of forming the side wall 104 is L2.
Referring to fig. 4, the core layer 102 (refer to fig. 3) is removed.
Referring to fig. 5, the substrate 101 is etched until a target pattern is formed, using the sidewall spacers 104 as masks.
From the foregoing analysis, after the core layer 102 is removed, the heights of the top surfaces of the substrates 101 on both sides of the sidewall 104 are different, and the difference between the heights of the top surfaces of the substrates 101 on both sides of the sidewall 104 is L1+ L2. Therefore, after the substrate 101 on both sides is etched by using the sidewall 104 as a mask to form a target pattern, the heights of the top surfaces of the substrate 101 on both sides of the correspondingly formed target pattern are also different, and the top surfaces of the substrate 101 on both sides of the target pattern have a height difference, so that the quality of the target pattern formed after etching is affected, and the formed target pattern has the problem of pitch walking.
Further analysis finds that, as shown in fig. 3 and fig. 4, the top surface of the sidewall 104 formed on the sidewall surface of the core layer 102 is an inclined surface, and the closer the distance between the sidewall 104 and the core layer 102 is, the higher the height of the top surface of the sidewall 104 is, so that when the core layer 102 is removed and etching is performed by using the sidewall 104 as a mask, the etching gas collection angles (etch species collection angles) of the etching processes in the two side regions of the same sidewall 104 are different.
Specifically, the etching gas collection angle of the region formed by removing the core layer 102 is a first angle a1, the etching gas collection angle of the region formed by the adjacent sidewall 104 before removing the core layer 102 is a second angle a2, and is affected by the inclination of the top surface of the sidewall 104, and the first angle a1 is smaller than the second angle a 2. In the etching process with the side walls 104 as masks, the etching rate of the region formed by removing the core layer 102 is a first rate, the etching rate of the region formed by the adjacent side wall 104 before removing the core layer 102 is a second rate, and since the first angle a1 is smaller than the second angle a2, the first rate is smaller than the second rate, which is a micro-loading effect (micro-loading effect), and the micro-loading effect further aggravates the height difference of the top surfaces of the substrate 101 on both sides of the target pattern.
To solve the above problems, the present invention provides a double patterning method, comprising: providing a substrate, wherein the substrate comprises a first region and a second region which are sequentially arranged at intervals, the second region comprises first sub-regions which are adjacent to the adjacent first regions, and second sub-regions which are positioned between the adjacent first sub-regions, and a core layer is formed on the substrate of the first region; forming side wall layers on the top and the side walls of the core layer and on the substrate of a second area, wherein the side wall layer of the first sub-area is positioned on the side wall of the core layer, the top of the side wall layer of the second sub-area is lower than the top of the core layer, and the bottom of the side wall layer of the second sub-area is lower than the bottom of the core layer; forming a sacrificial layer on the side wall layer of the second subregion, wherein the top of the sacrificial layer is higher than the top of the core layer or is flush with the top of the core layer; carrying out planarization treatment on the top of the sacrificial layer and the top of the side wall layer, removing the sacrificial layer and the side wall layer which are higher than the top of the core layer, and exposing the top of the core layer; etching the sacrificial layer and the core layer by adopting a first etching process to enable the top of the residual core layer to be flush with the top of the residual sacrificial layer in the second subregion; etching and removing the residual core layer and the side wall layer positioned in the second subarea by adopting a second etching process to expose the first area substrate and the second subarea substrate; and etching the substrate by taking the side wall layer of the first sub-area as a mask to form a target pattern.
In the invention, before the substrate is etched to form the target pattern, the height difference of the substrate surfaces at the two sides of the side wall layer of the first sub-area is small or even zero, so that after the target pattern is formed by etching, the height difference of the substrate surfaces at the two sides of the target pattern is small or even zero, and the quality of the target pattern formed by a double patterning method is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6 to 14 are schematic cross-sectional views illustrating a process of forming a semiconductor structure by using a double patterning method according to an embodiment of the invention.
Referring to fig. 6, a substrate 201 is provided.
In this embodiment, the substrate 201 includes a plurality of first regions I and second regions arranged at intervals in sequence, where the second regions include first sub-regions 21 adjacent to the adjacent first regions I and second sub-regions 22 located between the adjacent first sub-regions 21, and a surface of the substrate 201 of the first region I is flush with a surface of the substrate 201 of the second region; subsequently, a core layer is formed on the surface of the substrate 201 of the first region I, a sidewall layer covering the sidewall surface of the core layer is formed on the surface of the first sub-region 21, and a sidewall layer is also formed on the surface of the second sub-region 22, and simultaneously, the top of the sidewall layer on the surface of the second sub-region 22 is flush with the surface of the substrate 201 of the first region I.
In the direction parallel to the arrangement direction of the first region I and the second region, the width dimension of the first sub-region 21 is consistent with the width dimension of a target pattern to be formed subsequently, so that the width dimension of the first sub-region 21 in the direction parallel to the arrangement direction of the first region I and the second region can be determined according to the width dimension of the target pattern to be formed.
In order to reduce micro loading effect (micro loading effect) in the subsequent etching process of the substrate 201 and to make the distance between a plurality of discrete adjacent masks required for forming the target pattern equal, in this embodiment, the width dimension of the first region I is the same as the width dimension of the second sub-region 22 in the direction parallel to the arrangement direction of the first region I and the second region, or in the direction parallel to the surface of the substrate 201.
The substrate 201 is made of silicon, germanium, silicon carbide or indium gallium; the base 201 may also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a silicon-germanium-on-insulator substrate. In this embodiment, the base 201 is made of silicon, and the base 201 is a silicon substrate.
The substrate 201 can also have semiconductor devices formed therein, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, inductors, or the like. The surface of the substrate 201 can also form an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride or the like. It should be noted that, in the present invention, the substrate 201 is patterned subsequently, and a target pattern is formed in the substrate 201.
In other embodiments, the substrate can further include a substrate and a functional layer on the surface of the substrate, and the subsequent patterning of the substrate is actually the patterning of the functional layer on the surface of the substrate.
With continued reference to fig. 6, a core membrane 202 is formed on the substrate 201.
The core film 202 is subsequently patterned to form a core layer on the first region I substrate 201. And the formed core layer is subsequently removed, so that the material of the core film 202 is a material that can be easily removed, and the process of removing the core film 202 does not damage the substrate 201.
For this purpose, the core film 202 is made of amorphous carbon, ODL (organic Dielectric layer) material, DARC (Dielectric Anti-reflective Coating) material or BARC (Bottom Anti-reflective Coating) material.
In this embodiment, the core film 202 is made of amorphous carbon, and the core film 202 is formed by a spin-on coating process.
If the thickness of the core film 202 is too thin, the thicknesses of the subsequently formed core layer and the sidewall layer located in the first sub-region 21 are also correspondingly thin, so that the sidewall layer of the first sub-region 21 is not enough to be used as a mask for etching the substrate 201, which easily results in that the sidewall layer of the first sub-region 21 has been completely etched and removed when the target pattern is not yet formed. The thickness of the core film 202 should not be too thick, otherwise, the thickness of the subsequently formed core layer is too thick, and the aspect ratio between adjacent core layers is increased, so that the process window for subsequently forming the side wall layer is reduced, the process difficulty for forming the side wall layer is increased, and the poor coverage of the side wall layer at the interface between the core layer and the substrate 201 is also easily caused.
For this reason, in the present embodiment, the thickness of the core film 202 is 10 nm to 200 nm.
Referring to fig. 7, the core film 202 (refer to fig. 6) on the substrate 201 of the second region is etched away, and a core layer 203 is formed on the substrate 201 of the first region I.
The core film 202 on the second region substrate 201 is etched and removed by using a dry etching process. In one embodiment, the process parameters for etching away the core film 202 in the second region include: the etching gas is HBr and O2HBr flow rate of 100sccm to 500sccm, O2The flow rate is 1sccm to 50sccm, the pressure of the reaction chamber is 1 mTorr to 50 mTorr, the high frequency RF frequency of the etching is 100W to 500W, and the low frequency RF frequency is 0W to 200W.
Generally, during the process of etching the core film 202 on the second region substrate 201, the second region substrate 201 is also over-etched, so that a part of the thickness of the second region substrate 201 is etched away, and therefore, after the core layer 203 is formed on the second region substrate 201, the surface of the first region I substrate 201 is higher than the surface of the second region substrate 201. In the present embodiment, after the core layer 203 is formed, the first region I substrate 201 surface and the second region substrate 201 surface have a height difference La therebetween.
In this embodiment, the step of forming the core layer 203 includes: forming a photoresist layer on the core film 202 of the first region I; etching and removing the core film 202 on the substrate 201 of the second region by taking the photoresist layer as a mask to form the core layer 203; and removing the photoresist layer. Referring to fig. 8, a sidewall layer 204 is formed on the top and sidewall of the core layer 203 and on the substrate 201 of the second region, wherein the sidewall layer 204 of the first sub-region 21 is located on the sidewall of the core layer 203, the sidewall layer 204 of the second sub-region 22 is lower at the top than the top of the core layer 203, and the sidewall layer 204 of the second sub-region 22 is lower at the bottom than the bottom of the core layer 203.
As can be seen from the above analysis, in the present embodiment, after the core layer 203 is formed and before the sidewall layer 204 is formed, the surface of the first area I substrate 201 is higher than the surface of the second area I substrate 201.
The material of the sidewall layer 204 is different from that of the core layer 203, and the material of the sidewall layer 204 is also different from that of the substrate 201, so that the subsequent process of removing the core layer 203 does not cause adverse effect on the sidewall layer 204, and the subsequent sidewall layer 204 on the sidewall of the core layer 203 can be used as a mask for etching the substrate 201.
The material of the sidewall layer 204 is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or boron nitride. In this embodiment, the sidewall layer 204 is made of silicon nitride.
The sidewall layer 204 is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the atomic layer deposition process is used to form the side wall layer 204, so that the step coverage (step coverage) capability of the formed side wall layer 204 is good, and thus the side wall layer 204 at the interface between the core layer 203 and the substrate 201 has a good coverage effect.
As can be seen from the foregoing analysis, the surface of the substrate 201 of the second sub-region 22 is lower than the surface of the first region I substrate 201, and the bottom of the sidewall layer 204 of the second sub-region 22 is lower than the surface of the first region I substrate 201, so that when the sidewall layer 204 of the second sub-region 22 is etched and removed by using the second etching process, the first region I substrate 201 higher than the bottom of the sidewall layer 204 of the second sub-region 22 can also be etched and removed, and after the second etching process is completed, the surface of the substrate 201 of the second sub-region 22 is flush with the surface of the first region I substrate 201.
Referring to fig. 9, a sacrificial layer 205 is formed on the sidewall layer 204 of the second sub-region 22, and the top of the sacrificial layer 205 is higher than the top of the core layer 203 or is flush with the top of the core layer 203.
The sacrificial layer 205 fills the area between adjacent first sub-regions 21. The material of the sacrificial layer 205 is different from that of the sidewall layer 204, and the material of the sacrificial layer 205 is different from that of the substrate 201; the material of the sacrificial layer 205 is a material that can be easily removed, and the subsequent process for removing the sacrificial layer 205 will not cause etching damage to the substrate 201.
The material of the sacrificial layer 205 is amorphous carbon, ODL material, DARC material or BARC material.
In addition, in this embodiment, the sacrificial layer 205 and the core layer 203 are etched by using a first etching process, so that the top of the remaining core layer 203 is flush with the top of the remaining sacrificial layer 205 of the second sub-region 22, or the top of the remaining core layer 203 is flush with the top of the sidewall layer 204 of the second sub-region 22, and therefore, the etching rates of the sacrificial layer 205 and the core layer 203 by the first etching process are different from each other or equal to each other.
In order to reduce the requirement for the process difficulty of the subsequent first etching process, in this embodiment, the material of the sacrificial layer 205 is the same as that of the core layer 203. It should be noted that, in other embodiments, the material of the sacrificial layer may also be different from the material of the core layer, and subsequently in the first etching process, by reasonably adjusting the first etching process parameter, it is ensured that the top of the remaining core layer is flush with the top of the remaining sacrificial layer of the second sub-region after the first etching process.
In this embodiment, the material of the sacrificial layer 205 is amorphous carbon, and a spin-on coating process is used to form the sacrificial layer 205.
Referring to fig. 10, the top of the sacrificial layer 205 and the top of the sidewall layer 204 are planarized, and the sacrificial layer 205 and the sidewall layer 204 above the top of the core layer 203 are removed to expose the top of the core layer 203.
In this embodiment, after the planarization process, the top of the sacrificial layer 205, the top of the sidewall layer 204, and the top of the core layer 203 are flush.
The method for determining the stop position for performing the planarization treatment on the top of the sacrificial layer 205 and the sidewall layer 204 comprises the following steps: until the top surface of the sidewall layer 204 of the first sub-region 21 is parallel to the surface of the substrate 201, so that the top surface of the sidewall layer 204 on the first sub-region 21 after the planarization process no longer has an inclined surface, and therefore, when the substrate 201 is etched by using the sidewall layer 204 on the surface of the first sub-region 21 as a mask, the micro-loading effect problem caused by different etching gas collection angles between adjacent masks can be avoided.
Specifically, when the lowest top surface of the sidewall layer 204 of the first sub-region 21 is higher than the top of the core layer 203 or is flush with the top of the core layer 203, the planarization process may be performed only on the sidewall layer 204 and the sacrificial layer 205; alternatively, the planarization process removes a portion of the thickness of the core layer 203 in addition to the sidewall layer 204 and the sacrificial layer 205. When the lowest position of the top surface of the sidewall layer 204 of the first sub-region 21 is lower than the top surface of the core layer 203, the planarization process is performed not only on the sidewall layer 204 and the sacrificial layer 205, but also removes a part of the thickness of the core layer 203.
In this embodiment, the planarization process includes: firstly, performing a chemical mechanical polishing process on the sacrificial layer 205 until the top surface of the sidewall layer 204 is exposed; after the top surface of the sidewall layer 204 is exposed, the sacrificial layer 205 and the sidewall layer 204 are subjected to a dry etching process.
The dry etching process has low etching selectivity to the sacrificial layer 205 and the sidewall layer 204, and the etching gas used in the dry etching process includes fluorocarbon gas, such as C4F8Or CH3F。
In this embodiment, a chemical mechanical polishing process is first employed to polish and remove the thicker sacrificial layer 205, thereby effectively shortening the process duration of the planarization treatment; then, dry etching is performed on the sacrificial layer 205 and the sidewall layer 204, so that the flatness of the top surface of the sidewall layer 204 after planarization can be improved, and the quality of a mask pattern for subsequently etching the substrate 201 is improved.
In other embodiments, the planarization process employs a chemical mechanical polishing process. In another embodiment, the method for determining the stop position for performing the planarization process on the top of the sacrificial layer and the top of the sidewall layer includes: until the top surface of the core layer is exposed, i.e., the core layer does not need to undergo planarization.
Referring to fig. 11, the sacrificial layer 205 and the core layer 203 are etched using a first etching process such that the top of the remaining core layer 203 is flush with the top of the remaining sacrificial layer 205 of the second sub-region 22.
In this embodiment, the etching rates of the first etching process to the sacrificial layer 205 and the core layer 203 are the same, and the etching rate of the first etching process to the sidewall layer 204 is small or even zero, so that the first etching process has high selectivity between the sacrificial layer 205 and the sidewall layer 204, and avoids unnecessary etching of the sidewall layer 204 on the first sub-region 21.
Before the first etching process is performed, the top of the sacrificial layer 205 is flush with the top of the core layer 203, so that the thickness of the sacrificial layer 205 etched and removed by the first etching process is equal to the thickness of the core layer 203 etched and removed by the first etching process, and it is ensured that the top of the remaining sacrificial layer 205 is flush with the top of the remaining core layer 203 after the first etching process is finished.
In this embodiment, referring to fig. 11, in the first etching process, the sacrificial layer 205 with a partial thickness is removed by etching, so that the top of the remaining core layer 203 is flush with the top of the remaining sacrificial layer 205 of the second sub-region 22. The advantages are that: because the sacrificial layer 205 with a certain thickness is reserved on the sidewall layer 204 of the second sub-region 22, and the top of the remaining core layer 203 is flush with the top of the remaining sacrificial layer 205, the first etching process is easy to control, especially the first etching process has strong etching control capability on the core layer 203, and after the first etching process is finished, the top of the remaining core layer 203 is flush with the top of the remaining sacrificial layer 205, over-etching of the remaining core layer 203 by the first etching process is avoided, so that the top of the remaining core layer 203 is prevented from being lower than the top of the sidewall layer 204 of the second sub-region 22, and the quality of a target pattern formed subsequently is improved.
After the first etching process, the thickness of the remaining sacrificial layer 205 in the second sub-region 22 is not suitable to be too small, otherwise, the etching control capability of the first etching process on the core layer 203 is still poor, and the core layer 203 is easily over-etched; if the thickness of the remaining sacrificial layer 205 of the second sub-region 22 is too thick, the etching time for removing the remaining sacrificial layer 205 by etching in the subsequent second etching process is longer, and the corresponding thickness of the remaining core layer 203 is thicker, and the etching time for removing the remaining core layer 203 by etching in the subsequent second etching process is also longer.
For this reason, in this embodiment, after the first etching process, the thickness of the remaining sacrificial layer 205 in the second subregion 22 ranges from 100 angstroms to 200 angstroms.
It should be noted that, in another embodiment, referring to fig. 12, in the first etching process, the sacrificial layer 205 (refer to fig. 10) may be further etched and removed to a full thickness, so that the top of the remaining core layer 203 is flush with the top of the sidewall layer 204 of the second sub-region 22.
Referring to fig. 13, by using a second etching process, the remaining core layer 203 is etched and removed, and the sidewall layer 204 located in the second sub-region 22 is also etched and removed, so that the first I-substrate 201 and the second sub-region 22 substrate 201 are exposed.
In this embodiment, the etching rates of the second etching process to the sidewall layer 204 and the core layer 203 are the same; before the sidewall layer 204 of the second sub-region 22 is etched and removed, the remaining sacrificial layer 205 (refer to fig. 11) on the sidewall layer 204 of the second sub-region 22 is also etched and removed, and the etching rate of the second etching process to the sidewall layer 204 is the same as the etching rate to the sacrificial layer 205.
Since the top of the remaining sacrificial layer 205 is flush with the top of the remaining core layer 203 before the second etching process is performed, the etching rates of the sacrificial layer 205, the sidewall layer 204 and the core layer 203 by the second etching process can be made to be the same by adjusting the process parameters of the second etching process, when the second etching process is finished, the remaining sacrificial layer 205 and the sidewall layer 204 in the second sub-region 22 are etched and removed, the remaining core layer 203 in the first region I is etched and removed, and in the process of etching and removing the remaining core layer 203, the second etching process further etches and removes the substrate 201 in the first region I with a partial thickness, so that after the second etching process, the surface of the substrate 201 in the first region I is flush with the surface of the substrate 201 in the second sub-region 22.
In this embodiment, the second etching process has the same etching rate for the core layer 203, the sidewall layer 204 and the substrate 201.
It should be noted that the over-etched thickness La of the second region substrate 201 is equal to the thickness of the first region I substrate 201 etched and removed by the second etching process. Therefore, after the second etching process is finished, the surface of the first sub-area I substrate 201 is flush with the surface of the second sub-area 22 substrate 201.
Referring to fig. 14, the substrate 201 is etched by using the sidewall layer 204 of the first sub-region 21 as a mask to form a target pattern (not shown).
In this embodiment, the substrate 201 is etched to form a target pattern by using the sidewall layer 204 of the first sub-region 21 as a mask.
From the foregoing analysis, before the substrate 201 is etched, the height difference of the surface of the substrate 201 on both sides of the sidewall layer 204 of the first sub-region 21 is small, and the height difference may also be zero, so that the problem of the height difference caused by etching the sidewall layer in the prior art is avoided or reduced. Therefore, in this embodiment, after the substrate 201 is etched to form the target pattern, the difference between the heights of the surfaces of the remaining substrate 201 on the two sides of the target pattern is also small, and the difference between the heights of the top surfaces of the substrate 201 on the two sides of the target pattern is reduced, so that the quality of the target pattern formed by the double patterning method is improved.
Meanwhile, in this embodiment, after the planarization process, the top surface of the sidewall layer 204 of the first sub-region 21 is parallel to the surface of the substrate 201, so as to avoid the problem of different etching gas collection angles caused by the inclination of the top surface of the sidewall layer 204. In this embodiment, the etching gas collection angles of the areas on both sides of the sidewall layer 204 of the first sub-region 21 are the same, and accordingly, in the etching process of forming the target pattern by etching, the micro-loading effect is effectively reduced or avoided, so that the problem of poor etching rate caused by the micro-loading effect is further avoided, the height difference of the surfaces of the remaining substrates 201 on both sides of the target pattern is further reduced, and the quality of the target pattern formed by the double patterning method is further improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of double patterning, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region which are sequentially arranged at intervals, the second region comprises first sub-regions which are adjacent to the adjacent first regions, and second sub-regions which are positioned between the adjacent first sub-regions, and a core layer is formed on the substrate of the first region;
forming side wall layers on the top and the side walls of the core layer and on the substrate of a second area, wherein the side wall layer of the first sub-area is positioned on the side wall of the core layer, the top of the side wall layer of the second sub-area is lower than the top of the core layer, and the bottom of the side wall layer of the second sub-area is lower than the bottom of the core layer;
forming a sacrificial layer on the side wall layer of the second subregion, wherein the top of the sacrificial layer is higher than the top of the core layer or is flush with the top of the core layer;
carrying out planarization treatment on the top of the sacrificial layer and the top of the side wall layer, removing the sacrificial layer and the side wall layer which are higher than the top of the core layer, and exposing the top of the core layer;
etching the sacrificial layer and the core layer by adopting a first etching process to enable the top of the residual core layer to be flush with the top of the residual sacrificial layer in the second subregion;
etching and removing the residual core layer and the side wall layer positioned in the second subarea by adopting a second etching process to expose the first area substrate and the second subarea substrate;
and etching the substrate by taking the side wall layer of the first sub-area as a mask to form a target pattern.
2. The method of double patterning of claim 1, wherein a width dimension of the first region is the same as a width dimension of the second sub-region in a direction parallel to the substrate surface.
3. The method of double patterning of claim 1, wherein in the first etching process, the sacrificial layer is etched away to a full thickness such that the top of the remaining core layer is flush with the top of the second subregion sidewall layer.
4. The method of double patterning as claimed in claim 1, wherein in the first etching process, a portion of the thickness of the sacrificial layer is etched away so that the top of the remaining core layer is flush with the top of the remaining sacrificial layer of the second sub-region.
5. The method of double patterning of claim 4, wherein after the first etching process, the thickness of the remaining sacrificial layer of the second sub-region ranges from 100 angstroms to 200 angstroms.
6. The double patterning method of claim 4, wherein in the second etching process, the remaining sacrificial layer of the second sub-region is further etched and removed before the sidewall layer of the second sub-region is etched and removed.
7. The method of double patterning of claim 1, wherein the sacrificial layer top is flush with the core layer top prior to performing the first etch process; the thickness of the sacrificial layer etched and removed by the first etching process is equal to that of the core layer etched and removed.
8. The method of double patterning of claim 7, wherein the first etch process etches the sacrificial layer and the core layer at the same rate.
9. The double patterning process of claim 1 or 8, wherein the material of said sacrificial layer is the same as the material of said core layer.
10. The method of double patterning of claim 1, wherein the material of the sacrificial layer is amorphous carbon, BARC material, ODL material, or DARC material; the material of the core layer is amorphous carbon, BARC material, ODL material or DARC material.
11. The double patterning process of claim 1 wherein said spacer layer is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride or silicon oxycarbonitride.
12. The method of double patterning of claim 1, wherein after forming the core layer, the first region substrate surface is higher than the second region substrate surface; in the process of etching and removing the residual core layer, the second etching process also etches and removes the substrate with partial thickness in the first area, so that the substrate surface in the first area is flush with the substrate surface in the second sub-area after the second etching process.
13. The method of double patterning of claim 12, wherein the second etch process etches the core layer, the sidewall layer, and the substrate at the same rate.
14. The method of double patterning of claim 12, wherein the process step of forming the core layer comprises: forming a core film on the substrate; etching to remove the core film on the second regional substrate, and forming the core layer on the first regional substrate; and in the process of etching the core film on the substrate of the second area, the substrate of the second area is also over-etched.
15. The method of double patterning of claim 14, wherein the over-etching of the second region of the substrate is of a thickness equal to the thickness of the first region of the substrate etched away by the second etching process.
16. The method of double patterning as claimed in claim 1, wherein the step of determining the stop position for the planarization process on the top of the sacrificial layer and the top of the sidewall layer comprises: until the top surface of the side wall layer of the first subregion is parallel to the surface of the substrate.
17. The method of double patterning of claim 1 or 16, wherein the planarization process also removes a portion of the thickness of the core layer.
18. The method of double patterning as claimed in claim 1, wherein the step of determining the stop position for the planarization process on the top of the sacrificial layer and the top of the sidewall layer comprises: until the top surface of the core layer is exposed.
19. The method of double patterning as claimed in claim 1, wherein the planarization process comprises: carrying out a chemical mechanical polishing process on the sacrificial layer; and after the chemical mechanical grinding process, carrying out dry etching treatment on the sacrificial layer and the side wall layer.
CN201610738863.8A 2016-08-26 2016-08-26 Double patterning method Active CN107785252B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610738863.8A CN107785252B (en) 2016-08-26 2016-08-26 Double patterning method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610738863.8A CN107785252B (en) 2016-08-26 2016-08-26 Double patterning method

Publications (2)

Publication Number Publication Date
CN107785252A CN107785252A (en) 2018-03-09
CN107785252B true CN107785252B (en) 2021-03-09

Family

ID=61440089

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610738863.8A Active CN107785252B (en) 2016-08-26 2016-08-26 Double patterning method

Country Status (1)

Country Link
CN (1) CN107785252B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111199880B (en) * 2018-11-16 2022-11-08 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor device and semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7998874B2 (en) * 2006-03-06 2011-08-16 Samsung Electronics Co., Ltd. Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same
US7713818B2 (en) * 2008-04-11 2010-05-11 Sandisk 3D, Llc Double patterning method
CN103390551B (en) * 2012-05-10 2017-03-01 联华电子股份有限公司 The manufacture method of semiconductor device pattern structure
CN104900495B (en) * 2014-03-04 2018-03-30 中芯国际集成电路制造(上海)有限公司 The preparation method of self-alignment duplex pattern method and fin formula field effect transistor
CN104078366B (en) * 2014-07-16 2018-01-26 上海集成电路研发中心有限公司 The fin structure manufacture method of Dual graphing fin transistor
CN104064474B (en) * 2014-07-16 2018-01-26 上海集成电路研发中心有限公司 The fin structure manufacture method of Dual graphing fin transistor

Also Published As

Publication number Publication date
CN107785252A (en) 2018-03-09

Similar Documents

Publication Publication Date Title
CN108321079B (en) Semiconductor structure and forming method thereof
US8846490B1 (en) Method of fabricating a FinFET device
KR101992569B1 (en) Iterative self-aligned patterning
US11676821B2 (en) Self-aligned double patterning
CN107731666B (en) Double patterning method
US20090004862A1 (en) Method for forming fine patterns in semiconductor device
KR20150101398A (en) A method for producing fin structures of a semiconductor device in a substrate
CN108206131B (en) Semiconductor structure and method for forming semiconductor structure
TW202018764A (en) Methods for forming integrated circuit structure
TWI815116B (en) Method of manufacturing semiconductor structure
CN109559978B (en) Semiconductor structure and forming method thereof
CN108574010B (en) Semiconductor structure and forming method thereof
US10957550B2 (en) Semiconductor structure and formation method thereof
US10217633B2 (en) Substantially defect-free polysilicon gate arrays
CN110690117B (en) Semiconductor structure and forming method thereof
CN108573865B (en) Semiconductor device and method of forming the same
CN107785252B (en) Double patterning method
CN112349588A (en) Forming method of semiconductor structure and transistor
CN106960816B (en) The method of Dual graphing
KR20070113604A (en) Method for forming micro pattern of semiconductor device
CN110010447B (en) Semiconductor device and method of forming the same
CN114388352A (en) Semiconductor structure and forming method thereof
CN112735947A (en) Semiconductor structure and forming method thereof
TWI458011B (en) Methods for etching multi-layer hardmasks
US8940641B1 (en) Methods for fabricating integrated circuits with improved patterning schemes

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant