CN103515193B - The manufacture method of delicate pattern of semi-conductor device - Google Patents
The manufacture method of delicate pattern of semi-conductor device Download PDFInfo
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- CN103515193B CN103515193B CN201210219509.6A CN201210219509A CN103515193B CN 103515193 B CN103515193 B CN 103515193B CN 201210219509 A CN201210219509 A CN 201210219509A CN 103515193 B CN103515193 B CN 103515193B
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- side wall
- fine pattern
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000059 patterning Methods 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 230000008021 deposition Effects 0.000 claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 8
- 238000013138 pruning Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 230000001936 parietal effect Effects 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000003292 glue Substances 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 8
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000006396 nitration reaction Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Drying Of Semiconductors (AREA)
Abstract
This application discloses a kind of manufacture method of delicate pattern of semi-conductor device: deposition of polysilicon layer successively on a semiconductor substrate, and form the hard mask layer of patterning; The position of the width definition fine pattern odd number line of the hard mask layer of patterning; With the hard mask layer of patterning for mask, etches polycrystalline silicon layer is to manifesting Semiconductor substrate; Prune to reach target live width to the polysilicon layer through over etching; Filling oxide layer between the polysilicon layer with target live width; Side wall layer is formed, the space definition fine pattern even number live width between side wall layer in the both sides of the hard mask layer of patterning; Using the hard mask layer of side wall layer and patterning jointly as mask, the oxide layer manifested is etched to and manifests Semiconductor substrate; Deposition of polysilicon layer again, is filled in the position after oxide layer is etched, forms even number line; Cmp removes side wall layer and hard mask layer forms fine pattern.The present invention can reduce the LWR of fine pattern.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly a kind of manufacture method of delicate pattern of semi-conductor device.
Background technology
At present, for the fine pattern that substrate is formed by line (line) alternately and interval (space), general employing self-aligned double patterning case (SADP, Self-AlignedDoublePatterning) technology.
The method that existing employing SADP technology forms fine pattern comprises the following steps, and is described below in conjunction with Fig. 1 a to Fig. 1 e.
Step 11, refer to Fig. 1 a, deposition-etch destination layer 101 on a semiconductor substrate 100.
Step 12, refer to Fig. 1 b, on the surface of etching target 101 successively deposition of sacrificial layer 102, coating optical resistance glue layer (not shown), and optical resistance glue layer described in exposure imaging patterning, the optical resistance glue layer width of patterning is for defining the interval of fine pattern; With the optical resistance glue layer of patterning for mask, etch the sacrifice layer 102 that described sacrifice layer 102 forms patterning.Wherein, sacrifice layer is generally oxide layer.
Step 13, refer to Fig. 1 c, surperficial at the sacrifice layer 102 of patterning and manifest etching target 101 surface deposition side wall layer 103, and side wall layer 103 described in anisotropic etching, make the side wall layer 103 through over etching be positioned at sacrifice layer 102 both sides of patterning, its width is the live width of fine pattern.Wherein, side wall layer is generally nitration case.As can be seen from figure also, the gap length between sides adjacent parietal layer 103 defines the interval of fine pattern equally.
Step 14, refer to Fig. 1 d, wet method removes the sacrifice layer 102 of patterning.Because sacrifice layer is generally oxide layer, side wall layer is generally nitration case, so adopt hydrofluoric acid to remove the sacrifice layer 102 of patterning, while can guaranteeing to remove sacrifice layer 102, side wall layer is not removed.
Step 15, refer to Fig. 1 e, with the side wall layer 103 after etching for mask, etching target is etched, forms fine pattern.As can be seen from foregoing description, the gap length between the sides adjacent parietal layer 103 after etching defines the interval of fine pattern, and the width of the side wall layer 103 after etching defines the live width of fine pattern.
Based on above-mentioned explanation, existing SADP technology is more complicated, implements production efficiency lower.And side wall layer 103 is after incorgruous etching, and need to keep vertical and the shape of rule, define the live width of fine pattern, this point, for incorgruous etching technics, is difficult to realize well.Further, sacrifice layer 102 surface that side wall layer 103 is deposited on patterning and etching target 101 surface manifested, for the fine pattern of smaller szie, etching target 101 face width manifested is very narrow, the thickness evenness that side wall layer 103 deposits on this position will be very poor, is thus difficult to the side wall layer that etching obtains ideal form.So finally with the side wall layer after etching for mask, when etching target 101 is etched, be difficult to the fine pattern obtaining ideal dimensions, sidewall roughness (the linewallroughness of fine pattern in other words, LWR) very high, if overlooked, will find on the position that fine pattern has very narrow, very wide on some positions.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of delicate pattern of semi-conductor device, the sidewall roughness of fine pattern can be reduced.
Technical scheme of the present invention is achieved in that
A manufacture method for delicate pattern of semi-conductor device, described fine pattern is interval alternately and line, and the method comprises:
Deposition of polysilicon layer successively on a semiconductor substrate, and form the hard mask layer of patterning; The position of the width definition fine pattern odd number line of the hard mask layer of patterning;
With the hard mask layer of patterning for mask, etches polycrystalline silicon layer is to manifesting Semiconductor substrate;
Prune to reach target live width to the polysilicon layer through over etching, wherein, the method for carrying out pruning comprises: oxidise polysilicon layer sidewall, forms silicon oxide layer sidewall, makes unoxidized polysilicon layer width equal target live width; Wet etching removes silicon oxide layer sidewall; Adopt the unoxidized polysilicon layer sidewall of washed with de-ionized water;
Filling oxide layer between the polysilicon layer with target live width;
Side wall layer is formed, the space definition fine pattern even number live width between side wall layer in the both sides of the hard mask layer of patterning;
Using the hard mask layer of side wall layer and patterning jointly as mask, the oxide layer manifested is etched to and manifests Semiconductor substrate;
Deposition of polysilicon layer again, is filled in the position after oxide layer is etched, forms even number line;
Cmp removes side wall layer and hard mask layer forms fine pattern.
Described wet etching is removed silicon oxide layer sidewall and is adopted hydrofluoric acid or hydrochloric acid.
Filling oxide layer adopt spin coating method, and return carve oxide layer to manifest the hard mask layer of patterning.
Adopt polysilicon to form side wall layer, the method comprises further: offside parietal layer is pruned, and makes the space between side wall layer reach target live width.
Described hard mask layer is silicon nitride layer.
Etching is carried out to the oxide layer manifested and adopts dry etching.
As can be seen from such scheme, the line of the present invention to fine pattern is pruned, to reach target live width.Pruning method is softer, and the LWR therefore obtained is lower, thus reaches object of the present invention.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 e is the generalized section that existing employing SADP technology forms fine pattern;
Fig. 2 is the schematic flow sheet of embodiment of the present invention delicate pattern of semi-conductor device manufacture method;
Fig. 2 a to Fig. 2 h is the generalized section that the embodiment of the present invention forms delicate pattern of semi-conductor device.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail.
As shown in Figure 2, be described in detail below in conjunction with Fig. 2 a to Fig. 2 h, it comprises the following steps the schematic flow sheet of embodiment of the present invention delicate pattern of semi-conductor device manufacture method:
Step 21, refer to Fig. 2 a, on semiconductor substrate 200 deposition of polysilicon layer 201 successively, and form the hard mask layer 202 of patterning; The position of the width definition fine pattern odd number line of the hard mask layer 202 of patterning;
Hard mask layer can be silicon nitride layer.Concrete grammar can be: deposition of polysilicon layer and hard mask layer successively on semiconductor substrate 200, in the surface of hard mask layer coating optical resistance glue layer, and optical resistance glue layer described in exposure imaging patterning, the position of the width definition fine pattern odd number line of patterning optical resistance glue layer; With the optical resistance glue layer of patterning for mask, etching hard mask layer forms the hard mask layer 202 of patterning.
Step 22, refer to Fig. 2 b, with the hard mask layer 202 of patterning for mask, etches polycrystalline silicon layer 201 is to manifesting Semiconductor substrate 200;
Step 23, refer to Fig. 2 c, prune (trim) to reach target live width to the polysilicon layer 201 through over etching, wherein, the method for carrying out pruning comprises: oxidise polysilicon layer sidewall, form silicon oxide layer sidewall, make unoxidized polysilicon layer width equal target live width; Wet etching removes silicon oxide layer sidewall; Adopt the unoxidized polysilicon layer sidewall of washed with de-ionized water;
This step is key of the present invention, and in step 21, the width of the hard mask layer 202 of patterning not necessarily can reach target live width, so in this step, can carry out fine pruning, to reach target live width to the polysilicon layer 201 through over etching.First adopt two sidewalls of dioxygen oxidation polysilicon layer, make unoxidized polysilicon layer width equal target live width, the flow control of oxygen is carried out as required; Then hydrofluoric acid or hydrochloric acid wet method is adopted to remove this layer of silicon oxide layer sidewall; Finally adopt the unoxidized polysilicon layer sidewall of washed with de-ionized water.Accurately can control the width adjusting line during oxidation, adopt hydrofluoric acid or hydrochloric acid wet method to remove this layer of silicon oxide layer sidewall and remove silicon oxide layer gradually just as sand polishing, therefore compared with prior art, the LWR of line is effectively reduced.
Step 24, refer to Fig. 2 d, filling oxide layer 203 between the polysilicon layer with target live width;
Preferably, filling oxide layer adopts spin coating method, the hard mask layer 202 of the oxide layer coverage diagram patterning of spin coating, so need back to carve oxide layer to manifest the hard mask layer of patterning.In addition, filling oxide layer also can adopt chemical gaseous phase depositing process.
Step 25, refer to Fig. 2 e, form side wall layer 204 in the both sides of the hard mask layer 202 of patterning, the space definition fine pattern even number live width between side wall layer 204;
In the embodiment of the present invention, side wall layer 204 can adopt polysilicon, because the space definition fine pattern even number live width between this step side wall layer 204, so still can as in step 23, an oxidation part is as the polysilicon of side wall layer, and then this part silica is removed, make the space between side wall layer reach target live width.Certainly, the space between side wall layer also can be directly made to reach target live width.
Step 26, refer to Fig. 2 f, common as mask using the hard mask layer 202 of side wall layer 204 and patterning, the oxide layer 203 manifested is etched to and manifests Semiconductor substrate 200;
The oxide layer 203 that this step adopts dry etching to manifest.
Step 27, refer to Fig. 2 g, deposition of polysilicon layer 201 again, is filled in the position after oxide layer is etched, forms even number line;
Step 28, refer to Fig. 2 h, cmp removes side wall layer 204 and hard mask layer 202 forms fine pattern.
So far, fine pattern of the present invention completes.Fine pattern is interval alternately and line, and the line be made up of polysilicon layer 201 is alternately in the interval be made up of oxide layer 203.
To sum up, adopt the fine pattern that method of the present invention is formed, first substantially can define the position of odd number line; And then prune odd number line to reach target live width, during pruning, wet etching removes silicon oxide layer sidewall, and Measures compare is soft, and make odd number line reach target live width gradually, therefore LWR is lower.When utilizing the space definition fine pattern even number live width between side wall layer further, also can prune by offside parietal layer, make even number line reach target live width.Therefore, the line of fine pattern of the present invention can form accurate size, so accuracy is higher by regulating flexibly.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (6)
1. a manufacture method for delicate pattern of semi-conductor device, described fine pattern is interval alternately and line, and the method comprises:
Deposition of polysilicon layer successively on a semiconductor substrate, and form the hard mask layer of patterning; The position of the width definition fine pattern odd number line of the hard mask layer of patterning;
With the hard mask layer of patterning for mask, etches polycrystalline silicon layer is to manifesting Semiconductor substrate;
Prune to reach target live width to the polysilicon layer through over etching;
Filling oxide layer between the polysilicon layer with target live width;
Side wall layer is formed, the space definition fine pattern even number live width between side wall layer in the both sides of the hard mask layer of patterning;
Using the hard mask layer of side wall layer and patterning jointly as mask, the oxide layer manifested is etched to and manifests Semiconductor substrate;
Deposition of polysilicon layer again, is filled in the position after oxide layer is etched, forms even number line;
Cmp removes side wall layer and hard mask layer forms fine pattern;
It is characterized in that, described in the method for carrying out pruning comprise: oxidise polysilicon layer sidewall, forms silicon oxide layer sidewall, makes unoxidized polysilicon layer width equal target live width; Wet etching removes silicon oxide layer sidewall; Adopt the unoxidized polysilicon layer sidewall of washed with de-ionized water.
2. the method for claim 1, is characterized in that, described wet etching is removed silicon oxide layer sidewall and adopted hydrofluoric acid or hydrochloric acid.
3. method as claimed in claim 1 or 2, is characterized in that, filling oxide layer adopts spin coating method, and returns and carve oxide layer to manifest the hard mask layer of patterning.
4. method as claimed in claim 3, is characterized in that, adopt polysilicon to form side wall layer, the method comprises further: offside parietal layer is pruned, and makes the space between side wall layer reach target live width.
5. the method for claim 1, is characterized in that, described hard mask layer is silicon nitride layer.
6. the method for claim 1, is characterized in that, carries out etching adopt dry etching to the oxide layer manifested.
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| CN106298467B (en) * | 2015-05-28 | 2019-10-18 | 联华电子股份有限公司 | Manufacturing method of semiconductor element pattern |
| CN108231537A (en) * | 2017-12-05 | 2018-06-29 | 中国电子科技集团公司第五十五研究所 | Improve the preparation method of polysilicon sidewall roughness |
| KR20200011174A (en) * | 2018-07-24 | 2020-02-03 | 에스케이하이닉스 주식회사 | Semiconductor Device Having Symmetric Conductive Interconnection Patterns |
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| KR101017753B1 (en) * | 2007-09-12 | 2011-02-28 | 주식회사 하이닉스반도체 | Semiconductor device formation method |
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