CN108231537A - Improve the preparation method of polysilicon sidewall roughness - Google Patents

Improve the preparation method of polysilicon sidewall roughness Download PDF

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Publication number
CN108231537A
CN108231537A CN201711265860.8A CN201711265860A CN108231537A CN 108231537 A CN108231537 A CN 108231537A CN 201711265860 A CN201711265860 A CN 201711265860A CN 108231537 A CN108231537 A CN 108231537A
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polysilicon
layer
preparation
etching
improving
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李士颜
刘昊
何志强
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CETC 55 Research Institute
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CETC 55 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02499—Monolayers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

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Abstract

The invention discloses a kind of preparation method for improving polysilicon sidewall roughness, by strictly controlling the oxidation of polysilicon surface and side wall, etching process condition improves the roughness at etching polysilicon edge；The polysilicon autoxidation processes being combined simultaneously using dry oxygen, wet oxygen are avoided oxidation process and the increase that polysilicon sidewall rises and falls are acted on, and then improve etching line edge roughness problem.The present invention can greatly improve the consistency of polysilicon process, so as to improve the yield rate of the consistency of device performance and device；And the optimization that the novel process technology etches polycrystalline silicon growth so that self-registered technology can be applied in the raceway groove autoregistration preparation of more narrow linewidth.

Description

Improve the preparation method of polysilicon sidewall roughness
Technical field
The present invention relates to field of semiconductor devices more particularly to a kind of preparation methods for improving polysilicon sidewall roughness.
Background technology
Polycrystalline silicon material has high deposition growing efficiency, the processing such as etching, the corrosion of excellent thermal stability and maturation Technique makes it be had a wide range of applications in field of semiconductor device preparation.Polysilicon can be applied to the preparation of Si material devices, The preparation of Ge material devices, the preparation of carbofrax material device and the preparation of compound-material device etc..Such as conduct A kind of crucial constituent material of self-registered technology can solve lithography alignment and alignment difficulty, reduce photoetching cost；As medium Mask pattern can realize the block mask to techniques such as ion implantings；Polysilicon mixes rear good conductive capability, also makes it It is widely used as electrode material of semiconductor devices etc..
Polycrysalline silcon size gradually increases with the growth thickness of polysilicon in polysilicon layer, with polysilicon grain ruler Very little increase causes polysilicon surface surface undulation caused by crystal grain to increase, leads to the polysilicon bottom pair in photoetching Light reflection is uneven, so that line edge roughness after photoetching.Meanwhile during etching polysilicon, due to polysilicon Etch rate difference between crystal grain and crystal grain gap also can further increase the inhomogeneities of lines side wall after etching polysilicon. The surface undulation of these polysilicon lines side walls in high temperature oxidation process, can also further increase, so that polysilicon Lines sidewall profile is second-rate.
Polysilicon lines etch the inhomogeneities of a side wall, can reduce it as autoregistration mask, ion implantation mask, electrode The performance of figure directly influences the efficiency of device, the performance indicators such as consistency of performance and yield rate, therefore uses at present more Crystal silicon lines scheme also has improved necessity.
Invention content
Goal of the invention：In view of the above problems, the present invention proposes a kind of preparation method for improving polysilicon sidewall roughness.
Technical solution：Purpose to realize the present invention, the technical solution adopted in the present invention are：A kind of improvement polysilicon side The preparation method of wall roughness, includes the following steps：
(1) silicon dioxide layer is grown on epitaxial layer；
(2) growing polycrystalline silicon layer in silicon dioxide layer；
(3) high-temperature oxydation polysilicon layer forms polysilicon oxide layer；
(4) wet etching removal polysilicon oxide layer；
(5) polysilicon bargraphs is formed by photoetching and dry etching polysilicon layer；
(6) high-temperature oxydation polysilicon layer forms polysilicon lines oxide layer；
(7) wet etching removal polysilicon lines oxide layer；
(8) polysilicon layer autoxidation forms oxide layer.
Further, high-temperature oxydation is carried out to polysilicon layer and uses dry oxygen technique, wet oxygen technique or two kinds of oxidation technology phases With reference to, 700-1300 DEG C of oxidizing temperature, oxidization time 1-15min.
Further, wet etching uses HF or BOE corrosive liquids, etching time 30-600s.
Further, polysilicon autoxidation is combined using temperature gradients oxidation technology, dry oxygen technique and wet oxygen technique Mode of oxidizing.
Advantageous effect：By strictly controlling the oxidation of polysilicon surface and side wall, etching process condition improves the present invention The roughness at etching polysilicon edge；The polysilicon autoxidation processes being combined simultaneously using dry oxygen, wet oxygen, are avoided and aoxidized Journey acts on the increase that polysilicon sidewall rises and falls, and then improves etching line edge roughness problem.
The technique of the present invention can greatly improve the consistency of polysilicon process, so as to improve the consistency of performance of device With the yield rate of device；And the optimization that the technology etches polycrystalline silicon growth so that self-registered technology can be applied to In prepared by the raceway groove autoregistration of more narrow linewidth.
Description of the drawings
Fig. 1 is steps flow chart schematic diagram of the present invention；
Fig. 2 is that the structure diagram after silicon dioxide layer is grown on epitaxial layer；
Fig. 3 is the structure diagram after growing polycrystalline silicon layer in silicon dioxide layer；
Fig. 4 is the structure diagram after being aoxidized to polysilicon layer；
Fig. 5 is the structure diagram after wet etching；
Fig. 6 is the structure diagram after being etched to polysilicon layer；
Fig. 7 is the structure diagram after being aoxidized to etching polysilicon lines；
Fig. 8 is using the structure diagram after wet etching to polysilicon lines oxide layer；
Fig. 9 is to the structure diagram after polysilicon oxidation.
Specific embodiment
Technical scheme of the present invention is further described with reference to the accompanying drawings and examples.
It is the preparation method of the improvement polysilicon sidewall roughness of the present invention as shown in Figure 1, includes the following steps：
(1) silicon dioxide layer 2 is grown on epitaxial layer 1, as shown in Figure 2.Epitaxial layer 1 be substrate, substrate can be silicon, The a variety of materials such as germanium, silicon carbide, compound semiconductor, etching stop layer of the silicon dioxide layer 2 for polysilicon, thickness range 20nm-100nm.The processing step is applied to polysilicon mask preparation, polysilicon self aligned process and polysilicon electrode etching Etc. in technologies.
(2) the growing polycrystalline silicon layer 3 in silicon dioxide layer 2, as shown in figure 3, polysilicon layer 3 is according to its different purposes, Such as medium mask, polysilicon electrode, autoregistration material, thickness range 200nm-3000nm.
(3) high-temperature oxydation is carried out to polysilicon layer 3, forms polysilicon oxide layer 4, polysilicon oxide layer 4 is rotten in next step It is removed in erosion, has certain smoothing effect to surface, as shown in Figure 4.
High-temperature oxydation can be the method that dry oxygen, wet oxygen or two kinds of oxidation technologies are combined, 700 DEG C of oxidizing temperature range- 1300 DEG C, oxidization time range 1min-15min.The processing step can rise and fall to surface and sidewall polycrystalline silicon bulky grain and carry out Surface oxidation, so as to which in next step wet corrosion technique, smoothing effect is generated to surface and side wall.
(4) it to polysilicon oxide layer 4, is removed using wet corrosion technique, so as to carry out certain smooth, such as figure to surface Shown in 5.
Using HF or BOE corrosive liquids, etching time range 30s-600s, which can pass through etching away bulky grain table The oxide layer in face, so as to reach the smoothing effect to polysilicon surface and side wall.
(5) by photoetching polysilicon bargraphs, then dry etching polysilicon layer 3, forms required polysilicon lines Figure, as shown in Figure 6.
(6) high temperature oxidation process is carried out to the polysilicon layer 3 for forming etching lines, forms polysilicon lines oxide layer 5, it is more Crystal silicon lines oxide layer 5 removes in next step is corroded, and has certain smoothing effect to surface, as shown in Figure 7.
High-temperature oxydation can be the method that dry oxygen technique, wet oxygen technique or two kinds of oxidation technologies are combined, oxidizing temperature model 700 DEG C -1300 DEG C are enclosed, oxidization time range 1min-15min.The processing step can be to surface and sidewall polycrystalline silicon bulky grain It rises and falls and carries out surface oxidation, so as to which in next step wet corrosion technique, smoothing effect is generated to surface and side wall.
(7) it to polysilicon lines oxide layer 5, is removed using wet corrosion technique, so as to carry out centainly smooth to surface, As shown in Figure 8.
Using HF or BOE corrosive liquids, etching time range 30s-600s, which can pass through etching away bulky grain table The oxide layer in face, so as to reach the smoothing effect to polysilicon surface and side wall.
(8) mode of oxidizing being combined using temperature gradients oxidation technology, dry oxygen technique, wet oxygen technique, to polysilicon lines Item is aoxidized, and forms oxide layer 6, as shown in figure 9, to improve the flatness of polysilicon lines oxidation rear wall, avoids oxygen Change process acts on the increase that polysilicon sidewall rises and falls.

Claims (7)

1. a kind of preparation method for improving polysilicon sidewall roughness, it is characterised in that：Include the following steps：
(1) silicon dioxide layer (2) is grown on epitaxial layer (1)；
(2) growing polycrystalline silicon layer (3) in silicon dioxide layer (2)；
(3) high-temperature oxydation polysilicon layer (3) forms polysilicon oxide layer (4)；
(4) wet etching removal polysilicon oxide layer (4)；
(5) polysilicon bargraphs is formed by photoetching and dry etching polysilicon layer (3)；
(6) high-temperature oxydation polysilicon layer (3) forms polysilicon lines oxide layer (5)；
(7) wet etching removal polysilicon lines oxide layer (5)；
(8) polysilicon layer (3) autoxidation forms oxide layer (6).
2. the preparation method according to claim 1 for improving polysilicon sidewall roughness, it is characterised in that：Epitaxial layer (1) For silicon, germanium or silicon carbide.
3. the preparation method according to claim 1 for improving polysilicon sidewall roughness, it is characterised in that：Silicon dioxide layer (2) thickness 20-100nm.
4. the preparation method according to claim 1 for improving polysilicon sidewall roughness, it is characterised in that：Polysilicon layer (3) thickness 200-3000nm.
5. the preparation method according to claim 1 for improving polysilicon sidewall roughness, it is characterised in that：To polysilicon layer (3) it carries out high-temperature oxydation to be combined using dry oxygen technique, wet oxygen technique or two kinds of oxidation technologies, 700-1300 DEG C of oxidizing temperature, Oxidization time 1-15min.
6. the preparation method according to claim 1 for improving polysilicon sidewall roughness, it is characterised in that：Wet etching is adopted With HF or BOE corrosive liquids, etching time 30-600s.
7. the preparation method according to claim 1 for improving polysilicon sidewall roughness, it is characterised in that：Polysilicon is from oxygen Change the mode of oxidizing being combined using temperature gradients oxidation technology, dry oxygen technique and wet oxygen technique.
CN201711265860.8A 2017-12-05 2017-12-05 Improve the preparation method of polysilicon sidewall roughness Pending CN108231537A (en)

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1387248A (en) * 2001-05-18 2002-12-25 三星电子株式会社 Semiconductor device isolating method
CN101572229A (en) * 2008-04-28 2009-11-04 北大方正集团有限公司 Method for flattening surface of polysilicon
CN101740379A (en) * 2008-11-27 2010-06-16 中芯国际集成电路制造(上海)有限公司 Method for eliminating surface defect of semiconductor device and semiconductor device
CN103456608A (en) * 2012-06-04 2013-12-18 上海华虹Nec电子有限公司 Method for growing single crystals and polycrystals on semiconductor substrate at same time
CN103515193A (en) * 2012-06-28 2014-01-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device fine pattern manufacturing method
CN103745925A (en) * 2013-11-14 2014-04-23 上海和辉光电有限公司 Planarization polysilicon film manufacturing method
CN104218002A (en) * 2014-09-23 2014-12-17 武汉新芯集成电路制造有限公司 Manufacture method of three dimensional (3D) NAND flash memory
CN105336593A (en) * 2014-07-18 2016-02-17 中芯国际集成电路制造(上海)有限公司 Manufacturing method of grid and manufacturing method of memory
CN105589131A (en) * 2016-01-19 2016-05-18 中国电子科技集团公司第二十三研究所 Etching method of silicon chip grooves for optical waveguide
CN106601593A (en) * 2016-12-28 2017-04-26 武汉华星光电技术有限公司 Method for reducing the polysilicon surface roughness

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1387248A (en) * 2001-05-18 2002-12-25 三星电子株式会社 Semiconductor device isolating method
CN101572229A (en) * 2008-04-28 2009-11-04 北大方正集团有限公司 Method for flattening surface of polysilicon
CN101740379A (en) * 2008-11-27 2010-06-16 中芯国际集成电路制造(上海)有限公司 Method for eliminating surface defect of semiconductor device and semiconductor device
CN103456608A (en) * 2012-06-04 2013-12-18 上海华虹Nec电子有限公司 Method for growing single crystals and polycrystals on semiconductor substrate at same time
CN103515193A (en) * 2012-06-28 2014-01-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device fine pattern manufacturing method
CN103745925A (en) * 2013-11-14 2014-04-23 上海和辉光电有限公司 Planarization polysilicon film manufacturing method
CN105336593A (en) * 2014-07-18 2016-02-17 中芯国际集成电路制造(上海)有限公司 Manufacturing method of grid and manufacturing method of memory
CN104218002A (en) * 2014-09-23 2014-12-17 武汉新芯集成电路制造有限公司 Manufacture method of three dimensional (3D) NAND flash memory
CN105589131A (en) * 2016-01-19 2016-05-18 中国电子科技集团公司第二十三研究所 Etching method of silicon chip grooves for optical waveguide
CN106601593A (en) * 2016-12-28 2017-04-26 武汉华星光电技术有限公司 Method for reducing the polysilicon surface roughness

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Application publication date: 20180629