CN100517580C - Method for preparing and regulating semiconductor element grids - Google Patents

Abstract

The invention discloses a manufacturing method of a semiconductor device gate and the adjustment method thereof. The manufacturing method comprises the following steps: a polysilicon layer with stress is deposited; the polysilicon layer is etched to form a gate, the shape of the gate is determined by the stress of the polysilicon layer, and when the stress is tensile stress, the bottom part of the formed gate is provided with an unfilled corner; when the stress is compressive stress, the formed gate is provided with vertical side walls or a bottom part with a foot part. The gate manufacturing method of the invention has the advantages that the realization is simple and convenient, gates with different shapes can be manufactured, and the component performance is effectively improved. The gate adjustment method of the invention utilizes the optical characteristic dimension method to detect the fabricated gate shape , performs the adjustment to the stress which is provided to the polysilicon layer according to the difference between the fabricated gate shape and the set gate shape, and finally a gate with a shape conforming to the set shape is manufactured. The adjustment method of the invention is flexible, and can realize the adjustment to the gate shape in a larger range.

Description

The manufacture method of grating of semiconductor element and method of adjustment

Technical field

The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of grating of semiconductor element and method of adjustment.

Background technology

For the semiconductor device below the sub-micron, the shape of grid has material impact to the performance of device.How to form suitable gate shapes,, become one of problem that receives much concern in the current field of manufacturing semiconductor devices with effective performance parameter of improving device.

Figure 1A and 1B are the device profile map of the grid making method of explanation conventional semiconductor device, Figure 1A is the device profile map behind the formation grid material, shown in Figure 1A, on substrate 101, generate gate oxide 102 earlier, again deposition one deck grid material---polysilicon layer 103 on this gate oxide 102.Then, carry out photoetching treatment, on polysilicon layer, define gate patterns, carry out etching again to form polysilicon gate.Figure 1B is the device profile map behind the formation polysilicon gate, and Figure 1B is depicted as ideal situation, and grid 110 sidewalls that promptly form after the etching are steep, and its cross section is the identical square configuration of top and bottom size.In fact, form in the etching technics of grid in this step, the final gate shapes that forms is determined by multiple factor, as the control of etching terminal, evenness of substrate surface or the like, is difficult to form the square ideal structure with vertical sidewall shown in Figure 1B usually.

Fig. 2 A and 2B are the schematic diagram of two kinds of common gate shapes.Wherein, Fig. 2 A is the grid with foot, shown in Fig. 2 A, the bottom of the grid 201 that forms is greater than its top, formed the grid of foot (footing), the reason that this foot grid occurs has multiple, and a kind of common reason is when the etching terminal monitoring is not good, can make the still residual more grid material of substrate surface after the etching, cause gate bottom after the etching situation of foot to occur.The appearance of this foot grid makes the physical length of grid greater than the length value of design, and the result causes the device operating rate slow, when serious even can not work substantially.Fig. 2 B is the grid with unfilled corner, and shown in Fig. 2 B, grid 202 bottoms that form after the etching have formed the gate profile of unfilled corner (notch) less than the top.Over etching has appearred in a kind of reason of appearance unfilled corner when being etch polysilicon.The appearance of this unfilled corner phenomenon can make actual polysilicon gate length less than design load, and if this polysilicon gate length is too short, source region and drain region just may break-through, cause component failure.Therefore, how to guarantee when making grid that the shape of grid is normal, most important to the performance of device.

Along with developing rapidly of very lagre scale integrated circuit (VLSIC), the integrated level of chip is more and more higher, and size of devices is more and more littler, and the manufacture craft of semiconductor device is had higher requirement.With the example that is made as to grid, requirement to its shape is more strict, the requirement on devices that has can form the grid with vertical sidewall, the device that has is then because the small size device live width is less, the difficulty of photoetched grid is bigger, for reducing the requirement to photoetching, hope can form the gate shapes of unfilled corner to a certain degree.Reason is, is guaranteeing that the size at the top of its grid can be done greatlyyer, the requirement to characteristic size (CD) when so just having relaxed photoetched grid under the gate bottom size situation identical with design load.

The step that can add a step over etching behind the grid of etch polysilicon formation now usually; to remove the polymer that produces in the etching of on gate lateral wall, adhering to; this over etching is handled, and can cause the gate bottom after the etching to be shaped as unfilled corner, and this is unfavorable to device that hope forms the vertical gate sidewall.Simultaneously, form the device of unfilled corner grid to a certain degree for hope, because of excessive over etching can damage the surface of substrate, the degree of handling the grid unfilled corner that forms by over etching is limited merely.Therefore, only by the improvement of etch technological condition being realized method to the adjustment of device grids shape is to guarantee to produce grid that shape meets the demands.

The grid that has big unfilled corner for formation, application number is that 02143074.8 Chinese patent application discloses a kind of method that forms the groove grids profile, it utilizes the polysilicon layer of thermal oxidation technology consumption part, when removing oxidized polysilicon, the oxide regions place that forms between polysilicon and gate oxide can form a depression, the gate shapes that one groove is arranged bottom promptly having formed, but this method has increased thermal oxidation, multistep steps such as wet etching, prolonged the production cycle, strengthened production cost, and this step oxidation technology has negative influence to device, can cause the decreased performance such as reliability of device.In addition, this method can only realize forming the adjusting of grid unfilled corner size by changing oxidizing condition, can not other gate shapes, and as desirable grid with vertical sidewall, versatility and flexibility deficiency.

Summary of the invention

The invention provides a kind of grid making method and method of adjustment of semiconductor device, this manufacture method can form respectively as required have vertical sidewall, the bottom is the grid of foot or unfilled corner, and can utilize method of adjustment to adjust the bottom shape of the grid of made easily and flexibly according to the deviation between the gate shapes of actual gate shape and setting.

The manufacture method of a kind of grating of semiconductor element provided by the invention comprises step:

Deposition has the polysilicon layer of stress;

The described polysilicon layer of etching forms grid, and the shape of described grid determines that by the stress that described polysilicon layer has when described stress was tensile stress, the gate bottom of formation had unfilled corner; When described stress was compression, the gate shapes of formation was that the vertical or bottom of sidewall has foot.

Wherein, the stress that described polysilicon layer has is by its depositing temperature adjustment: when described depositing temperature between 400 to 600 ℃ the time, described polysilicon layer has tensile stress, and described tensile stress increases along with the reduction of temperature; When described depositing temperature more than 600 ℃ the time, described polysilicon layer has compression, and described compression increases along with the rising of temperature.

Wherein, described polysilicon layer is formed by the plasma enhanced chemical vapor deposition method, and the thickness of described polysilicon layer is 600 to 1500

Between.

The present invention has the method for adjustment of a kind of grating of semiconductor element of identical or relevant art feature, comprises step:

Set the shape of grid;

Be identified for making the stress that the polysilicon layer of grid should have according to described shape, be shaped as the bottom when having unfilled corner when described grid, described polysilicon layer should have tensile stress, and when being shaped as the vertical or bottom of sidewall and having foot of described grid, described polysilicon layer should have compression;

The stress that should be had by described polysilicon layer is determined the depositing temperature of described polysilicon layer;

By described depositing temperature deposit spathic silicon layer;

The described polysilicon layer of etching forms grid.

Wherein, when the stress of polysilicon layer required to tensile stress, described depositing temperature was between 400 to 600 ℃, and described tensile stress can increase along with the reduction of described depositing temperature; When the stress of polysilicon layer required to compression, described depositing temperature was more than 600 ℃, and described compression can increase along with the rising of described depositing temperature.

Wherein, described polysilicon layer is formed by the plasma enhanced chemical vapor deposition method, and the thickness of described polysilicon layer is 600 to 1500

Between.

In addition, after forming grid, also comprise step:

Shape to described grid detects;

The shape of the shape of the grid that detection is obtained and the grid of setting compares:

Conform to the shape of the grid of setting if detect the shape of the grid obtain, then keep the depositing temperature of described polysilicon layer of next group device constant;

If it is bigger than the bottom of the gate shapes of setting to detect the bottom of the gate shapes that obtains, then reduce the depositing temperature of the described polysilicon layer of next group device;

If it is littler than the bottom of the gate shapes of setting to detect the bottom of the gate shapes that obtains, then improve the depositing temperature of the described polysilicon layer of next group device.

Wherein, described detection utilizes optical signature size measuring method to realize.

Compared with prior art, the present invention has the following advantages:

The grid making method of semiconductor device of the present invention, the method that the polysilicon layer that has adopted deposition to have stress is made device grids, formation has vertical sidewall respectively, the bottom is the grid of foot or unfilled corner, this manufacture method does not need to increase new processing step, can not extend manufacture cycle and increase production cost, and implement simple and convenient.

The grid method of adjustment of semiconductor device of the present invention, utilize optical signature size method that the device grids bottom shape of producing is monitored, and the shape of shape that can go out in actual fabrication and setting is to some extent during deviation, by adjusting stress kind and the size that this polysilicon layer has, gate bottom shape to the next group device is adjusted, and finally makes the gate bottom shape that forms behind this polysilicon layer of etching conform to the shape of setting.Shapes such as this method of adjustment can be adjusted into gate bottom vertically easily and flexibly, foot and unfilled corner, and the scope of adjusting is bigger, and versatility is stronger.

Description of drawings

Figure 1A and 1B are the device profile map of the grid making method of explanation conventional semiconductor device;

Fig. 2 A and 2B are the schematic diagram of two kinds of common gate shapes;

Fig. 3 A and 3B are the device profile map of the grid making method of explanation semiconductor device of the present invention;

Fig. 4 is the flow chart of the method for adjustment of explanation grating of semiconductor element of the present invention.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.

Processing method of the present invention can be widely applied in many application; and can utilize many suitable material; be to be illustrated below by preferred embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.

Secondly, the present invention utilizes schematic diagram to describe in detail, when the embodiment of the invention is described in detail in detail, for convenience of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, should be with this as limitation of the invention, in addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.

For realizing the optimum of device performance, various types of devices is to shape, the dimensional requirement difference of grid, and the device grids that needs that has is desirable vertical sidewall shape, and there is certain unfilled corner in its bottom of then wishing that has.For obtaining sidewall shape grid preferably, normally utilize the adjustment that the adjustment of grid etch process conditions is realized the gate lateral wall shape, as, the control that can stop terminal point by to etching the time realizes the adjustment of oppose side wall shape: form the grid of foot when etching is not enough, form the grid of unfilled corner during over etching.But; when etch polysilicon forms grid; if not carrying out over etching handles; to be difficult to remove polymer attached on the gate lateral wall; therefore, after carrying out main etching, also need to add the operation of over etching usually, like this; the polysilicon gate that forms is generally the unfilled corner shape shown in Fig. 2 B, and the grid of this unfilled corner shape often can not meet the gate shapes of the optimum of device setting---and have vertical sidewall or have bigger unfilled corner.Because, though over etching can produce a unfilled corner in gate bottom, but, the size of this unfilled corner is relevant with the degree of over etching, the processing that common over etching is removed polymer can only form less unfilled corner, and for the formation of bigger unfilled corner, the over etching time that needs is longer, can damage substrate surface, unfavorable to device performance.Therefore, in fact be difficult to adjust the gate shapes of device by adjusting etch technological condition.

For obtaining having the grid of optimum shape, the invention provides a kind of manufacture method of grating of semiconductor element: deposition one deck has the polysilicon layer of stress earlier, again this polysilicon layer is carried out etching, forms grid.Utilize the difference of the stress that polysilicon layer has, can under identical etching condition, form and have difform polysilicon gate.It realizes that principle is: when the polysilicon of growth has different stress, they also can be different thereupon with the surface stress of intersection between the grid silicon oxide layer of its lower floor, if this stress is tensile stress, etch rate at the polysilicon of the intersection with stress during etching can be higher, and the result has just formed unfilled corner at this intersection (bottom the polysilicon gate); Otherwise if this stress is compression, the etching polysilicon speed of this intersection can decrease, and the result has formed foot at this intersection (polysilicon gate bottom).In addition, when proper, can realize only remedying the grid unfilled corner phenomenon that the over etching polysilicon causes, form and have the gate shapes of vertical sidewall the control of this compression size.

Fig. 3 A and 3B are the device profile map of grid making method of explanation semiconductor device of the present invention, below in conjunction with Fig. 3 A and 3B a specific embodiment of the grid making method of semiconductor device of the present invention are described in detail.

In the present embodiment, the gate shapes of setting is the square configuration with vertical sidewall, usually when forming polysilicon layer, etching has the over etching step, make the gate bottom that forms that one unfilled corner always be arranged, for removing this unfilled corner, form the grid of setting with vertical sidewall, the polysilicon layer in the present embodiment will have compression.

Fig. 3 A is for forming the device profile map behind the polysilicon layer with compression, and as shown in Figure 3A, one deck gate oxide 102 of having grown on substrate 101, this gate oxide normally utilize thermal oxidation method to form, and thickness is between several nm.Then, utilize the chemical gaseous phase depositing process one deck of on this gate oxide 102, having grown to be used to form the polysilicon layer 301 of grid.In the present embodiment, this polysilicon layer should have certain compression, to form the polysilicon gate with vertical sidewall after etching.

Can realize the kind of stress that this polysilicon layer is had and the adjustment of size by the growth conditions of adjusting polysilicon layer, as depositing temperature, reaction gas flow, chamber pressure etc., in the present embodiment, utilize plasma enhanced chemical vapor deposition method (PECVD) growing polycrystalline silicon material, and realize the adjustment of stress that polysilicon layer is had by the depositing temperature of regulating polysilicon: if need to generate polysilicon layer with tensile stress, then the depositing temperature of this polysilicon should be between 400 to 600 ℃, and this tensile stress increases along with the reduction of temperature; If need to generate the polysilicon layer with compression, then the depositing temperature of this polysilicon should be more than 600 ℃, and this tensile stress increases along with the rising of temperature.In the present embodiment, the polysilicon deposition temperature of choosing as is 620 ℃ between 600 to 650 ℃, and the polysilicon layer that this moment, growth formed only has less compression, about at-20MPa.This thickness with polysilicon layer of compression is determined by the gate height of requirement on devices, usually 600 to 1500

Between, as be 1000

Fig. 3 B is the device profile schematic diagram behind the formation grid, shown in Fig. 3 B, have the polysilicon layer 301 of compression in formation after, make gate patterns thereon by lithography, then utilize the dry etching method etching to form polysilicon gate 310, when carrying out dry etching, still prolong and use original dry etching method, after etching,, add the over etching step for removing the polymer of side-walls.Because polysilicon layer has compression, its etch rate at polysilicon and gate oxide intersection is slower, when main etching technology is finished, one foot can be formed on the bottom at polysilicon gate, therefore, this over etching step that adds behind the main etching not only can be removed the polymer on the gate lateral wall, can also make gate bottom originally because of the foot that etch rate forms slowly is eliminated, and finally form the grid 310 that conforms to the shape of the vertical sidewall of setting.

In the present embodiment,, make it have compression, after etching, formed grid with vertical sidewall shape by adjusting the depositing temperature of polysilicon layer; In other embodiments of the invention, can also pass through adjusting, make it have tensile stress, to form the grid that the bottom has bigger unfilled corner the depositing temperature of polysilicon layer.When depositing temperature being arranged on 500 ℃ of left and right sides, the polysilicon layer of growth has tensile stress, and the etch rate of itself and gate oxide intersection is very fast, and the result can form the grid with unfilled corner shape after etching.And, the size of this unfilled corner is to be determined by the stress intensity that polysilicon layer has, and the stress intensity that this polysilicon layer had is to be regulated by its depositing temperature: the temperature during the deposit spathic silicon layer is low more, the required tensile stress that has of this polysilicon layer is just big more, and the bottom unfilled corner of the device grids of formation is also just big more.Therefore,, can grow polysilicon layer with big tensile stress by growing polycrystalline silicon layer under than the low deposition temperature, but and then etching form the gate shapes that the bottom has bigger unfilled corner.The grid that this bottom has bigger unfilled corner can guarantee that under the undersized situation of grid, the characteristic size when relaxing photoetched grid has reduced the requirement to photoetching process, and is particularly favourable for small size device.

Grating of semiconductor element manufacture method of the present invention has illustrated how to utilize the polysilicon layer with different stress, and etching forms has difform grid.In addition, utilize grid method of adjustment of the present invention can also realize adjustment easily and flexibly to gate shapes.

Fig. 4 is the flow chart of the method for adjustment of explanation grating of semiconductor element of the present invention, introduces a specific embodiment of grid method of adjustment of the present invention in detail below in conjunction with Fig. 4.

Before making device, set the bottom shape (S401) of this device grids earlier according to the requirement of concrete device.Usually be not very little device for size, realize that the characteristic size of its grid is not difficult for photoetched grid technology, at this moment, the grid of this device preferably has vertical sidewall shape.But for the little device to 65nm of size, because of its grid size too small, required precision to photoetching during photoetched grid is higher, technology difficulty is bigger, at this moment, in order to reduce the required precision of photoetching, preferably can form the bottom and have the gate shapes of unfilled corner, and different devices also has different requirements to the size of this unfilled corner.Therefore before making device, should set the gate bottom shape that it has earlier according to performance, the technological requirement of concrete device.In the present embodiment, the gate shapes of setting is bottom size (45nm) has unfilled corner than the bottom of the little 5nm of top dimension (50nm) a shape.

Then, determine the stress that should have (S402) of polysilicon layer by the bottom shape of the grid of setting, when gate bottom need be the unfilled corner shape, the stress of this polysilicon layer required to be tensile stress, and need the grid unfilled corner of formation big more, the tensile stress that requires this polysilicon layer to have is also just big more; When gate bottom need be vertical or foot shape, the stress of this polysilicon layer required to be compression, and needed the grid foot of formation big more, and the compression that requires this polysilicon layer to have is also just big more.In the present embodiment, formation be bottom unfilled corner bigger grid, thereby require this polysilicon layer to have certain tensile stress, the size that is assumed to be this stress is about 20MPa.

Then, require to determine the depositing temperature (S403) of polysilicon layer according to the stress of the polysilicon layer of determining among the S402.In the present embodiment, this polysilicon layer is formed by chemical gaseous phase depositing process, therefore, this step is in the time of can be according to the chemical vapour deposition (CVD) polysilicon, relation between the stress that its depositing temperature and polysilicon layer have determines that growth has the required depositing temperature of polysilicon layer of definite stress, is specially: when the stress of polysilicon layer requires to tensile stress, depositing temperature need be arranged between 400 to 600 ℃, and depositing temperature reduces along with the increase of the desired tensile stress of polysilicon layer; When the stress of polysilicon layer required to compression, depositing temperature need be arranged on more than 600 ℃, and depositing temperature raises along with the increase of the desired compression of polysilicon layer.In the present embodiment,, need its depositing temperature is arranged on about 550 ℃ for growth has the polysilicon layer of the tensile stress of 20MPa.

Follow again, can be according to the depositing temperature deposit spathic silicon layer of determining in the S403 step (S404).In the present embodiment, utilize the method for chemical vapour deposition (CVD), be assumed to be the PECVD method, under 550 ℃ temperature, deposited the polysilicon layer that has about 20MPa with tensile stress.

Then, the etch polysilicon layer forms grid (S405).Because this polysilicon layer has the tensile stress about 20MPa, intersection at polysilicon layer and gate oxide, the etch rate of polysilicon is very fast, therefore, the grid that forms after etching should conform to the gate shapes of setting, the bottom (45nm) that is grid is less than top (50nm), and the bottom has bigger unfilled corner.

But, consider that the gate lateral wall shape that forms after the etching can be subjected to influence of various factors, also can have influence on the gate shapes of device as the evenness of substrate surface, therefore, in actual fabrication, the gate shapes that may occur producing with set the situation that shape does not conform to, and this can cause departing from of device performance.For the device grids shape of guaranteeing to produce conforms to design shape, after making device grids, it is carried out sampling Detection, be to utilize optical signature size method that gate shapes is detected (S406) in the present embodiment, it can damage device, but in other embodiments of the invention, also can utilize ESEM additive methods such as (SEM) that the gate shapes of making is detected.

Then, the gate shapes that detection is obtained compares judgement (S407) with the setting shape: conform to the setting shape if detect the gate shapes that obtains, the depositing temperature that then shows polysilicon is suitable, subsequent technique (S411) can be directly entered, and the polysilicon layer of next group device can be directly deposited by the depositing temperature in this S404 step; If but the bottom shape that detects the grid obtain do not conform to the gate shapes of setting, then also to judge (S408), with the adjustment direction of the depositing temperature of definite next group polysilicon layer to its concrete condition that does not conform to.As judge and whether detect the bottom obtain than big (being that unfilled corner is bigger than what set than the little or foot of setting) set, if, then reduce the depositing temperature (S409) of polysilicon layer, then by the polysilicon layer (S404) of this depositing temperature that has reduced deposition next group device; If not, the depositing temperature (S410) of the polysilicon layer that then raises is then by the polysilicon layer (S404) of this depositing temperature that has raise deposition next group device.As, in the present embodiment, find that if detect the bottom of the grid of producing has only dwindled 3nm than the top, compare with the 5nm that dwindles that sets, its gate bottom is bigger than what set, promptly the unfilled corner that forms in gate bottom is big not enough, for this reason, should suitably reduce the depositing temperature of its polysilicon again, as reduce to 520 ℃, and when next group device growth polysilicon, press this newly-installed 520 ℃ temperature deposition growing polysilicon layer.

After the above-mentioned adjustment of detection repeatedly, finally can obtain shape and set the device that shape conforms to, after this, can carry out device production by the polycrystalline silicon growth condition that obtains by above-mentioned method of adjustment.

Present embodiment, be to the adjustment of device grids shape before formal production, in other embodiments of the invention, can also be after entering formal production, carry out above-mentioned detection, determining step simultaneously, whether the gate shapes made from monitoring at any time meets the demands, and can be according to its deviation value, depositing temperature to polysilicon layer is adjusted flexibly, guarantees that the difference of the shape of the shape of grid and setting is to drop within the normal tolerance.

Though the present invention with preferred embodiment openly as above, it is not to be used for limiting the present invention, and is any

Those skilled in the art can make possible change and modification without departing from the spirit and scope of the present invention, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.

Claims (10)

1, a kind of manufacture method of grating of semiconductor element comprises step:

Deposition has the polysilicon layer of stress;

The described polysilicon layer of etching forms grid, and the shape of described grid determines that by the stress that described polysilicon layer has when described stress was tensile stress, the gate bottom of formation had unfilled corner; When described stress was compression, the gate shapes of formation was that the bottom has foot.

2, manufacture method as claimed in claim 1, it is characterized in that: the stress that described polysilicon layer has is by its depositing temperature adjustment: when described depositing temperature between 400 to 600 ℃ the time, described polysilicon layer has tensile stress, and described tensile stress increases along with the reduction of temperature; When described depositing temperature more than 600 ℃ the time, described polysilicon layer has compression, and described compression increases along with the rising of temperature.

3, manufacture method as claimed in claim 1 is characterized in that: described polysilicon layer is formed by the plasma enhanced chemical vapor deposition method.

4, manufacture method as claimed in claim 1 is characterized in that: the thickness of described polysilicon layer 600 to

Between.

5, a kind of method of adjustment of grating of semiconductor element comprises step:

Set the shape of grid;

Be identified for making the stress that the polysilicon layer of grid should have according to described shape, be shaped as the bottom when having unfilled corner when described grid, described polysilicon layer should have tensile stress, when described grid be shaped as the bottom when having foot, described polysilicon layer should have compression;

The stress that should be had by described polysilicon layer is determined the depositing temperature of described polysilicon layer;

By described depositing temperature deposit spathic silicon layer;

The described polysilicon layer of etching forms grid.

6, method of adjustment as claimed in claim 5 is characterized in that: when the stress of polysilicon layer required to tensile stress, described depositing temperature was between 400 to 600 ℃, and described tensile stress can increase along with the reduction of described depositing temperature; When the stress of polysilicon layer required to compression, described depositing temperature was more than 600 ℃, and described compression can increase along with the rising of described depositing temperature.

7, method of adjustment as claimed in claim 5 is characterized in that: described polysilicon layer is formed by the plasma enhanced chemical vapor deposition method.

8, manufacture method as claimed in claim 5 is characterized in that: the thickness of described polysilicon layer 600 to

Between.

9, method of adjustment as claimed in claim 5 is characterized in that: after forming grid, also comprise step:

Shape to described grid detects;

The shape of the shape of the grid that detection is obtained and the grid of setting compares:

Conform to the shape of the grid of setting if detect the shape of the grid obtain, then keep the depositing temperature of described polysilicon layer of next group device constant;

If it is bigger than the bottom of the gate shapes of setting to detect the bottom of the gate shapes that obtains, then reduce the depositing temperature of the described polysilicon layer of next group device;

If it is littler than the bottom of the gate shapes of setting to detect the bottom of the gate shapes that obtains, then improve the depositing temperature of the described polysilicon layer of next group device.

10, method of adjustment as claimed in claim 9 is characterized in that: described detection utilizes optical signature size measuring method to realize.

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