CN101728253A - Manufacturing method and adjusting method of grating of semiconductor element - Google Patents
Manufacturing method and adjusting method of grating of semiconductor element Download PDFInfo
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- CN101728253A CN101728253A CN200810224594A CN200810224594A CN101728253A CN 101728253 A CN101728253 A CN 101728253A CN 200810224594 A CN200810224594 A CN 200810224594A CN 200810224594 A CN200810224594 A CN 200810224594A CN 101728253 A CN101728253 A CN 101728253A
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Abstract
The invention discloses a manufacturing method of a grating of a semiconductor element. The method comprises: forming a grating oxidization layer on a substrate, and then depositing a polysilicon layer on the grating oxidization layer; depositing a stressed silicon nitride layer on the polysilicon layer to allow the polysilicon layer to have a corresponding stress; removing the silicon nitride layer; and etching the polysilicon layer to form the grating, wherein the shape of the grating is determined by the stress born by the polysilicon layer, so the bottom of the formed grating has an unfilled corner when the stress is a tensile stress, and the grating has a shape that a side wall is vertical or the bottom part has a foot part when the stress is a pressure stress. The invention also discloses an adjusting method of the grating of the semiconductor element. The method can flexibly and accurately form the grating with the vertical side wall and the foot part or unfilled corner on the bottom part.
Description
Technical field
The present invention relates to the semiconductor integrated circuit manufacture technology field, particularly a kind of manufacture method of grating of semiconductor element and method of adjustment.
Background technology
At present, for the semiconductor device below the sub-micron, the shape of grid has material impact to the performance of device.How to form suitable gate shapes,, become one of problem that receives much concern in the current semiconductor device making field with effective performance parameter of improving device.
Fig. 1 is the device profile map of the manufacture method of prior art grating of semiconductor element.As shown in Figure 1, on substrate 101, generate gate oxide 102, deposit spathic silicon layer 103 on this gate oxide 102 more earlier.Then, polysilicon layer is carried out photoetching treatment, on polysilicon layer, define gate patterns, carry out etching again to form polysilicon gate 203, as shown in Figure 2.Figure 2 shows that ideal situation, grid 203 sidewalls that promptly form after the etching are steep, and its cross section is the identical square configuration of top and bottom size.In fact, in the etching technics that forms grid, the final gate shapes that forms is determined by multiple factor, as the control of etching terminal, evenness of substrate surface or the like, is difficult to form the square ideal structure with vertical sidewall as shown in Figure 2 usually.
Fig. 3 A and 3B are the schematic diagram of two kinds of common gate shapes.Wherein, Fig. 3 A is for having the grid of foot (footing), this grid 303 the bottom be greater than its top.The reason that this foot grid occurs has multiple, and a kind of common reason is to monitor when not good when etching terminal, can make the still residual more grid material of substrate surface after the etching, causes gate bottom after the etching situation of foot to occur.The appearance of this foot grid makes the physical length of grid greater than the length value of design, and the result causes the device operating rate slow, when serious even can not work substantially.Fig. 3 B is for having the grid of unfilled corner (notch), and the bottom of this grid 313 is less than the top.A kind of reason that this unfilled corner grid occurs over etching occurred when being etch polysilicon, makes actual polysilicon gate length less than design load, if polysilicon gate length is too short, the just possibility break-through of source region and drain region causes component failure.Therefore, how to guarantee when making grid that the shape of grid is normal, most important to the performance of device.
Usually be not very little device for size, realize that the characteristic size of its grid is not difficult for photoetched grid technology, at this moment, the grid of this device preferably has vertical sidewall shape.But for the little device to 65nm of size, because of its grid size too small, required precision to photoetching during photoetched grid is higher, technology difficulty is bigger, at this moment, in order to reduce the required precision of photoetching, be preferably formed as the gate shapes that the bottom has unfilled corner, and different devices also has different requirements to this unfilled corner size.
Normally utilize adjustment to realize the gate lateral wall shape to the grid etch process conditions.The control that can stop terminal point by to etching the time realizes needed gate shapes: form the grid of foot when etching is not enough, form the grid of unfilled corner during over etching.But, when the etch polysilicon layer forms grid, if not carrying out over etching handles, to be difficult to remove polymer, therefore, after carrying out main etching, add the operation of over etching usually attached on the gate lateral wall, like this, just formed grid, and this grid with unfilled corner often can not meet the gate shapes of the optimum of device setting, promptly has bigger unfilled corner with unfilled corner.But for the formation of big unfilled corner, the over etching time that needs is longer, can damage substrate surface, and is unfavorable to device performance.Therefore in fact be difficult to realize the gate shapes of required usefulness by adjusting etch technological condition.
Application number is manufacture method and the method for adjustment that 200610147435.4 Chinese patent application discloses a kind of grating of semiconductor element, the method that the polysilicon layer that has adopted deposition to have stress is made device grids, formation has vertical sidewall respectively, the bottom is the grid of foot or unfilled corner, and utilize the device grids bottom shape of optical signature size method, adjust by the depositing temperature of direct change polysilicon to producing.But this method is directly the growth conditions of polysilicon layer to be adjusted, because the type difference of polysilicon layer can be brought some negative effects as grid electrology characteristic aspect, influences the quality of grid.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of manufacture method of grating of semiconductor element, and formation has vertical sidewall exactly, the bottom is the grid of foot or unfilled corner.
Second purpose of the present invention is to provide a kind of method of adjustment of grating of semiconductor element, on the basis of manufacture method, more flexibly and accurately realizes desired gate bottom shape.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
According to first aspect of above-mentioned purpose, the invention discloses a kind of manufacture method of grating of semiconductor element, on substrate, generate after the gate oxide, key is that this method is further comprising the steps of:
Deposit spathic silicon layer on described gate oxide;
Deposition has the silicon nitride layer of stress on described polysilicon layer, makes described polysilicon layer have corresponding stress;
Remove described silicon nitride layer;
The described polysilicon layer of etching forms grid, and the shape of described grid determines that by the stress that described polysilicon layer has when described stress was tension stress, the gate bottom of formation had unfilled corner; When described stress was compression, the gate shapes of formation was that the vertical or bottom of sidewall has foot.
The stress that described polysilicon layer has by described silicon nitride layer depositing temperature determine, when the depositing temperature of described silicon nitride layer at 400 ℃ between 600 ℃ the time, described polysilicon layer has tension stress, and described tension stress increases with the reduction of temperature; When described silicon nitride layer depositing temperature more than 600 ℃ the time, described polysilicon layer has compression, and described compression increases with the rising of temperature.
Described deposition has after the silicon nitride layer of stress, and this method further comprises the step of described silicon nitride layer being carried out annealing in process.
The method of described deposit spathic silicon layer is a chemical vapour deposition technique, and technological parameter comprises: chamber pressure is 0.05Torr～0.5Torr, and the flow of silane is 50sccm～500sccm, and depositing temperature is 550 ℃～700 ℃, and sedimentation time is 500s～2000s.
The method that described deposition has the silicon nitride layer of stress is the plasma enhanced chemical vapor deposition method.
The technological parameter of described deposition process comprises: chamber pressure is 1Torr～15Torr, radio-frequency power is 10W～200W, high frequency is 10MHZ～15MHZ, low frequency is 100KHZ～500KHZ, the flow of silane is 5sccm～100sc2cm, the flow of ammonia is 5sccm～50sccm, and the flow of nitrogen is 100sccm～1000sccm.
The thickness of described silicon nitride layer is
The method of the described silicon nitride layer of described removal is hot phosphoric acid wet etching.
According to second aspect of above-mentioned purpose, the invention also discloses a kind of method of adjustment of grating of semiconductor element, may further comprise the steps:
Set the shape of grid;
Be identified for making the stress that the polysilicon layer of grid should have according to described shape, be shaped as the bottom when having unfilled corner when described grid, described polysilicon layer should have tension stress, and when being shaped as the vertical or bottom of sidewall and having foot of described grid, described polysilicon layer should have compression; The stress that should have according to described polysilicon layer is determined the depositing temperature of silicon nitride layer; Depositing temperature deposited silicon nitride layer on the polysilicon layer that has deposited according to described silicon nitride layer; Remove silicon nitride layer; The etch polysilicon layer forms grid;
Shape to described formation grid detects;
The gate shapes that detection is obtained compares judgement with setting shape, and determines whether to adjust the depositing temperature of next group silicon nitride layer.
The described gate shapes that detection is obtained compares judgement with setting shape, and the concrete grammar that determines whether to adjust the depositing temperature of next group silicon nitride layer is:
The gate shapes that obtains when detection conforms to the gate shapes of setting, enters subsequent technique, and the depositing temperature of the described silicon nitride layer of maintenance next group device is constant;
The gate shapes bottom that obtains when detection is bigger than the gate shapes bottom of setting, and reduces the depositing temperature of the described silicon nitride layer of next group device;
The gate shapes bottom of comparing setting when the gate shapes bottom that detection obtains is little, the depositing temperature of the described silicon nitride layer of rising next group device.
Described detection utilizes optical signature size method to realize.
As seen from the above technical solutions, the manufacture method of a kind of grating of semiconductor element provided by the invention, compression and the tension stress of having utilized silicon nitride (SIN) to have, on the semiconductor gate oxide layer after the deposit spathic silicon layer, deposit the silicon nitride that one deck has stress again on polysilicon layer, this stress makes the polysilicon layer under the silicon nitride layer also have corresponding stress.So after silicon nitride layer was removed, the stress that polysilicon layer has still existed, utilize the difference of the stress that polysilicon layer has, can under identical etching condition, form and have difform polysilicon gate.It realizes that principle is: the stress of control silicon nitride layer changes the polysilicon layer stress under it thereupon.When polysilicon layer has different stress, polysilicon layer also can be different thereupon with the surface stress of intersection of gate oxide under it, if this stress is compression, the etch rate at the polysilicon of the intersection with stress during etching can be lower, and the result forms foot at intersection; Otherwise if this stress is tension stress, the etching polysilicon speed of this intersection can raise to some extent, and the result forms unfilled corner at intersection.In addition, when proper, can realize only remedying the grid unfilled corner phenomenon that the over etching polysilicon layer causes, form and have the gate shapes of vertical sidewall compression size control.Compared with prior art, eliminated when directly the polysilicon layer depositing temperature being adjusted because the type difference of polysilicon is brought a lot of negative effects, can form exactly have vertical sidewall, the bottom is the grid of foot or unfilled corner.
The method of adjustment of a kind of grating of semiconductor element provided by the invention, on the basis of manufacture method, utilize optical signature size method that the device grids bottom shape of producing is detected, and the shape of shape that can go out in actual fabrication and setting is to some extent during deviation, by adjusting stress kind and the size that this silicon nitride layer has, gate bottom shape to the next group device is adjusted, the gate bottom shape that finally obtains forming behind the etch polysilicon layer conforms to the shape of setting, more flexibly and accurately realizes desired gate bottom shape.
Description of drawings
Fig. 1 and Fig. 2 are the profile of the desirable device of formation of the manufacture method of prior art grating of semiconductor element.
Fig. 3 A and 3B are the schematic diagram of two kinds of common gate shapes.
Fig. 4 A to 4D is the device profile map of the manufacture method of embodiment of the invention semiconductor device grid.
Fig. 5 A to 5D is the device profile map of the manufacture method of the embodiment of the invention two grating of semiconductor element.
Fig. 6 is the flow chart of the method for adjustment of explanation grating of semiconductor element of the present invention.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The manufacture method of grating of semiconductor element provided by the invention, compression and the tension stress of having utilized silicon nitride (SIN) to have, on the semiconductor gate oxide layer after the deposit spathic silicon layer, deposit the silicon nitride that one deck has stress again on polysilicon layer, this stress makes the polysilicon layer under the silicon nitride layer also have corresponding stress.So after silicon nitride layer was removed, the stress that polysilicon layer has still existed, utilize the difference of the stress that polysilicon layer has, can under identical etching condition, form and have difform polysilicon gate.It realizes that principle is: the stress of control silicon nitride layer changes the polysilicon layer stress under it thereupon.When polysilicon layer has different stress, polysilicon layer also can be different thereupon with the surface stress of intersection of gate oxide under it, if this stress is compression, the etch rate at the polysilicon of the intersection with stress during etching can be lower, and the result forms foot at intersection; Otherwise if this stress is tension stress, the etching polysilicon speed of this intersection can raise to some extent, and the result forms unfilled corner at intersection.In addition, when proper, can realize only remedying the grid unfilled corner phenomenon that the over etching polysilicon layer causes, form and have the gate shapes of vertical sidewall compression size control.
The method of adjustment of a kind of grating of semiconductor element provided by the invention, on the basis of manufacture method, utilize optical signature size method that the device grids bottom shape of producing is monitored, and the shape of shape that can go out in actual fabrication and setting is to some extent during deviation, by adjusting the stress kind and the size of silicon nitride layer, gate bottom shape to the next group device is adjusted, and finally makes the gate bottom shape conform to the shape of setting.
Processing method of the present invention can be widely applied in many application; and can utilize many suitable materials and method to make; be to be illustrated below by preferred embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is encompassed in protection scope of the present invention far and away.
In order to obtain having the grid of optimum shape, be detailed description below to the manufacture method of grating of semiconductor element of the present invention.
Fig. 4 A to 4D is the device profile map of the manufacture method of embodiment of the invention semiconductor device grid.
In the present embodiment, the gate shapes of setting is the square configuration with vertical sidewall, so the silicon nitride layer of deposition should have certain compression.
Step 401 generates earlier gate oxide 102 on substrate 101, deposit spathic silicon layer 103 on this gate oxide 102 again is shown in Fig. 4 A.
In the present embodiment, polysilicon layer 103 is to utilize original chemical gaseous phase depositing process to obtain, and its thickness is determined by the gate height of requirement on devices.Technological parameter comprises: chamber pressure is 0.05Torr～0.5Torr, and the flow of silane is 50sccm～500sccm, and depositing temperature is 550 ℃～700 ℃, and sedimentation time is 500s～2000s.
Step 402, the silicon nitride layer 404 that deposition has compression on polysilicon layer 103 after silicon nitride layer 404 is carried out annealing in process, thereby makes polysilicon layer 103 also have corresponding compression, shown in Fig. 4 B.
In the present embodiment, the deposition of silicon nitride layer has been utilized the plasma enhanced chemical vapor deposition method.Its technological parameter comprises: chamber pressure is 1Torr～15Torr, radio-frequency power is 10W～200W, high frequency is 10MHZ～15MHZ, low frequency is 100KHZ～500KHZ, the flow of silane is 5sccm～100sccm, the flow of ammonia is 5sccm～50sccm, and the flow of nitrogen is 100sccm～1000sccm.The thickness of the silicon nitride layer of deposition is
Owing to can pass through Stress Transfer between silicon nitride layer and the polysilicon layer below it, polysilicon layer is had and the corresponding stress of silicon nitride layer, so growth conditions of control silicon nitride layer, as depositing temperature, reaction gas flow, chamber pressure etc., can realize the control of stress kind that silicon nitride layer is had and size, thus stress kind and size that the control polysilicon layer has.
Pass through the control of the depositing temperature realization of control silicon nitride layer in the present embodiment to polysilicon layer stress.Because need to generate the silicon nitride layer with compression, then the depositing temperature of this silicon nitride layer should be more than 600 ℃, and this compression increases along with the rising of temperature, and the corresponding foot that forms grid is also big more.
Step 403 is removed above-mentioned silicon nitride layer 404, shown in Fig. 4 C.In the present embodiment, remove above-mentioned silicon nitride layer with hot phosphoric acid wet method.
On polysilicon layer 103, make gate patterns by lithography, then utilize dry etching method etch polysilicon layer 103, when carrying out dry etching, still prolong and use original dry etching method with compression.Because polysilicon layer has had compression, its etch rate at polysilicon and gate oxide intersection is slower, when main etch process is finished, one foot can be formed on the bottom at polysilicon gate, therefore, added etching step after the main etching, and can make gate bottom originally because of the foot that etch rate forms slowly is cancelled, and finally form the grid 405 that conforms to the shape of the vertical sidewall of setting.
Fig. 5 A to 5D is the device profile map of the manufacture method of the embodiment of the invention two grating of semiconductor element.
In the present embodiment, the grid of setting is the shape with big unfilled corner, so the silicon nitride layer of deposition should have certain tension stress.
Step 501 generates earlier gate oxide 102 on substrate 101, deposit spathic silicon layer 103 on this gate oxide 102 again is shown in Fig. 5 A.
Step 502, the silicon nitride layer 404 that deposition has tension stress on polysilicon layer 103, silicon nitride layer 404 carried out annealing in process after, thereby make polysilicon layer 103 also have corresponding tension stress, shown in Fig. 5 B.
In the present embodiment, because need to generate the silicon nitride layer with tension stress, then the depositing temperature of this silicon nitride layer should be between 400 ℃ to 600 ℃, and this tension stress increases along with the reduction of temperature, and the corresponding unfilled corner that forms grid is also big more.
Step 503 is removed above-mentioned silicon nitride layer 404, shown in Fig. 5 C.
Step 504, have the polysilicon layer 103 of tension stress in formation after, etching polysilicon layer 103 forms the grid 505 with big unfilled corner, shown in Fig. 5 D.
Because polysilicon layer has had tension stress, its etch rate at polysilicon and gate oxide intersection is very fast, forms the grid with unfilled corner after the etching.The depositing temperature of control polysilicon layer is low more, and the gate bottom unfilled corner of formation is big more.
Fig. 6 is the flow chart of the method for adjustment of explanation grating of semiconductor element of the present invention, introduces a specific embodiment of this method of adjustment in detail below in conjunction with Fig. 6.
Step 602 is determined the stress that polysilicon layer should have by the gate bottom shape of setting.
When gate bottom required to unfilled corner, the stress of this polysilicon layer required to be tension stress, and the grid unfilled corner that need form is big more, and the tension stress that requires this polysilicon layer to have is also just big more; When gate bottom required to be vertical or foot shape, the stress of this polysilicon layer required to be compression, and needed the grid foot of formation big more, and the compression that requires this polysilicon layer to have is also just big more.In the present embodiment, formation be the grid that the bottom has big unfilled corner, thereby need polysilicon layer to have certain tension stress, suppose that this stress intensity is about 20MPa.
Step 603 requires to determine the depositing temperature of silicon nitride layer according to the stress of above-mentioned definite polysilicon layer.
When the stress of polysilicon layer required to tension stress, the depositing temperature of silicon nitride layer need be arranged between 400 ℃ to 600 ℃, and depositing temperature reduces along with the increase of the desired tension stress of polysilicon layer; When the stress of polysilicon layer required to compression, the depositing temperature of silicon nitride layer need be arranged on more than 600 ℃, and depositing temperature raises along with the increase of the desired compression of polysilicon layer.In the present embodiment, the polysilicon layer for growth has the tension stress of 20MPa must be arranged on the depositing temperature of silicon nitride layer about 550 ℃.
In the present embodiment, under 550 ℃ temperature, deposited the silicon nitride layer that has about 20MPa with tension stress.
Step 605 is removed silicon nitride layer.
But, consider that the gate lateral wall shape that forms after the etching can be subjected to influence of various factors, also can have influence on the gate shapes of device as the evenness of substrate surface, therefore, in actual fabrication, the situation that gate shapes that may occur producing and setting shape are not inconsistent, and this can cause departing from of device performance.For the device grids shape of guaranteeing to produce conforms to design shape, after etching forms grid, it is carried out sampling Detection, promptly carry out step 607, utilize optical signature size method that gate shapes is detected.This is the preferred embodiment of detection method, also can utilize additive method such as ESEM that the gate shapes of making is detected.
If the unfilled corner that forms is bigger than what set than the foot of setting little or that form, then execution in step 611, reduce the depositing temperature of silicon nitride layer, then according to the silicon nitride layer of this depositing temperature deposition next group device that has reduced; If the unfilled corner that forms is littler than what set than the foot of setting big or that form, then execution in step 612, and the depositing temperature of rising silicon nitride layer is then according to the silicon nitride layer of this depositing temperature deposition next group device that has raise.
In the present embodiment, find that if detect the gate bottom unfilled corner of producing is big inadequately, promptly gate bottom has only been dwindled 3nm than the top, compares with the 5nm that dwindles that sets, and the bottom unfilled corner of grid is littler than what set, so execution in step 612.Suitably reduce the depositing temperature of silicon nitride layer, as reduce to 520 ℃, and in the next group device, the temperature deposited silicon nitride layer is set according to this.
Through above-mentioned detect to adjust repeatedly after, finally can obtain and set the device that shape conforms to, after this, can carry out device production by the silicon nitride layer sedimentary condition that obtains by above-mentioned method of adjustment.
By the above embodiments as seen, the manufacture method of a kind of grating of semiconductor element provided by the invention, compression and the tension stress of having utilized silicon nitride (SIN) to have, on the semiconductor gate oxide layer after the deposit spathic silicon layer, deposit the silicon nitride that one deck has stress again on polysilicon layer, this stress makes the polysilicon layer under the silicon nitride layer also have corresponding stress.So after silicon nitride layer was removed, the stress that polysilicon layer has still existed, utilize the difference of the stress that polysilicon layer has, can under identical etching condition, form and have difform polysilicon gate.It realizes that principle is: the stress of control silicon nitride layer changes the polysilicon layer stress under it thereupon.When polysilicon layer has different stress, polysilicon layer also can be different thereupon with the surface stress of intersection of gate oxide under it, if this stress is compression, the etch rate at the polysilicon of the intersection with stress during etching can be lower, and the result forms foot at intersection; Otherwise if this stress is tension stress, the etching polysilicon speed of this intersection can raise to some extent, and the result forms unfilled corner at intersection.In addition, when proper, can realize only remedying the grid unfilled corner phenomenon that the over etching polysilicon layer causes, form and have the gate shapes of vertical sidewall compression size control.Compared with prior art, eliminated when directly the polysilicon layer depositing temperature being adjusted because the type difference of polysilicon is brought a lot of negative effects, can form exactly have vertical sidewall, the bottom is the grid of foot or unfilled corner.
The method of adjustment of a kind of grating of semiconductor element provided by the invention, on the basis of manufacture method, utilize optical signature size method that the device grids bottom shape of producing is detected, and the shape of shape that can go out in actual fabrication and setting is to some extent during deviation, by adjusting stress kind and the size that this silicon nitride layer has, gate bottom shape to the next group device is adjusted, the gate bottom shape that finally obtains forming behind the etch polysilicon layer conforms to the shape of setting, more flexibly and accurately realizes desired gate bottom shape.
The manufacture method of a kind of grating of semiconductor element provided by the invention and method of adjustment have been simplified device making technics, and implementation method is simple, and versatility is stronger.
Claims (11)
1. the manufacture method of a grating of semiconductor element generates after the gate oxide on substrate, it is characterized in that this method is further comprising the steps of:
Deposit spathic silicon layer on described gate oxide;
Deposition has the silicon nitride layer of stress on described polysilicon layer, makes described polysilicon layer have corresponding stress;
Remove described silicon nitride layer;
The described polysilicon layer of etching forms grid, and the shape of described grid determines that by the stress that described polysilicon layer has when described stress was tension stress, the gate bottom of formation had unfilled corner; When described stress was compression, the gate shapes of formation was that the vertical or bottom of sidewall has foot.
2. the method for claim 1, it is characterized in that, the stress that described polysilicon layer has is determined by the depositing temperature of described silicon nitride layer, when described silicon nitride layer depositing temperature at 400 ℃ between 600 ℃ the time, described polysilicon layer has tension stress, and described tension stress increases with the reduction of temperature; When described silicon nitride layer depositing temperature more than 600 ℃ the time, described polysilicon layer has compression, and described compression increases with the rising of temperature.
3. the method for claim 1 is characterized in that, described deposition has after the silicon nitride layer of stress, and this method further comprises the step of described silicon nitride layer being carried out annealing in process.
4. the method for claim 1, it is characterized in that, the method of described deposit spathic silicon layer is a chemical vapour deposition technique, technological parameter comprises: chamber pressure is 0.05Torr～0.5Torr, the flow of silane is 50sccm～500sccm, depositing temperature is 550 ℃～700 ℃, and sedimentation time is 500s～2000s.
5. the method for claim 1 is characterized in that, the method that described deposition has the silicon nitride layer of stress is the plasma enhanced chemical vapor deposition method.
6. method as claimed in claim 5, it is characterized in that, the technological parameter of described deposition process comprises: chamber pressure is 1Torr～15Torr, radio-frequency power is 10W～200W, high frequency is 10MHZ～15MHZ, and low frequency is 100KHZ～500KHZ, and the flow of silane is 5sccm～100sccm, the flow of ammonia is 5sccm～50sccm, and the flow of nitrogen is 100sccm～1000sccm.
7. the method for claim 1 is characterized in that, the thickness of described silicon nitride layer is
～
8. the method for claim 1 is characterized in that, the method for the described silicon nitride layer of described removal is hot phosphoric acid wet etching.
9. the method for adjustment of a grating of semiconductor element is characterized in that, may further comprise the steps:
Set the shape of grid;
Be identified for making the stress that the polysilicon layer of grid should have according to described shape, be shaped as the bottom when having unfilled corner when described grid, described polysilicon layer should have tension stress, and when being shaped as the vertical or bottom of sidewall and having foot of described grid, described polysilicon layer should have compression; The stress that should have according to described polysilicon layer is determined the depositing temperature of silicon nitride layer; Depositing temperature deposited silicon nitride layer on the polysilicon layer that has deposited according to described silicon nitride layer; Remove silicon nitride layer; The etch polysilicon layer forms grid;
Shape to described formation grid detects;
The gate shapes that detection is obtained compares judgement with setting shape, and determines whether to adjust the depositing temperature of next group silicon nitride layer.
10. method as claimed in claim 9 is characterized in that, the described gate shapes that detection is obtained compares judgement with setting shape, and the concrete grammar that determines whether to adjust the depositing temperature of next group silicon nitride layer is:
The gate shapes that obtains when detection conforms to the gate shapes of setting, enters subsequent technique, and the depositing temperature of the described silicon nitride layer of maintenance next group device is constant;
The gate shapes bottom that obtains when detection is bigger than the gate shapes bottom of setting, and reduces the depositing temperature of the described silicon nitride layer of next group device;
The gate shapes bottom of comparing setting when the gate shapes bottom that detection obtains is little, the depositing temperature of the described silicon nitride layer of rising next group device.
11. method as claimed in claim 9 is characterized in that, described detection utilizes optical signature size method to realize.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681413A (en) * | 2015-02-25 | 2015-06-03 | 苏州工业园区纳米产业技术研究院有限公司 | Preparing method of low-stress polycrystalline silicon film |
| US11031162B2 (en) | 2014-11-27 | 2021-06-08 | Posco | Grain-oriented electrical steel sheet and manufacturing method therefor |
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2008
- 2008-10-21 CN CN200810224594A patent/CN101728253A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11031162B2 (en) | 2014-11-27 | 2021-06-08 | Posco | Grain-oriented electrical steel sheet and manufacturing method therefor |
| CN104681413A (en) * | 2015-02-25 | 2015-06-03 | 苏州工业园区纳米产业技术研究院有限公司 | Preparing method of low-stress polycrystalline silicon film |
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Application publication date: 20100609 |