CN103515193A - Semiconductor device fine pattern manufacturing method - Google Patents

Semiconductor device fine pattern manufacturing method Download PDF

Info

Publication number
CN103515193A
CN103515193A CN201210219509.6A CN201210219509A CN103515193A CN 103515193 A CN103515193 A CN 103515193A CN 201210219509 A CN201210219509 A CN 201210219509A CN 103515193 A CN103515193 A CN 103515193A
Authority
CN
China
Prior art keywords
layer
hard mask
fine pattern
side wall
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201210219509.6A
Other languages
Chinese (zh)
Other versions
CN103515193B (en
Inventor
张海洋
王新鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201210219509.6A priority Critical patent/CN103515193B/en
Publication of CN103515193A publication Critical patent/CN103515193A/en
Application granted granted Critical
Publication of CN103515193B publication Critical patent/CN103515193B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention discloses a semiconductor device fine pattern manufacturing method. The method comprises the steps of sequentially depositing polycrystalline silicon layers on a semiconductor substrate, forming a patterned hard mask layer, defining the position of the (odd number)th line of a fine pattern according to the width of the patterned hard mask layer, using the patterned hard mask layer as a mask, etching the polycrystalline layers until the semiconductor substrate is exposed, pruning the etched polycrystalline layers to reach the target line widths, filling an oxide layer between the polycrystalline layers with the target line widths, forming side wall layers on the two sides of the patterned hard mask layer, defining the (even number)th line width of the fine pattern in a gap between side wall layers, jointly using the side wall layers and the patterned hard mask layer as masks, etching the exposed oxide layer until the semiconductor substrate is exposed, depositing the polycrystalline layers again, filling the etched positions of the oxide layer to form the (even number)th line, and using chemical machinery to grind and remove the side wall layers and the hard mask layer to form the fine pattern. The semiconductor device fine pattern manufacturing method can reduce LWR of the fine pattern.

Description

The manufacture method of delicate pattern of semi-conductor device
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly a kind of manufacture method of delicate pattern of semi-conductor device.
Background technology
At present, the fine pattern for being formed by line (line) alternately and interval (space) on substrate, generally adopts self-aligned double patterning case (SADP, Self-Aligned Double Patterning) technology.
The method that existing employing SADP technology forms fine pattern comprises the following steps, and below in conjunction with Fig. 1 a to Fig. 1 e, describes.
Step 11, refer to Fig. 1 a, deposition-etch destination layer 101 in Semiconductor substrate 100.
Step 12, refer to Fig. 1 b, deposition of sacrificial layer 102, coating photoresistance glue-line (not shown) successively on the surface of etching target 101, and photoresistance glue-line described in exposure imaging patterning, the photoresistance glue-line width of patterning is for defining the interval of fine pattern; The photoresistance glue-line of patterning of take is mask, and sacrifice layer 102 forms the sacrifice layer 102 of patternings described in etching.Wherein, sacrifice layer is generally oxide layer.
Step 13, refer to Fig. 1 c, in sacrifice layer 102 surfaces of patterning and the etching target 101 surface deposition side wall layer 103 that manifest, and side wall layer 103 described in anisotropic etching, make to be positioned at through the side wall layer 103 of over etching sacrifice layer 102 both sides of patterning, the live width that its width is fine pattern.Wherein, side wall layer is generally nitration case.From figure, also can find out, the gap length between sides adjacent parietal layer 103 has defined the interval of fine pattern equally.
Step 14, refer to Fig. 1 d, wet method is removed the sacrifice layer 102 of patterning.Because sacrifice layer is generally oxide layer, side wall layer is generally nitration case, so adopt hydrofluoric acid to remove the sacrifice layer 102 of patterning, when can guarantee to remove sacrifice layer 102, side wall layer is not removed.
Step 15, refer to Fig. 1 e, the side wall layer 103 of take after etching is mask, and etching target is carried out to etching, forms fine pattern.From foregoing description, can find out, the gap length between the sides adjacent parietal layer 103 after etching has defined the interval of fine pattern, and the width of the side wall layer 103 after etching has defined the live width of fine pattern.
Based on above-mentioned explanation, existing SADP technology is more complicated, implements production efficiency lower.And side wall layer 103, through after incorgruous etching, need to keep vertical and regular shape, defines the live width of fine pattern, this point, for incorgruous etching technics, is difficult to realize well.Further, side wall layer 103 is deposited on sacrifice layer 102 surfaces of patterning and etching target 101 surfaces that manifest, fine pattern for smaller szie, etching target 101 face widths that manifest are very narrow, the thickness evenness depositing on side wall layer 103Gai position will be very poor, thereby very difficult etching obtains the side wall layer of ideal form.So the side wall layer of finally take after etching is mask, when etching target 101 is carried out to etching, be difficult to obtain the fine pattern of ideal dimensions, the sidewall roughness of fine pattern (line wall roughness in other words, LWR) very high, if overlooked, will find on fine pattern You position very on Zhai，You position very wide.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of delicate pattern of semi-conductor device, can reduce the sidewall roughness of fine pattern.
Technical scheme of the present invention is achieved in that
A manufacture method for delicate pattern of semi-conductor device, described fine pattern is interval and line alternately, the method comprises:
Deposit spathic silicon layer successively in Semiconductor substrate, and form the hard mask layer of patterning; The width definition fine pattern odd number Xian position of the hard mask layer of patterning;
The hard mask layer of patterning of take is mask, and etch polysilicon layer is to manifesting Semiconductor substrate;
To pruning to reach target live width through the polysilicon layer of over etching, wherein, the method for pruning comprises: oxidation polysilicon layer sidewall, form silicon oxide layer sidewall, and make unoxidized polysilicon layer width equal target live width; Wet etching is removed silicon oxide layer sidewall; Adopt the unoxidized polysilicon layer sidewall of washed with de-ionized water;
Filling oxide layer between the polysilicon layer with target live width;
Both sides at the hard mask layer of patterning form side wall layer, the space definition fine pattern even number live width between side wall layer;
Using the hard mask layer of side wall layer and patterning jointly as mask, the oxide layer manifesting is etched to and manifests Semiconductor substrate;
Deposit spathic silicon layer again, is filled in the position of oxide layer after being etched, and forms even number line;
Cmp removes side wall layer and hard mask layer forms fine pattern.
Described wet etching is removed silicon oxide layer sidewall and is adopted hydrofluoric acid or hydrochloric acid.
Filling oxide layer adopts spin coating method, and returns and carve oxide layer to manifest the hard mask layer of patterning.
Adopt polysilicon to form side wall layer, the method further comprises: offside parietal layer is pruned, and makes the space between side wall layer reach target live width.
Described hard mask layer is silicon nitride layer.
The oxide layer manifesting is carried out to etching and adopt dry etching.
From such scheme, can find out, the present invention prunes the line of fine pattern, to reach target live width.Pruning method is softer, and the LWR therefore obtaining is lower, thereby reaches object of the present invention.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 e is the generalized section that existing employing SADP technology forms fine pattern;
Fig. 2 is the schematic flow sheet of embodiment of the present invention delicate pattern of semi-conductor device manufacture method;
Fig. 2 a to Fig. 2 h is the generalized section that the embodiment of the present invention forms delicate pattern of semi-conductor device.
Embodiment
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
The schematic flow sheet of embodiment of the present invention delicate pattern of semi-conductor device manufacture method as shown in Figure 2, is elaborated below in conjunction with Fig. 2 a to Fig. 2 h, and it comprises the following steps:
Step 21, refer to Fig. 2 a, deposit spathic silicon layer 201 successively in Semiconductor substrate 200, and form the hard mask layer 202 of patterning; The width definition fine pattern odd number Xian position of the hard mask layer 202 of patterning;
Hard mask layer can be silicon nitride layer.Concrete grammar can be: deposit spathic silicon layer and hard mask layer successively in Semiconductor substrate 200, surface-coated photoresistance glue-line at hard mask layer, and photoresistance glue-line described in exposure imaging patterning, the width definition fine pattern odd number Xian position of patterning photoresistance glue-line; The photoresistance glue-line of patterning of take is mask, and etching hard mask layer forms the hard mask layer 202 of patterning.
Step 22, refer to Fig. 2 b, the hard mask layer 202 of patterning of take is mask, and etch polysilicon layer 201 is to manifesting Semiconductor substrate 200;
Step 23, refer to Fig. 2 c, polysilicon layer 201 through over etching is pruned to (trim) to reach target live width, and wherein, the method for pruning comprises: oxidation polysilicon layer sidewall, form silicon oxide layer sidewall, make unoxidized polysilicon layer width equal target live width; Wet etching is removed silicon oxide layer sidewall; Adopt the unoxidized polysilicon layer sidewall of washed with de-ionized water;
This step is key of the present invention, and in step 21, the width of the hard mask layer 202 of patterning not necessarily can reach target live width, so in this step, can carry out fine pruning to the polysilicon layer 201 through over etching, to reach target live width.First adopt two sidewalls of dioxygen oxidation polysilicon layer, make unoxidized polysilicon layer width equal target live width, the flow control of oxygen is carried out as required; Then adopt hydrofluoric acid or hydrochloric acid wet method to remove this layer of silicon oxide layer sidewall; Finally adopt the unoxidized polysilicon layer sidewall of washed with de-ionized water.During oxidation, can accurately control the width of adjusting line, adopt hydrofluoric acid or hydrochloric acid wet method to remove this layer of silicon oxide layer sidewall and remove gradually silicon oxide layer just as sand polishing, therefore compared with prior art, the LWR of line is effectively reduced.
Step 24, refer to Fig. 2 d, between the polysilicon layer with target live width, filling oxide layer 203;
Preferably, filling oxide layer adopts spin coating method, and the hard mask layer 202 of the oxide layer overlay pattern of spin coating, so need back to carve oxide layer to manifest the hard mask layer of patterning.In addition, filling oxide layer also can adopt chemical gaseous phase depositing process.
Step 25, refer to Fig. 2 e, in the hard mask layer 202 both sides of patterning, form side wall layer 204, the space definition fine pattern even number live width between side wall layer 204;
In the embodiment of the present invention, side wall layer 204 can adopt polysilicon, because the definition of the space between this step side wall layer 204 fine pattern even number live width, so still can be as in step 23, an oxidation part is as the polysilicon of side wall layer, and then this part silica is removed, make the space between side wall layer reach target live width.Certainly, also can directly make the space between side wall layer reach target live width.
Step 26, refer to Fig. 2 f, using the hard mask layer 202 of side wall layer 204 and patterning jointly as mask, the oxide layer 203 manifesting is etched to and manifests Semiconductor substrate 200;
The oxide layer 203 that this step adopts dry etching to manifest.
Step 27, refer to Fig. 2 g, deposit spathic silicon layer 201 again, are filled in the position of oxide layer after being etched, and form even number line;
Step 28, refer to Fig. 2 h, cmp removes side wall layer 204 and hard mask layer 202 forms fine patterns.
So far, fine pattern of the present invention completes.Fine pattern is interval and line alternately, and the line consisting of polysilicon layer 201 is alternately in the interval consisting of oxide layer 203.
To sum up, the fine pattern that adopts method of the present invention to form, can first define odd number Xian position substantially; And then prune odd number line to reach target live width, and during pruning, wet etching is removed silicon oxide layer sidewall, and method is softer, make gradually odd number line reach target live width, so LWR is lower.While further utilizing the space definition fine pattern even number live width between side wall layer, also can prune by offside parietal layer, make even number line reach target live width.Therefore, the line of fine pattern of the present invention can be by regulating and form accurate size flexibly, so accuracy is higher.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.

Claims (6)

1. a manufacture method for delicate pattern of semi-conductor device, described fine pattern is interval and line alternately, the method comprises:
Deposit spathic silicon layer successively in Semiconductor substrate, and form the hard mask layer of patterning; The width definition fine pattern odd number Xian position of the hard mask layer of patterning;
The hard mask layer of patterning of take is mask, and etch polysilicon layer is to manifesting Semiconductor substrate;
To pruning to reach target live width through the polysilicon layer of over etching, wherein, the method for pruning comprises: oxidation polysilicon layer sidewall, form silicon oxide layer sidewall, and make unoxidized polysilicon layer width equal target live width; Wet etching is removed silicon oxide layer sidewall; Adopt the unoxidized polysilicon layer sidewall of washed with de-ionized water;
Filling oxide layer between the polysilicon layer with target live width;
Both sides at the hard mask layer of patterning form side wall layer, the space definition fine pattern even number live width between side wall layer;
Using the hard mask layer of side wall layer and patterning jointly as mask, the oxide layer manifesting is etched to and manifests Semiconductor substrate;
Deposit spathic silicon layer again, is filled in the position of oxide layer after being etched, and forms even number line;
Cmp removes side wall layer and hard mask layer forms fine pattern.
2. the method for claim 1, is characterized in that, described wet etching is removed silicon oxide layer sidewall and adopted hydrofluoric acid or hydrochloric acid.
3. method as claimed in claim 1 or 2, is characterized in that, filling oxide layer adopts spin coating method, and returns and carve oxide layer to manifest the hard mask layer of patterning.
4. method as claimed in claim 3, is characterized in that, adopts polysilicon to form side wall layer, and the method further comprises: offside parietal layer is pruned, and makes the space between side wall layer reach target live width.
5. the method for claim 1, is characterized in that, described hard mask layer is silicon nitride layer.
6. the method for claim 1, is characterized in that, the oxide layer manifesting is carried out to etching and adopt dry etching.
CN201210219509.6A 2012-06-28 2012-06-28 The manufacture method of delicate pattern of semi-conductor device Active CN103515193B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210219509.6A CN103515193B (en) 2012-06-28 2012-06-28 The manufacture method of delicate pattern of semi-conductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210219509.6A CN103515193B (en) 2012-06-28 2012-06-28 The manufacture method of delicate pattern of semi-conductor device

Publications (2)

Publication Number Publication Date
CN103515193A true CN103515193A (en) 2014-01-15
CN103515193B CN103515193B (en) 2016-03-30

Family

ID=49897730

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210219509.6A Active CN103515193B (en) 2012-06-28 2012-06-28 The manufacture method of delicate pattern of semi-conductor device

Country Status (1)

Country Link
CN (1) CN103515193B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298467A (en) * 2015-05-28 2017-01-04 联华电子股份有限公司 The manufacture method of semiconductor element pattern
CN108231537A (en) * 2017-12-05 2018-06-29 中国电子科技集团公司第五十五研究所 Improve the preparation method of polysilicon sidewall roughness
CN110783257A (en) * 2018-07-24 2020-02-11 爱思开海力士有限公司 Semiconductor device with symmetrical conductive interconnection pattern

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060117018A (en) * 2005-05-12 2006-11-16 삼성전자주식회사 Method of forming fine pattern of semiconductor device
KR20090045780A (en) * 2007-11-02 2009-05-08 주식회사 하이닉스반도체 Method for forming fine pattern in semiconductor device
CN101840890A (en) * 2008-12-30 2010-09-22 东部高科股份有限公司 Method for fabricating flash memory device
KR101017753B1 (en) * 2007-09-12 2011-02-28 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
US20110223769A1 (en) * 2010-03-15 2011-09-15 Ko Nikka Method of fabricating a semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060117018A (en) * 2005-05-12 2006-11-16 삼성전자주식회사 Method of forming fine pattern of semiconductor device
KR101017753B1 (en) * 2007-09-12 2011-02-28 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
KR20090045780A (en) * 2007-11-02 2009-05-08 주식회사 하이닉스반도체 Method for forming fine pattern in semiconductor device
CN101840890A (en) * 2008-12-30 2010-09-22 东部高科股份有限公司 Method for fabricating flash memory device
US20110223769A1 (en) * 2010-03-15 2011-09-15 Ko Nikka Method of fabricating a semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298467A (en) * 2015-05-28 2017-01-04 联华电子股份有限公司 The manufacture method of semiconductor element pattern
CN106298467B (en) * 2015-05-28 2019-10-18 联华电子股份有限公司 The production method of semiconductor element pattern
CN108231537A (en) * 2017-12-05 2018-06-29 中国电子科技集团公司第五十五研究所 Improve the preparation method of polysilicon sidewall roughness
CN110783257A (en) * 2018-07-24 2020-02-11 爱思开海力士有限公司 Semiconductor device with symmetrical conductive interconnection pattern
CN110783257B (en) * 2018-07-24 2023-11-17 爱思开海力士有限公司 Semiconductor device having symmetrical conductive interconnect patterns

Also Published As

Publication number Publication date
CN103515193B (en) 2016-03-30

Similar Documents

Publication Publication Date Title
TWI409852B (en) Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning
CN103839781A (en) Method for forming fine patterns on semiconductor
CN104078366B (en) The fin structure manufacture method of Dual graphing fin transistor
CN102347217A (en) Method for making fine pattern on semiconductor device
CN104459854A (en) Preparation method of metal grating
CN105118775A (en) A shield grid transistor formation method
CN103515193B (en) The manufacture method of delicate pattern of semi-conductor device
US9023224B2 (en) Method of forming a spacer patterning mask
CN104078329B (en) The forming method of autoregistration multiple graphics
CN103681274B (en) Semiconductor device manufacturing method
KR20090089497A (en) Method for fabricating fine pattern in semiconductor device
CN104347362A (en) Manufacturing method of small-dimension pattern
CN104425218B (en) The dual pattern process of semiconductor structure
CN104701145B (en) The forming method of semiconductor structure
CN104078330B (en) The forming method of the triple figures of autoregistration
US11011601B2 (en) Narrow gap device with parallel releasing structure
CN104064474B (en) The fin structure manufacture method of Dual graphing fin transistor
CN102693932B (en) Manufacturing method of shallow trench isolation structure
CN108091553B (en) Method for forming mask pattern
CN104282613A (en) Semiconductor manufacturing method
JP6123242B2 (en) Pattern formation method
CN105206512A (en) Method for improving multiple patterned mask layers
CN109003894A (en) A kind of process improving double-pattern etching core model top fillet
CN106960816B (en) The method of Dual graphing
CN107527802A (en) Groove type double-layer grid MOS film build methods

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant