KR101017753B1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR101017753B1
KR101017753B1 KR1020070092664A KR20070092664A KR101017753B1 KR 101017753 B1 KR101017753 B1 KR 101017753B1 KR 1020070092664 A KR1020070092664 A KR 1020070092664A KR 20070092664 A KR20070092664 A KR 20070092664A KR 101017753 B1 KR101017753 B1 KR 101017753B1
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South Korea
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pattern
forming
spacer
material layer
etching
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KR1020070092664A
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Korean (ko)
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KR20090027442A (en
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윤형순
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

본 발명은 스페이서가 형성되는 층을 다층으로 형성하고 언더 컷 구조를 형성하여 스페이서 하부의 두께를 증가시켜 패턴의 CD(Critical Dimension)를 증가시킬 수 있는 기술을 개시한다.The present invention discloses a technique of increasing the thickness of the bottom of the spacer by forming a layer in which the spacer is formed in multiple layers and forming an undercut structure to increase the CD (Critical Dimension) of the pattern.

DPT, SPT, 언더 컷, 스페이서, CD DPT, SPT, Under Cut, Spacer, CD

Description

반도체 소자 형성 방법{Method for manufacturing semiconductor device}Method for manufacturing semiconductor device

도 1a 내지 도 1e는 일반적인 SPT를 이용하는 반도체 소자 형성 방법을 나타낸 단면도들이다.1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device using a general SPT.

도 2a 내지 도 2f는 본 발명에 따른 SPT를 이용하는 반도체 소자 형성 방법을 나타낸 단면도들이다.2A to 2F are cross-sectional views illustrating a method of forming a semiconductor device using an SPT according to the present invention.

<도면의 주요 부분에 대한 부호 설명>Description of the Related Art [0002]

22: 피식각층22: etching layer

24: 산화막24: oxide film

25: 산화막 패턴25: oxide film pattern

26: 다결정 실리콘막26: polycrystalline silicon film

27: 다결정 실리콘막 패턴27: polycrystalline silicon film pattern

28: 감광막 패턴28: photosensitive film pattern

30: 스페이서30: spacer

32: 패턴32: pattern

본 발명은 반도체 소자 형성 방법에 관한 것으로, 더욱 상세하게는 다중 노광 공정(Multi Exposure Technology; MET)에 의한 SPT(Spacer Patterning Technology)를 통해 스페이서의 두께를 조절하여 패턴의 CD(Critical Dimension)를 조절할 수 있는 반도체 소자 형성 방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, and more particularly, to control a CD (Critical Dimension) of a pattern by controlling a thickness of a spacer through a SPT (Spacer Patterning Technology) by a multi exposure technology (MET). It relates to a method for forming a semiconductor device that can be.

일반적으로, 반도체 제조 공정은 가공(fabrication), 전기적 다이 분류(electrical die sorting), 조립(assembly) 및 검사(test)로 구분된다.In general, semiconductor manufacturing processes are divided into fabrication, electrical die sorting, assembly, and testing.

가공 공정은 웨이퍼에 확산, 사진, 식각, 박막 공정 등을 여러 차례 반복 진행하면서 전기 회로들을 형성하여 웨이퍼 상태에서 전기적으로 완전하게 동작하는 반제품이 만들어지는 모든 과정을 말한다.The machining process refers to all processes in which electrical circuits are formed by repeatedly performing diffusion, photographing, etching, and thin film processes on a wafer to produce semi-finished products that are fully electrically operated in a wafer state.

한편, 반도체 소자가 고집적화됨에 따라 회로를 구성하는 패턴의 크기 및 간격(pitch)이 점점 감소하고 있다. On the other hand, as semiconductor devices are highly integrated, the size and pitch of the patterns constituting the circuit are gradually decreasing.

또한, 반도체 소자가 고집적화됨에 따라 가공 공정 중 사진 공정 기술은 마스크 설계를 정교하게 해줌으로써 마스크를 통해 나오는 빛의 양을 적절히 조절하고, 새로운 감광제의 개발, 고구경(high numerical aperture) 렌즈를 사용하는 스캐너(scanner)의 개발, 변형된 마스크를 개발하는 등의 노력에 의해 반도체 소자 제조 장치가 갖고 있는 기술적인 한계를 극복하고 있다.In addition, as semiconductor devices become more integrated, photo-processing techniques in the machining process refine the mask design to properly control the amount of light exiting the mask, develop new photosensitizers, and use high numerical aperture lenses. By developing a scanner, developing a modified mask, and the like, the technical limitations of the semiconductor device manufacturing apparatus are overcome.

하지만, 현재 사용되는 광원, 예를 들어 KrF, ArF 등을 사용하여 진행하는 노광 및 해상 능력의 한계로 인하여 원하는 패턴의 폭 및 간격을 형성하기 어려운 실정이다. However, due to limitations in exposure and resolution ability that proceed with current light sources, for example, KrF, ArF, etc., it is difficult to form a width and an interval of a desired pattern.

이에 미세한 패턴의 크기 및 간격을 갖는 감광막 패턴을 형성하기 위한 여러 가지 연구가 계속되고 있다. Accordingly, various studies for forming a photosensitive film pattern having a fine pattern size and spacing are continued.

그 중의 한 가지 방법은 두 번의 사진 공정을 수행하여 패턴을 형성하는 DPT(Double Patterning Technology) 방법이 있고, 다른 방법으로는 스페이서를 이용하여 패턴을 형성하는 SPT(Spacer Patterning Technology)가 사용되고 있다.One method is a double patterning technology (DPT) method for forming a pattern by performing two photographic processes, and another method is a space patterning technology (SPT) for forming a pattern using a spacer.

도 1a 내지 도 1e는 일반적인 SPT를 이용하는 반도체 소자 형성 방법을 나타낸 단면도들이다.1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device using a general SPT.

도 1a를 참조하면, 피식각층(12) 상부에 산화막을 증착하고, 사진 및 식각 공정을 통해 산화막 패턴(14)을 형성한다. Referring to FIG. 1A, an oxide layer is deposited on an etched layer 12, and an oxide layer pattern 14 is formed through a photolithography and an etching process.

도 1b 및 도 1c를 참조하면, 산화막 패턴(14) 측벽에 스페이서(16)를 형성하고, 산화막 패턴(14)을 제거한다. 1B and 1C, spacers 16 are formed on sidewalls of the oxide film pattern 14, and the oxide film pattern 14 is removed.

도 1d 및 도 1e를 참조하면, 스페이서(16)를 식각 마스크로 사용하여 피식각층(12)을 식각하고 스페이서(16)를 제거하여 원하는 피식각층 패턴(18)을 형성한다. 여기서, 피식각층(12)에 형성된 패턴(8)의 크기(critical dimension; CD)는 스페이서(16)의 두께에 의해 결정된다. 즉, 스페이서(16)의 두께에 따라서 패턴(18)의 CD(critical dimension)가 정해지기 때문에 스페이서(16)의 두께와 동일한 CD의 패턴(18)이 형성된다. 1D and 1E, the etching target layer 12 is etched using the spacer 16 as an etching mask and the spacer 16 is removed to form the desired etching pattern layer 18. Here, the critical dimension (CD) of the pattern 8 formed on the etched layer 12 is determined by the thickness of the spacer 16. That is, since the CD (critical dimension) of the pattern 18 is determined according to the thickness of the spacer 16, the pattern 18 of the same CD as the thickness of the spacer 16 is formed.

상기와 같은 일반적인 SPT를 이용할 경우 스페이서의 두께에 따라서 라인 패턴의 CD(critical dimension)가 정해지기 때문에 일반적인 작은 크기의 라인/스페이스 패터닝에는 적용할 수 있지만, 큰 크기(CD)의 패턴을 형성하기 위해서는 스페이서의 두께를 두껍게 형성해야하지만 스페이서의 두께를 증가시키는데에는 한계가 있는 문제점이 있다.In the case of using the general SPT as described above, since the CD (critical dimension) of the line pattern is determined according to the thickness of the spacer, it is applicable to general small size line / space patterning, but to form a large size (CD) pattern Although the thickness of the spacer should be formed thick, there is a problem in that there is a limit in increasing the thickness of the spacer.

본 발명은 스페이서가 형성되는 층을 다층으로 형성하고 언더 컷 구조를 형성하여 스페이서 하부의 두께를 증가시켜 패턴의 CD를 증가시킬 수 있는 반도체 소자 형성 방법을 제공하는 것을 목적으로 한다.An object of the present invention is to provide a method for forming a semiconductor device capable of increasing the thickness of the lower portion of the spacer by forming a layer in which the spacer is formed in multiple layers and forming an undercut structure to increase the CD of the pattern.

본 발명에 따른 반도체 소자 형성 방법은 The method of forming a semiconductor device according to the present invention

피식각층 상부에 식각비가 서로 다른 제 1 물질 층 및 제 2 물질 층을 순차적으로 형성하는 단계;Sequentially forming a first material layer and a second material layer having different etching ratios on the etched layer;

상기 제 2 물질 층 및 상기 제 1 물질 층을 순차적으로 식각하여 제 1 패턴을 형성하는 단계;Sequentially etching the second material layer and the first material layer to form a first pattern;

상기 제 1 패턴의 상기 제 1 물질 층에 대해 선택 식각 공정을 수행하여 언더 컷(under cut) 구조를 형성하는 단계;Performing a selective etching process on the first material layer of the first pattern to form an under cut structure;

상기 언더 컷 구조를 갖는 상기 제 1 패턴 측벽에 스페이서를 형성하는 단계;Forming a spacer on the first pattern sidewall having the undercut structure;

상기 제 1 패턴을 제거하는 단계; 및 Removing the first pattern; And

상기 스페이서를 이용하여 상기 피식각층을 식각하여 제 2 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다. And etching the etched layer using the spacers to form a second pattern.

또한, 상기 제 1 패턴을 형성하는 단계는 In addition, the step of forming the first pattern

상기 제 2 물질 층 상부에 감광막을 도포하고, 노광 및 현상 공정을 통해 감 광막 패턴을 형성하는 단계; 및Applying a photoresist film over the second material layer and forming a photoresist pattern through an exposure and development process; And

상기 감광막 패턴을 식각 마스크로 이용하여 상기 제 2 물질 층 및 상기 제 1 물질 층을 순차적으로 식각하는 단계를 포함하고,Sequentially etching the second material layer and the first material layer by using the photoresist pattern as an etching mask,

상기 제 1 물질 및 상기 제 2 물질은 금속, 다결정 실리콘, 산화막, 질화막, 비정질 탄소 중의 어느 하나로 각각 형성하고,The first material and the second material are each formed of any one of metal, polycrystalline silicon, oxide film, nitride film, and amorphous carbon,

상기 제 1 물질 층은 다수의 층으로 형성하는 것을 특징으로 한다.The first material layer is formed of a plurality of layers.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명은 여기서 설명되는 실시예에 한정되지 않고 다른 형태로 구체화될 수 있다. 오히려, 여기서 소개되는 실시예는 본 발명의 기술적 사상이 철저하고 완전하게 개시되고 당업자에게 본 발명의 사상이 충분히 전달되기 위해 제공되는 것이다. 또한, 명세서 전체에 걸쳐서 동일한 참조 번호들은 동일한 구성요소를 나타낸다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

본 발명은 스페이서가 형성되는 층을 다층으로 형성하고 언더 컷 구조를 형성하여 스페이서 하부의 두께를 증가시켜 패턴의 CD를 증가시킬 수 있는 기술을 개시한다. The present invention discloses a technique of increasing the thickness of the bottom of the spacer by forming a layer in which the spacer is formed in multiple layers and forming an undercut structure to increase the CD of the pattern.

도 2a 내지 도 2f는 본 발명에 따른 SPT를 이용하는 반도체 소자 형성 방법을 나타낸 단면도들이다.2A to 2F are cross-sectional views illustrating a method of forming a semiconductor device using an SPT according to the present invention.

도 2a를 참조하면, 피식각층(22) 상부에 산화막(24) 및 다결정 실리콘막(26)을 증착하고, 다결정 실리콘막(26) 상부에 감광막을 도포하고, 노광 및 현상 공정을 통해 감광막 패턴(28)을 형성한다. 여기서는 피식각층(22) 상부에 형성하는 두 개의 층을 산화막(24) 및 다결정 실리콘막(26)을 예를 들어 설명하였지만, 필요에 따라 식각비가 서로 다른 임의의 두 개의 물질, 예를 들어 금속, 질화막, 비정질 탄소 등을 선택하여 사용할 수 있다.Referring to FIG. 2A, an oxide film 24 and a polycrystalline silicon film 26 are deposited on the etched layer 22, a photosensitive film is coated on the polycrystalline silicon film 26, and a photosensitive film pattern ( 28). Here, the two layers formed on the etched layer 22 are described using the oxide film 24 and the polycrystalline silicon film 26 as an example. However, as required, any two materials having different etching ratios, for example, metals, A nitride film, amorphous carbon, etc. can be selected and used.

도 2b를 참조하면, 감광막 패턴(28)을 식각 마스크로 이용하여 다결정 실리콘막(26) 및 산화막(24)을 순차적으로 식각하여 산화막 패턴(25) 및 다결정 실리콘막 패턴(27)을 형성하고, 감광막 패턴(28)은 제거한다. Referring to FIG. 2B, the polycrystalline silicon film 26 and the oxide film 24 are sequentially etched using the photoresist pattern 28 as an etching mask to form an oxide film pattern 25 and a polycrystalline silicon film pattern 27. The photosensitive film pattern 28 is removed.

도 2c를 참조하면, 산화막 패턴(25)에 대해 불화수소(HF) 또는 BOE(Buffer Oxide Etchant) 용액을 이용한 세정 공정을 30초 내지 5분 동안 수행하여 언더 컷(under-cut) 구조를 형성한다.Referring to FIG. 2C, an under-cut structure is formed by performing a cleaning process using hydrogen fluoride (HF) or a buffer oxide etch (BOE) solution for 30 seconds to 5 minutes on the oxide layer pattern 25. .

도 2d를 참조하면, 전면 상부에 스페이서 물질 층을 증착하고 전면 식각을 통해 다결정 실리콘막 패턴(27) 및 산화막 패턴(25) 측벽에 스페이서(30)를 형성한다. 여기서 스페이서 물질은 질화막을 사용하는 경우를 예를 들어 설명하지만 필요에 따라 임의의 물질을 사용할 수 있다.Referring to FIG. 2D, the spacer material layer is deposited on the top surface and the spacer 30 is formed on the sidewalls of the polycrystalline silicon layer pattern 27 and the oxide layer pattern 25 through front side etching. Here, the spacer material is described using a nitride film as an example, but any material may be used as necessary.

도 2e를 참조하면, 다결정 실리콘막 패턴(27) 및 산화막 패턴(25)을 제거한다.Referring to FIG. 2E, the polycrystalline silicon film pattern 27 and the oxide film pattern 25 are removed.

도 2f를 참조하면, 스페이서(30)를 식각 마스크로 이용하여 피식각층(22)을 식각하여 원하는 패턴(32)을 형성하고, 스페이서(30)를 제거한다. 여기서, 피식각층(22)에 형성된 패턴(32)의 크기(critical dimension; CD)는 언더 컷 구조에 의해 증가된 스페이서(30) 하부의 두께에 의해 결정된다. Referring to FIG. 2F, the etching target layer 22 is etched using the spacer 30 as an etching mask to form a desired pattern 32, and the spacer 30 is removed. Here, the critical dimension (CD) of the pattern 32 formed on the etched layer 22 is determined by the thickness of the lower portion of the spacer 30 increased by the undercut structure.

상기한 실시예에서는 스페이서가 형성되는 패턴을 형성하기 위해 2개의 물질 층을 형성하는 경우 예를 들어 설명하였지만 필요에 따라 다수 층을 형성하여 각 층에 언더 컷을 형성하여 스페이서 하부의 두께를 원하는 만큼 증가시킬 수 있다.In the above-described embodiment, a case in which two material layers are formed to form a pattern in which a spacer is formed has been described, for example. Can be increased.

본 발명은 스페이서가 형성되는 층을 다층으로 형성하고 언더 컷 구조를 형성하여 스페이서 하부의 두께를 증가시켜 패턴의 CD를 증가시킬 수 있는 효과가 있다.The present invention has the effect of increasing the thickness of the lower portion of the spacer by forming a layer in which the spacer is formed in multiple layers and forming an under cut structure to increase the CD of the pattern.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다. It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (4)

피식각층 상부에 식각비가 서로 다른 제 1 물질 층 및 제 2 물질 층을 순차적으로 형성하는 단계;Sequentially forming a first material layer and a second material layer having different etching ratios on the etched layer; 상기 제 2 물질 층 및 상기 제 1 물질 층을 순차적으로 식각하여 제 1 패턴을 형성하는 단계;Sequentially etching the second material layer and the first material layer to form a first pattern; 상기 제 1 패턴의 상기 제 1 물질 층에 대해 선택 식각 공정을 수행하여 언더 컷(under cut) 구조가 형성된 제 2 패턴을 형성하는 단계;Performing a selective etching process on the first material layer of the first pattern to form a second pattern having an under cut structure; 상기 제 2 패턴 측벽에 스페이서를 형성하는 단계;Forming a spacer on the sidewall of the second pattern; 상기 제 2 패턴을 제거하는 단계; 및 Removing the second pattern; And 상기 스페이서를 이용하여 상기 피식각층을 식각하여 제 3 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 형성 방법.And etching the etched layer using the spacers to form a third pattern. 제 1 항에 있어서, 상기 제 1 패턴을 형성하는 단계는 The method of claim 1, wherein the forming of the first pattern is performed. 상기 제 2 물질 층 상부에 감광막을 도포하고, 노광 및 현상 공정을 통해 감광막 패턴을 형성하는 단계; 및Applying a photoresist film on the second material layer, and forming a photoresist pattern through an exposure and development process; And 상기 감광막 패턴을 식각 마스크로 이용하여 상기 제 2 물질 층 및 상기 제 1 물질 층을 순차적으로 식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 형성 방법.And sequentially etching the second material layer and the first material layer using the photoresist pattern as an etching mask. 제 1 항에 있어서, The method of claim 1, 상기 제 1 물질 및 상기 제 2 물질은 금속, 다결정 실리콘, 산화막, 질화막, 비정질 탄소 중의 어느 하나로 각각 형성하여 적층 구조를 이루는 것을 특징으로 하는 반도체 소자 형성 방법.And the first material and the second material are formed of any one of metal, polycrystalline silicon, oxide film, nitride film, and amorphous carbon to form a laminated structure. 제 1 항에 있어서, The method of claim 1, 상기 제 1 물질 층은 다수의 층으로 형성하는 것을 특징으로 하는 반도체 소자 형성 방법.And the first material layer is formed of a plurality of layers.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515193A (en) * 2012-06-28 2014-01-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device fine pattern manufacturing method

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