CN104051263A - Preparation method of semiconductor device - Google Patents
Preparation method of semiconductor device Download PDFInfo
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- CN104051263A CN104051263A CN201310076609.2A CN201310076609A CN104051263A CN 104051263 A CN104051263 A CN 104051263A CN 201310076609 A CN201310076609 A CN 201310076609A CN 104051263 A CN104051263 A CN 104051263A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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Abstract
The invention relates to a preparation method for a semiconductor device. The preparation method includes the following steps: providing a semiconductor substrate and at least forming grid structures on the semiconductor substrate; etching the semiconductor substrate so as to form a first trench at the two sides of the grid structures; forming a barrier layer on the grid structures and the side walls of the first trench so as to form a second trench; executing wet-method etching so as to flatten the bottom part of the second trench; removing the barrier layer; and depositing a stress layer in the second trench. In the preparation method of the semiconductor device, after the first trench is formed, the barrier layer is formed on the side walls of the trench so as to form the second trench; the surface of the bottom part of the second groove is flattened so as to reduce the roughness of the horizontal plane of the bottom part of the second trench and ensure that the surface of the stress layer deposited in the follow-up process is smoother and more uniform; and therefore, the roughness of the surface of the stress layer is reduced, the deposit quality of the SiC layer is improved and the performance and yield of the device are improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of preparation method of semiconductor device.
Background technology
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly that the size by constantly dwindling integrated circuit (IC)-components realizes with the speed that improves it.At present, owing to having advanced to nanometer technology process node pursuing semi-conductor industry in high device density, high-performance and low cost, particularly when dimensions of semiconductor devices drops to 20nm or when following, the preparation of semiconductor device is subject to the restriction of various physics limits.
In prior art in order to improve the performance of semiconductor device, in semiconductor device, introduce stressor layers, described stressor layers affects the mobility of charge carrier in device, for example in silicon the mobility of electronics along with tension stress along electronics moving direction increases and increases, reduce along with the increase of compression, in described silicon, the mobility in band hole on schedule, along with the compression along electronics moving direction increases and increases, reduces along with the increase of tension stress.
Along with the increase of semiconductor device integrated level, described stress becomes more important to the impact of electronic component, in CMOS transistor, conventionally on nmos pass transistor, form the stressor layers with tension stress, on PMOS transistor, form the stressor layers with compression, the performance of cmos device can by by described action of pulling stress in NMOS, action of compressive stress improves in PMOS.
In prior art, in nmos pass transistor, conventionally select SiC as tension stress layer, in PMOS transistor, conventionally select SiGe as compressive stress layer.In explanation prior art, form the method for described stressor layers using SiC layer as example, first substrate is provided in nmos device, on described substrate, form multiple grid structures, in leaking, the source of grid structure both sides forms groove, then SiC stressor layers described in epitaxial growth in described groove, but due to constantly reducing of semiconductor device, forming after described groove, the bottom water plane of described groove is uneven, thereby cause the rough surface, uneven of the SiC stressor layers of deposition, affected the performance of device.
Although can improve by various stressor layers the performance of device in prior art, but below device size drops to 20nm time, the surface of the various stressor layers that form becomes coarse, have a strong impact on the performance of device, therefore, stressor layers how to prepare smooth surface homogeneous under 20nm size becomes the key that improves device performance, and various means of the prior art can't realize described object.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order effectively to address the above problem, the present invention proposes a kind of preparation method of semiconductor device, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, at least forms grid structure;
Semiconductor substrate described in etching, to form the first groove in the both sides of described grid structure;
On the sidewall of described grid structure and described the first groove, form barrier layer, and then form the second groove; Carry out wet etching, with the bottom of the second groove described in planarization; Remove described barrier layer;
In described the second groove, deposit stressor layers.
As preferably, described the first groove is dark U-shaped groove.
As preferably, the formation method of described the second groove is:
On sidewall and the formation barrier layer, bottom of described the first groove, selective etch is removed the barrier layer of described the first channel bottom, continues substrate described in etching, and then forms described the second groove.
As preferably, described selective etch is selected CHF
3, CF
4, C
4f
6, C
4f
8, C
5f
8in one or more.
As preferably, select plasma etching method to continue substrate described in etching, and then form described the second groove.
As preferably, the plasma gas power of described plasma etching is 200W-500W, and voltage is 100V-300V, temperature 10-60 DEG C.
As preferably, described the second groove is shallow trench, and the degree of depth of described the second groove is in 50 dusts.
As preferably, described barrier layer is oxide.
As preferably, described barrier layer is SiO
2.
As preferably, the formation method on described barrier layer is the one in chemical vapour deposition (CVD), physical vapour deposition (PVD), ald or boiler tube sedimentation.
As preferably, select wet etching to remove described barrier layer.
As preferably, remove described barrier layer and select the HF solution of dilution.
As preferably, described grid structure comprises grid and is positioned at the grid curb wall on described gate lateral wall.
As preferably, the thickness of described grid curb wall is 5-25nm.
As preferably, described wet etching is selected TAMH.
As preferably, the concentration of described TAMH is 10-30%.
As preferably, described wet etching temperature is in 30 DEG C.
As preferably, described stressor layers is embedded SiC layer.
As preferably, the deposition process of described SiC layer is atomic layer deposition method or epitaxial growth method.
In the present invention in order to make the horizontal plane roughness of embedded SiC layer less, surface homogeneous Paint Gloss, forming after described the first groove, on the sidewall of described groove, form barrier layer, and then formation the second groove, and to shown in the lower surface of the second groove carry out planarization, eliminate the rough plane of described the second groove by described planarization, reduce described the second channel bottom horizontal plane roughness, and make the contact-making surface of described Si-SiC cleaner, guaranteed the surface homogeneous Paint Gloss of the stressor layers depositing in subsequent technique, reduce the roughness on described stressor layers surface, improve the deposition quality of SiC layer, and then performance and the yield of raising device.
Brief description of the drawings
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the generalized section of the substrate that comprises grid structure;
Fig. 2 is the generalized section that forms the first groove in substrate;
Fig. 3 is in the generalized section that forms the second groove;
Fig. 4 is the generalized section of the second channel bottom described in planarization;
Fig. 5 is the generalized section of removing behind described barrier layer;
Fig. 6 is the process chart of preparation containing the stressor layers device of surfacing.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, by propose detailed description in following description, so that semiconductor device of the present invention and preparation method thereof to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerated the size in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
Below in conjunction with accompanying drawing, 1-5 is described in detail the specific embodiment of the present invention.
First with reference to Fig. 1, provide Semiconductor substrate 101, described substrate at least comprises grid structure 102;
Particularly, Semiconductor substrate 101 can be at least one in following mentioned material in the present invention: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Preferred silicon-on-insulator (SOI) in an embodiment of the present invention, silicon-on-insulator (SOI) comprises and is followed successively by from the bottom up support substrates, oxide insulating layer and semiconductor material layer, but is not limited to above-mentioned example.
In Semiconductor substrate 101, form grid structure 102, grid structure comprises the grid curb wall 103 being positioned on gate lateral wall, particularly, grid structure 102 can comprise each material, each material is including but not limited to some metal, metal alloy, metal nitride and metal silicide, and laminate and its compound.Gate electrode also can comprise polysilicon and polysilicon-Ge alloy material (, having the doping content from every cubic centimetre of about 1e18 to about 1e22 foreign atom) and polysilicon metal silicide (polycide) material (polysilicon/metal silicide laminated material of doping) of doping.
Similarly, also can adopt any one formation previous materials of several methods.Limiting examples comprises self-aligned metal silicate method, process for chemical vapor deposition of materials with via and physical vapor deposition methods, such as, but not limited to: method of evaporating and sputtering method.Conventionally, gate electrode 102 comprises having the polycrystalline silicon material of thickness from about 50 doping to about 2000 dusts.
Particularly, first in Semiconductor substrate 101, form gate dielectric (not shown), then on gate dielectric, form grid layer.In one embodiment, grid layer is made up of polycrystalline silicon material, generally also can use metal, metal nitride, metal silicide or the similar compound material as grid layer.Gate dielectric and preferably formation method of grid layer comprise chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD), also can use the general similarity method such as such as sputter and physical vapour deposition (PVD) (PVD).The thickness of grid layer is to be less than approximately 1200 dusts as good.
Grid layer can be the sandwich construction that comprises semi-conducting material, for example silicon, germanium, metal or its combination.The formation technique of grid layer can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, for example low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technique.The thickness of grid layer is 800 to 3000 dusts.
In an embodiment of the present invention, be preferably formed polysilicon gate construction, the formation method of polysilicon layer can be selected low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions that form polysilicon layer comprise: reacting gas is silane (SiH4), and the range of flow of silane can be 100～200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700～750 degrees Celsius; Reaction chamber internal pressure can be 250～350mTorr, as 300mTorr; In reacting gas, also can comprise buffer gas, buffer gas can be helium (He) or nitrogen, and the range of flow of helium and nitrogen can be 5～20 liters/min (slm), as 8slm, 10slm or 15slm.Deposition is carried out patterning after forming polysilicon layer, to obtain grid.
Then on gate lateral wall, form grid curb wall (spacer) 103; Grid curb wall is e-SiC side wall (e-SiC spacer), and grid curb wall 103 can be SiO
2, in SiN, SiOCN a kind of or they constitute.Optimize execution mode for one as the present embodiment, side wall is that silica, silicon nitride form jointly, concrete technology is: in Semiconductor substrate, form the first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer, then adopt engraving method to form grid curb wall 103.The thickness of grid curb wall 103 is 2-30nm, is preferably 5-25nm.
As example, in Semiconductor substrate, can also be formed with and be positioned at grid structure both sides and the sidewall structure near grid structure.Wherein, sidewall structure can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.It should be noted that, sidewall structure is optional and nonessential, its be mainly used in follow-up while carrying out etching or Implantation the sidewall of grill-protected electrode structure injury-free.
With reference to Fig. 2, etching semiconductor substrate 101, forms the first groove 10 in the both sides of grid structure 102;
Particularly, in an embodiment of the present invention taking grid curb wall 103 as mask etch substrate, to form the first groove 10 in substrate, the first groove 10 is " U " type groove (trench), the first groove is deep trench, the degree of depth of " U " type groove (trench) is 100-5000 dust, is preferably 500-1000 dust, and wherein the bottom of " U " type groove (trench) is rough A.
In this step, etching can be selected dry etching or wet etching, in an embodiment of the present invention, select dry etching manufacturing process, for example the combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also more than one lithographic method can be used.As preferably, select plasma etching, as further preferably, select HBr, Cl
2, NF
3deng gas as reacting gas, by making, after gas plasma, substrate is carried out to etching.Be 300W～400W in this etching step reaction power, air pressure is 10～30mtorr, reaction time can be set according to the needs of target devices and etch process, is not limited to a certain number range, in an embodiment of the present invention, is preferably 40～60s.
In one embodiment of this invention, can also heat substrate, be heated to 100-400 DEG C, then carry out plasma etching, particularly, the heated substrate by making inert gas plasma, treatment conditions when to make substrate temperature be the etch processes temperature of 200 DEG C～400 DEG C are: the supply flow rate as the He gas of inert gas is made as to 50-150sccm; Pressure in treatment chamber is made as to 3-10Pa; When substrate temperature reaches after etch processes temperature, treatment conditions when this substrate of etching are: using the SF as etching gas
6the supply flow rate of gas is made as 50-200sccm; Pressure in treatment chamber is made as to 3-10Pa.
The groove horizontal plane obtaining by this step is uneven, the performance of device is reduced, in order to overcome this problem, in an embodiment of the present invention, groove is done to further processing, first with reference to Fig. 3, on the sidewall of grid curb wall 102 and the first groove 10, form barrier layer 104 and then form other shallow trench-the second groove 20;
Particularly, barrier layer 104 can be oxide, for example, can be oxide, nitrogen oxide etc., for example SiO
2, selection and Semiconductor substrate have the material of larger etching selectivity, are not limited to cited material.As preferably, the thickness on barrier layer 104 is not more than 5nm.
As preferably, the formation method on barrier layer 104 for depositing one deck oxide skin(coating) in Semiconductor substrate 101, described barrier layer forms by chemical vapour deposition (CVD) (CVD), plasma auxiliary chemical vapor deposition (PECVD), physical vapour deposition (PVD), boiler tube sedimentation, metal organic chemical vapor deposition (MOCVD) and ald (ALD) or other advanced deposition technique, preferred ald (ALD) method or boiler tube deposition in an embodiment of the present invention.After deposition, oxide skin(coating) covers whole Semiconductor substrate 101, and then selective etch is removed the oxide layer of the first groove 10 bottoms, to expose the bottom of the first groove.
In an embodiment of the present invention, selective etch is selected CHF
3, CF
4, C
4f
6, C
4f
8, C
5f
8in one or more, in this etching process, gas flow can be controlled as required and be not limited to a certain number range, does not repeat them here.
Form barrier layer 104 on the sidewall of grid curb wall 103 and the first groove 10 after, continue etching semiconductor substrate 101, form the second groove on the basis of the first groove, the degree of depth of the second groove can not be excessive, and the degree of depth of the second groove 20 is not more than 50 dusts.
In an embodiment of the present invention, select plasma etching method to continue etch substrate, and then form the second groove 20, as preferably, the plasma gas power of plasma etching is 200W-500W, voltage is 100V-300V, temperature 10-60 DEG C, it should be noted that, described method is only exemplary, the method that forms the second groove 20 is not limited to the method, all can be for the present invention as long as can realize the method for described object.
With reference to Fig. 4, carry out a wet etching, with the bottom of planarization the second groove 20;
Particularly, the lower surface B of the second groove forming remains rough, in order to obtain smooth horizontal plane, in an embodiment of the present invention, select the base plane B of smooth the second groove 20 of wet method, particularly, in this etching process, select tetramethyl aqua ammonia (TMAH) to carry out etching as etching solution.
In order to obtain even curface more, reduce the roughness of the second groove 20 horizontal planes, in an embodiment of the present invention, select the TMAH that concentration is lower to carry out etching, preferably the TMAH of 10-30% carries out etching, the TMAH that is more preferably 15-20% carries out etching, the strict temperature of controlling this etching process simultaneously, and in this step, preferably etch temperature is less than 30 DEG C, more preferably 20-25 DEG C, Paint Gloss evenly with the surface of the groove guaranteeing to obtain.
The in the situation that in an embodiment of the present invention, TMAH concentration and temperature being lower, in order to accelerate etching speed, and obtain uniform surface Paint Gloss, in an embodiment of the present invention, in etching process, can stir etching solution, so that etchant concentration homogeneous more.In this step, etch-rate is preferably 200-800nm/min, is preferably 200-400nm/min, better to control this etching process.
After wet etching, smooth rough plane, as shown in Figure 4, the second groove 20 bottom level surface roughness reduce, horizontal plane homogeneous Paint Gloss, guarantee the surface homogeneous Paint Gloss of the stressor layers depositing in subsequent technique, reduced the roughness on stressor layers surface, and then improved performance and the yield of device.
With reference to Fig. 5, remove barrier layer 104;
Particularly, in an embodiment of the present invention, can peel off and remove barrier layer 104 by dry etching or wet method, preferably peel off and remove barrier layer 104 by wet method, obtain and in an embodiment, remove described barrier layer and select the HF solution of dilution in the present invention, the concentration of described HF solution is not limited to a certain number range, does not repeat them here.
Executing after this step, the roughness of described the second groove 20 lower surface B reduces greatly, smooth surface homogeneous, for subsequent process steps provides good basis, then in described the first groove 10 and described the second groove 20, deposit stress material layer, particularly, select according to the character that will form device, for example in nmos pass transistor, conventionally select SiC as tension stress layer, in PMOS transistor, conventionally select SiGe as compressive stress layer.
In an embodiment of the present invention, in the sidewall of the first groove and the second groove, form the SiC layer of embedded (embedded).SiC layer forms by other advanced deposition technique such as low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and ald (ALD) or epitaxial growth etc., preferably ald (ALD) method or epitaxial growth.
In one embodiment of this invention, utilize growth technology, at 1000-1600 DEG C of temperature, at the bottom of the second groove epitaxial growth SiC layer, in epitaxial growth, used source gas is SiH
4and C
3h
8, carrier gas is H
2, N
2for N-shaped doping, trimethyl aluminium (TMA) or B
2h
6for the doping of P type, typical growth temperature is 1500～1600 DEG C.
In the time of device fabrication, SiC can not use diffusion technology, therefore Implantation is very important to selective doping, uses heavy dose of N
+or P
+can form N
+siC; The P that Implantation makes
+siC, then further annealing at 1600～1700 DEG C, can obtain more than 90% activity ratio.
Forming after embedded SiC layer, described method can also further comprise epitaxial growth of semiconductor material, and planarization, and then the step such as formation source leakage, does not repeat them here.
In the present invention in order to make the horizontal plane roughness of embedded SiC layer less, surface homogeneous Paint Gloss, forming after described the first groove, on the sidewall of described groove, form barrier layer, and then formation the second groove, and to shown in the lower surface of the second groove carry out planarization, eliminate the rough plane of described the second groove by described planarization, reduce described the second channel bottom horizontal plane roughness, and make the contact-making surface of described Si-SiC cleaner, guaranteed the surface homogeneous Paint Gloss of the stressor layers depositing in subsequent technique, reduce the roughness on described stressor layers surface, improve the deposition quality of SiC layer, and then performance and the yield of raising device.
With reference to Fig. 6, wherein show the process chart of the method for the invention, comprise the following steps particularly:
Step 201 provides Semiconductor substrate, at least forms grid structure in described Semiconductor substrate;
Semiconductor substrate described in step 202 etching, to form the first groove in the both sides of described grid structure;
Step 203 forms barrier layer on the sidewall of described grid structure and described the first groove, and then forms the second groove;
Step 204 is carried out wet etching, with the bottom of the second groove described in planarization;
Step 205 is removed described barrier layer;
Step 206 deposits stressor layers in described the second groove.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (19)
1. a preparation method for semiconductor device, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, at least forms grid structure;
Semiconductor substrate described in etching, to form the first groove in the both sides of described grid structure;
On the sidewall of described grid structure and described the first groove, form barrier layer, and then form the second groove;
Carry out wet etching, with the bottom of the second groove described in planarization;
Remove described barrier layer;
In described the second groove, deposit stressor layers.
2. method according to claim 1, is characterized in that, described the first groove is dark U-shaped groove.
3. method according to claim 1, is characterized in that, the formation method of described the second groove is:
On sidewall and the formation barrier layer, bottom of described the first groove, selective etch is removed the barrier layer of described the first channel bottom, continues Semiconductor substrate described in etching, and then forms described the second groove.
4. method according to claim 3, is characterized in that, described selective etch is selected CHF
3, CF
4, C
4f
6, C
4f
8, C
5f
8in one or more.
5. method according to claim 3, is characterized in that, selects plasma etching method to continue substrate described in etching, and then forms described the second groove.
6. method according to claim 5, is characterized in that, the plasma gas power of described plasma etching is 200W-500W, and voltage is 100V-300V, temperature 10-60 DEG C.
7. method according to claim 1, is characterized in that, described the second groove is shallow trench, and the degree of depth of described the second groove is in 50 dusts.
8. method according to claim 1, is characterized in that, described barrier layer is oxide.
9. according to the method described in claim 1 or 8, it is characterized in that, described barrier layer is SiO
2.
10. method according to claim 9, is characterized in that, the formation method on described barrier layer is the one in chemical vapour deposition (CVD), physical vapour deposition (PVD), ald or boiler tube sedimentation.
11. methods according to claim 1, is characterized in that, select wet etching to remove described barrier layer.
12. according to the method described in claim 1 or 11, it is characterized in that, removes described barrier layer and selects the HF solution of dilution.
13. methods according to claim 1, is characterized in that, described grid structure comprises grid and is positioned at the grid curb wall on described gate lateral wall.
14. methods according to claim 9, is characterized in that, the thickness of described grid curb wall is 5-25nm.
15. methods according to claim 1, is characterized in that, described wet etching is selected TAMH.
16. methods according to claim 15, is characterized in that, the concentration of described TAMH is 10-30%.
17. methods according to claim 15, is characterized in that, described wet etching temperature is in 30 DEG C.
18. methods according to claim 1, is characterized in that, described stressor layers is embedded SiC layer.
19. methods according to claim 18, is characterized in that, the deposition process of described SiC layer is atomic layer deposition method or epitaxial growth method.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111446166A (en) * | 2020-03-16 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Process method for generating double-groove transistor by utilizing polymer isolation layer |
| CN112509918A (en) * | 2021-01-29 | 2021-03-16 | 度亘激光技术（苏州）有限公司 | Processing method of semiconductor structure and semiconductor structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090050965A1 (en) * | 2007-08-20 | 2009-02-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| US20090114956A1 (en) * | 2007-11-01 | 2009-05-07 | Fujitsu Microelectronics Limited | Semiconductor device and manufacturing method thereof |
| US20110241073A1 (en) * | 2010-03-30 | 2011-10-06 | International Business Machines Corporation | Structure for self-aligned silicide contacts to an upside-down fet by epitaxial source and drain |
-
2013
- 2013-03-11 CN CN201310076609.2A patent/CN104051263A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090050965A1 (en) * | 2007-08-20 | 2009-02-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| US20090114956A1 (en) * | 2007-11-01 | 2009-05-07 | Fujitsu Microelectronics Limited | Semiconductor device and manufacturing method thereof |
| US20110241073A1 (en) * | 2010-03-30 | 2011-10-06 | International Business Machines Corporation | Structure for self-aligned silicide contacts to an upside-down fet by epitaxial source and drain |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111446166A (en) * | 2020-03-16 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Process method for generating double-groove transistor by utilizing polymer isolation layer |
| CN112509918A (en) * | 2021-01-29 | 2021-03-16 | 度亘激光技术（苏州）有限公司 | Processing method of semiconductor structure and semiconductor structure |
| CN112509918B (en) * | 2021-01-29 | 2021-04-23 | 度亘激光技术（苏州）有限公司 | Processing method of semiconductor structure and semiconductor structure |
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