TWI716441B - Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications - Google Patents

Abstract

The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.

Description

Method for manufacturing nanowires for horizontal wrap-around gate devices for semiconductor applications

The embodiments of the present invention generally relate to methods for forming vertically stacked nanowires on semiconductor substrates using desired materials, and more specifically, to methods for forming vertically stacked nanowires on semiconductor substrates using desired materials. On the substrate for the method used for field effect transistor (FET) semiconductor manufacturing applications.

Reliable production of sub-half micron and smaller features is one of the key technical challenges for the next generation of very large integrated circuit (VLSI) and ultra-large integrated circuit (ULSI) semiconductor devices. However, with the advancement of circuit technology limits, shrinking VLSI and ULSI technologies have additional requirements for processing capabilities. Reliable formation of the gate structure on the substrate is important for the success of VLSI and ULSI and for continued efforts to increase circuit density and the quality of individual substrates and dies.

As the circuit density of next-generation devices increases, the width of interconnects (such as vias, trenches, contacts, gate structures and other features, and dielectric materials between them) is reduced to 25 nm and 20 nm The size and smaller, while the thickness of the dielectric layer remains substantially constant, whereby the aspect ratio of the feature increases. In addition, the reduced channel length usually causes a significant short channel effect of conventional planar MOSFET architectures. In order to be able to manufacture next-generation devices and structures, three-dimensional (3D) device structures are often used to improve the performance of transistors. Specifically, fin field effect transistors (FinFETs) are often used to enhance device performance. FinFET devices generally include semiconductor fins with a high aspect ratio, in which channels for transistors and source/drain regions are formed on the semiconductor fins. Subsequently, the gate electrode is formed above and along the side of a part of the fin device, taking advantage of the increased surface area of the channel and source/drain regions, in order to produce a faster, more reliable and better controlled semiconductor Transistor device. Other advantages of FinFET include reducing short-channel effects and providing higher current. Device structures with hGAA configurations usually provide superior electrostatic control by surrounding gates in order to suppress short channel effects and associated leakage currents.

In some applications, the horizontal surround gate (hGAA) structure is used for next-generation semiconductor device applications. The hGAA device structure includes several lattice matching channels (eg, nanowires) suspended in a stacked configuration and connected by source/drain regions.

In the hGAA structure, different materials are usually used to form the channel structure (for example, nanowires). This will undesirably increase manufacturing in terms of integrating all these materials into the nanowire structure without reducing device performance. Difficulty. For example, one of the challenges associated with the hGAA structure includes the large parasitic capacitance between the metal gate and the source/drain. Inappropriate management of such parasitic capacitance may result in a lot of reduction in device performance.

Therefore, there is a need for an improved method for forming the channel structure of the hGAA device structure on the substrate with good profile and size control.

The present disclosure provides a method for forming a nanowire structure of a horizontal surround gate (hGAA) structure of a semiconductor wafer using a desired material. In one example, a method of forming a nanowire structure on a substrate includes: supplying an oxygen-containing gas mixture to a multi-material layer on the substrate in a processing chamber, wherein the multi-material layer includes a repeated first layer and The second layer pair, the first layer and the second layer having a first set of sidewalls and a second set of sidewalls respectively exposed through openings defined in the multi-material layer; Two sets of side walls.

In another example, a method for forming a nanowire structure on a substrate includes mainly forming an oxide layer on a portion of a multi-material layer provided on the substrate, wherein the multi-material layer includes repeated first and second layers. A pair of layers, the first layer and the second layer have a first set of sidewalls and a second set of sidewalls respectively exposed through openings defined in the multi-material layer, wherein an oxide layer is selectively formed in the second set of the second layer On the side wall.

In yet another example, a method for forming a nanowire structure on a substrate includes: mainly forming an oxide layer on a part of a multi-material layer provided on the substrate, wherein the multi-material layer includes repeated pairs of silicon and SiGe layers , The silicon layer and the SiGe layer have a first set of sidewalls and a second set of sidewalls respectively exposed through the openings defined in the multi-material layer, wherein the portion on which the oxide layer is selectively formed is located in the second set of the SiGe layer Group on the side wall.

Provided is a method for manufacturing a nanowire structure with controlled parasitic capacitance for a horizontal surround gate (hGAA) semiconductor device structure. In one example, a superlattice structure including different materials (for example, a first material and a second material) arranged in an alternating stack configuration may be formed on a substrate to be later used as a horizontal wrap-around type Gate electrode (hGAA) semiconductor device structure nanowire (for example, channel structure). A selective oxidation process may be performed to selectively form an oxide layer on the sidewalls of the first material in the superlattice structure, while minimal oxidation occurs on the second material. The oxidation selectivity on the sidewalls of the first material and the second material in the superlattice structure is greater than 5:1. By doing so, the interface with parasitic devices formed between the nanowire and the source/drain regions is maintained and controlled to effectively reduce the parasitic capacitance.

Figure 1 is a cross-sectional view of an illustrative processing system 132 suitable for performing a selective oxidation process as described further below. The processing system 132 can be a CENTURA® and Producer® SE or Producer® GT deposition system, all of which can be purchased from Applied Materials Inc. (Santa Clara, California). It is contemplated that other processing systems (including those available from other manufacturers) may be suitable for practicing the invention.

The processing system 132 includes a processing chamber 100 that is coupled to the gas panel 130 and the controller 110. The processing chamber 100 generally includes a top 124, a side 101, and a bottom wall 122, which define an internal volume 126.

The support base 150 is provided in the internal volume 126 of the chamber 100. The base 150 may be made of aluminum, ceramic, and other suitable materials. In one embodiment, the base 150 is made of a ceramic material (such as aluminum nitride), which is suitable for use in a high temperature environment (such as a plasma process environment) without causing damage to the base 150 Thermal damage. The base 150 can be moved in the vertical direction in the chamber 100 using a lifting mechanism (not shown).

The base 150 may include an embedded heater element 170 adapted to control the temperature of the substrate 190 supported on the base 150. In one embodiment, the susceptor 150 may be resistively heated by applying current from the power source 106 to the heater element 170. In one embodiment, the heater element 170 may be made of nickel-chromium wire encapsulated in a nickel-iron-chromium alloy (eg, INCOLOY®) sheath. The current supplied from the power supply 106 is adjusted by the controller 110 to control the heat generated by the heater element 170, thereby maintaining the substrate 190 and the susceptor 150 in a substantially constant state during the film deposition process under any suitable temperature range. temperature. In another embodiment, the base can be maintained at room temperature as needed. In another embodiment, the base 150 may also include a cooler (not shown) as required, so as to cool the base 150 in a range below room temperature as required. The supplied current can be adjusted to selectively control the temperature of the base 150 between about 100 degrees Celsius and about 1100 degrees Celsius, for example, between 200 degrees Celsius and about 1000 degrees Celsius, such as between about 300 degrees Celsius and about 800 degrees Celsius. between.

A temperature sensor 172 (such as a thermocouple) may be embedded in the support base 150 to monitor the temperature of the base 150 in a conventional manner. The measured temperature will be used by the controller 110 to control the power supplied to the heater element 170 in order to maintain the substrate at a desired temperature.

The vacuum pump 102 is coupled to a port formed in the wall 101 of the chamber 100. The vacuum pump 102 is used to maintain a desired gas pressure in the processing chamber 100. The vacuum pump 102 also evacuates the processed gas and process by-products from the chamber 100.

A shower head 120 having a plurality of apertures 128 is coupled to the top 124 of the processing chamber 100 above the substrate support base 150. The aperture 128 of the shower head 120 is used to introduce the process gas into the chamber 100. The pores 128 may have different sizes, numbers, distributions, shapes, designs, and diameters in order to facilitate the flow of various process gases used for different process requirements. The shower head 120 is connected to the gas panel 130 to allow various gases to be supplied to the internal volume 126 during the manufacturing process. The plasma is formed from the process gas mixture leaving the shower head 120 to enhance the pyrolysis of the process gas, thereby causing material to be deposited on the surface 191 of the substrate 190.

The shower head 120 and the substrate support base 150 may be formed as a pair of spaced apart electrodes in the internal volume 126. One or more RF power sources 140 provide a bias potential to the showerhead 120 via the matching network 138 to promote the generation of plasma between the showerhead 120 and the base 150. Alternatively, the RF power source 140 and the matching network 138 may be coupled to the shower head 120, the substrate support base 150, or to both the shower head 120 and the substrate support base 150, or to An antenna (not shown) outside the chamber 100. In one embodiment, the RF power source 140 may provide power between about 10 watts and about 3000 watts at a frequency of about 30 kHz to about 13.6 MHz.

An optional water vapor generation (WVG) system 152 is coupled to the processing system 132, which water vapor generation (WVG) system 152 is in fluid communication with an internal volume 126 defined in the processing chamber 100. The WVG system 152 generates ultra-high purity water vapor through the catalytic reaction of O ₂ and H ₂ . In one embodiment, the WVG system 152 has a reactor or catalytic cylinder lined with a catalyst, in which water vapor is generated by a chemical reaction. The catalyst may include metals or alloys, such as palladium, platinum, nickel, combinations thereof, and alloys thereof.

The controller 110 includes a central processing unit (CPU) 112, a memory 116, and a support circuit 114 for controlling the system sequence and adjusting the gas flow from the gas panel 130 and the WVG system 152. The CPU 112 may be any form of general-purpose computer processor that can be used in an industrial environment. The software routines may be stored in the memory 116 (such as random access memory, read-only memory, floppy disk or hard disk drive, or other forms of digital storage devices). The support circuit 114 is conventionally coupled to the CPU 112, and may include a cache memory, a clock circuit, an input/output system, a power supply, and so on. The two-way communication between the controller 110 and the various elements of the processing system 132 is processed via many signal cables (collectively referred to as signal bus 118, some of which are shown in FIG. 1).

Figure 2 depicts a plan view of a semiconductor processing system 200 in which the methods described herein can be practiced. One processing system that can be adapted to benefit from the present invention is the 300mm Producer ^(TM) processing system commercially available from Applied Materials, Inc., Santa Clara, California. The processing system 200 generally includes: a front platform 202 in which a substrate cassette 218 included in the FOUP 214 is supported, and substrates are loaded into and unloaded from the load lock chamber 209; a transfer chamber 211, which transfers The chamber houses the substrate processor 213; and a series of series-connected processing chambers 206, the series-connected processing chambers are installed on the transfer chamber 211.

Each cascade processing chamber 206 includes two processing regions for processing substrates. The two process areas share a common gas supply source, a common pressure control, and a common process gas discharge/pumping system. The modular design of the system enables rapid conversion from any configuration to any other configuration. The arrangement and combination of chambers can be changed for the purpose of performing specific process steps. According to aspects of the invention, any one of the tandem processing chambers 206 may include a cover as described below, which includes one or more chamber configurations described above with reference to the processing chamber 100 depicted in FIG. 1. It should be noted that the processing chamber 100 can be configured to perform a deposition process, an etching process, a curing process, or a heating/annealing process as needed. In one embodiment, the processing chamber 100 shown as a single chamber designed may be incorporated into the semiconductor processing system 200.

In one embodiment, the processing system 132 may be equipped with one or more of the series-connected processing chambers, which are known to adapt to various other known processes (such as chemical vapor deposition (CVD)). , Physical vapor deposition (PVD), etching, curing or heating/annealing, etc.) of the supporting chamber hardware. For example, the system 200 may be configured with one of the processing chambers 100 as a plasma deposition chamber for depositing, for example, a dielectric thin film on a substrate. This configuration can maximize research and R&D manufacturing utilization, and if necessary, reduce the exposure of the etched film to the atmosphere.

A controller 240 including a central processing unit (CPU) 244, a memory 242, and a support circuit 246 is coupled to various components of the semiconductor processing system 200 to facilitate control of the process of the present invention. The memory 242 can be any computer-readable medium, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage device (whether it is the semiconductor processing system 200 Or the local end of the CPU 244 is still remote). The support circuit 246 is coupled to the CPU 244 to support the CPU in a conventional manner. These circuits include cache memory, power supplies, clock circuits, input/output circuits, and subsystems. When the software routines or a series of program instructions stored in the memory 242 are executed by the CPU 244, the serial processing chamber 206 is executed.

FIG. 3 is a flowchart of an example of a method 300 for manufacturing a nanowire structure (for example, a channel structure) using composite materials for use in a horizontal surround gate (hGAA) semiconductor device structure. 4A-4C are cross-sectional views of a portion of a composite substrate corresponding to various stages of method 300. The method 300 can be used to form a nanowire structure with a desired material of a horizontal surround gate (hGAA) semiconductor device structure on a substrate, which can be later used to form a field effect transistor (FET). Alternatively, the method 300 can be beneficially used to manufacture other types of structures.

The method 300 begins at operation 302 by providing a substrate, such as the substrate 502 depicted in FIG. 2 with a thin film stack 401 formed thereon as shown in FIG. 4A. The substrate 502 can be made of the following materials, such as crystalline silicon (for example, Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, doped or undoped Silicon wafers and patterned or unpatterned silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass or sapphire. The substrate 502 may have various sizes, such as 200 mm, 300 mm, 450 mm, or other diameters, and may be a rectangular or square panel. Unless otherwise specified, the examples described herein were performed on substrates having a diameter of 200 mm, 300 mm, or 450 mm.

The thin film stack 401 includes a multi-material layer 212 disposed on an optional material layer 504. In an embodiment where the optional material layer 504 is not present, the thin film stack 401 may be directly formed on the substrate 502 as required. In one example, the optional material layer 504 is an insulating material. Suitable examples of the insulating material may include silicon oxide material, silicon nitride material, silicon oxynitride material, or any suitable insulating material. Alternatively, the optional material layer 504 may be any suitable material as required, including conductive materials or non-conductive materials. The multi-material layer 212 includes at least one pair of layers, and each pair includes a first layer 212a and a second layer 212b. Although the example depicted in FIG. 4A shows four pairs, each pair including the first layer 212a and the second layer 212b (alternating pairs, each pair including the first layer 212a and the second layer 212b), it should be noted that the logarithm (each The pair including the first layer 212a and the second layer 212b) may vary based on different process requirements. In a specific embodiment, 4 pairs of the first layer 212 a and the second layer 212 b may be deposited to form the multi-material layer 212 on the substrate 502. In one embodiment, the thickness of each single first layer 212a may be between about 20Å and about 200Å, such as about 50Å, and the thickness of each single second layer 212b may be between about 20Å and about 200Å, such as about 50Å. . The multi-material layer 212 may have a total thickness between about 10 Å and about 5000 Å, such as between about 40 Å and about 4000 Å.

The first layer 212a may be a crystalline silicon layer formed by an epitaxial deposition process, such as a single crystalline silicon layer, a polycrystalline silicon layer, or a monocrystalline silicon layer. Alternatively, the first layer 212a may be a doped silicon layer, including a p-type doped silicon layer or an n-type doped silicon layer. Suitable p-type dopants include B dopants, Al dopants, Ga dopants, In dopants, and so on. Suitable n-type dopants include N dopants, P dopants, As dopants, Sb dopants, and so on. In yet another example, the first layer 212a may be a III-V group material, such as a GaAs layer. The second layer 212b may be a Ge-containing layer, such as a SiGe layer, a Ge layer, or other suitable layers. Alternatively, the second layer 212b may be a doped silicon layer, including a p-type doped silicon layer or an n-type doped silicon layer. In yet another example, the second layer 212b may be a III-V group material, such as a GaAs layer. In yet another example, the first layer 212a may be a silicon layer, and the second layer 212b may be a metal material with a high dielectric constant material coating on the outer surface of the metal material. Suitable examples of high dielectric constant materials include hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), hafnium oxysilicate (HfSiO ₄ ), hafnium aluminum oxide (HfAlO), zirconium oxysilicate (ZrSiO ₄ ), Tantalum dioxide (TaO ₂ ), aluminum oxide, aluminum-doped hafnium dioxide, bismuth strontium titanate (BST) or platinum zirconium titanate (PZT), etc. In a specific embodiment, the coating is a hafnium dioxide (HfO ₂ ) layer.

In the specific example depicted in FIG. 4A, the first layer 212a is a crystalline silicon layer, such as a single crystal silicon layer, a polycrystalline silicon layer, or a single crystal silicon layer. The second layer 212b is a SiGe layer.

In some examples, a hard mask layer (not shown in FIG. 4A) and/or a patterned photoresist layer may be disposed on the multi-material layer 212 to pattern the multi-material layer 212. In the example shown in FIG. 4A, the multi-material layer 212 has been patterned in the previous patterning process to form openings 402 in the multi-material layer 212, which openings can be formed later with source/drain anchors In it.

In the embodiment where the substrate 502 is a crystalline silicon layer and the insulating layer 504 is a silicon oxide layer, the first layer 212a may be an intrinsic epitaxial silicon layer, and the second layer 212b is a SiGe layer. In another embodiment, the first layer 212a may be a layer containing doped silicon, and the second layer 212b may be an intrinsic epitaxial silicon layer. The layer containing doped silicon may be a p-type dopant or an n-type dopant, or a SiGe layer as required. In another embodiment where the substrate 502 is a Ge or GaAs substrate, the first layer 212a may be a GeSi layer, and the second layer 212b may be an intrinsic epitaxial Ge layer, or vice versa. In yet another embodiment where the substrate 502 is a GaAs layer mainly having crystal planes at <100>, the first layer 212a may be an intrinsic Ge layer, and the second layer 212b is a GaAs layer, or vice versa. It should be noted that the substrate material and the selection of the first layer 212a and the second layer 212b in the multi-material layer 212 may utilize different combinations of the materials listed above.

At optional operation 303, the liner layer 404 may be formed on the sidewall 405 of the multi-material layer 212, as shown in FIG. 4B2. The liner layer 404 may provide a substantially planar (eg, uniform) surface that allows the oxide layer to be later formed thereon with good interface adhesion and flatness. The process for forming the oxide layer will be described later at operation 304. Therefore, in an embodiment in which the sidewall 405 of the multi-material layer 212 is substantially planar with the desired straightness, the liner layer 404 can be weakened, and at operation 304, an oxide layer can be directly formed on the multi-material layer 212 On the side wall 405.

In one example, the liner layer 404 can be selected from materials that can help bridge the oxide layer to the sidewall 405 of the multi-material layer 212 with good adhesion at the interface. In addition, the liner layer 404 may have a sufficient thickness to fill the nano-rough surface from the sidewall 405 of the multi-material layer 212 in order to provide a substantially planar surface that allows the oxide layer to be at a desired level later. The flatness and flatness are formed on it. In one example, the liner layer 404 may have a thickness between about 0.5 nm and about 5 nm.

In one embodiment, the liner layer 404 is a silicon-containing dielectric layer, such as a silicon nitride-containing layer, a silicon carbide-containing layer, a silicon oxide-containing layer, for example, SiN, SiON, SiC, SiCN, SiOC or oxygen. Silicon carbonitride or silicon materials with dopants, etc. The dopants formed in the silicon-containing dielectric layer can have a relatively low concentration and have the properties of a thin film rich in silicon atoms. In one example, the liner layer 404 is a silicon nitride layer or silicon oxynitride (SiON), having a thickness between about 5 Å and about 50 Å, such as about 10 Å. The liner layer 404 may be formed by a CVD process, an ALD process, or any suitable deposition technique in a PVD, CVD, ALD, or other suitable plasma processing chamber.

At operation 304, after the optional liner layer 404 is formed on the sidewall 405 of the multi-material layer 212, selective oxide deposition may be performed to selectively form an oxide layer on certain areas of the multi-material layer 212 . In an example in which the optional operation 303 is not performed and the liner layer 404 is not formed on the substrate, the selective oxide deposition process can be directly performed on the substrate, as mentioned in FIG. 4B1.

Since the first layer 212a and the second layer 212b in the multi-material layer 212 are made of different materials, when the selective oxide deposition process is performed, the oxidation process can mainly occur on one material relative to the other material. In the example depicted in FIG. 4B1, where the first layer 212a is a silicon layer and the second layer 212b is a SiGe layer, the selective oxidation process can mainly occur on the sidewalls 406 of the second layer 212b instead of the first layer. On 212a. The selective oxidation process that occurs on the sidewall 406 of the second layer 212b mainly forms an oxide layer 407 on the sidewall 406 of the second layer 212b. It is believed that SiGe alloy has higher activity than the main silicon-containing material. Therefore, when oxygen atoms are supplied, the oxygen atoms tend to react with Si atoms in the SiGe alloy at a faster reaction rate instead of reacting with Si atoms from the main silicon-containing material, thereby providing a selective deposition process for the main An oxide layer 407 is formed on the sidewall 406 of the second layer 212b of SiGe alloy instead of on the first layer 212a. The minimum oxide residue 411 may appear on the sidewall 408 of the first layer 212a.

The oxidation process consumes silicon atoms from the SiGe alloy in the second layer 212b, thereby pulling the silicon atoms outward to react with oxygen atoms to form the oxide layer 407. Since Ge atoms can be activated and moved relatively easily during the oxidation process, the silicon atoms in the second layer 212b are gradually pulled out and react with oxygen atoms to form an oxide layer 407 on the sidewall 406.

In contrast, since the silicon atoms in the first layer 212a do not have Ge atoms to act as active drivers to actively push the silicon atoms outward to allow the reaction to react with oxygen atoms, the oxidation in the first layer 212a The layer formation rate is significantly lower than the oxide layer formation rate in the second layer 212b, thereby providing a selective oxidation process that mainly forms oxidation on the sidewall 406 of the second layer 212b instead of on the first layer 212a Layer 407. In one example, the selectivity of the oxidation rate between the second layer 212b (eg, SiGe layer) and the first layer 212a (eg, silicon layer) is greater than 5:1, such as about 6:1 and 10:1.

In one embodiment, the selective oxidation process may be performed in a suitable plasma processing chamber, including a processing chamber, such as the processing chamber 100 depicted in FIG. 1 or other suitable plasma chambers. The processing temperature is controlled in a low temperature range, such as less than 1200 degrees Celsius. It is believed that the low-temperature process can provide mild thermal energy to consume silicon atoms and push the silicon atoms toward the sidewall surface where oxygen atoms are present to form silicon oxide 407 without damaging the lattice formed by the Ge atoms in the thin film stack 401 structure. In this way, a part of the silicon atoms can be gradually transformed into the oxide layer 407 without forming interface parts or atomic vacancies. In one embodiment, the process temperature can be achieved between about 100 degrees Celsius and about 1100 degrees Celsius, for example, between 200 degrees Celsius and about 1000 degrees Celsius, such as between about 300 degrees Celsius and about 800 degrees Celsius.

In one embodiment, the oxidation process can be performed in a plasma-containing environment (such as decoupling plasma oxidation or rapid thermal oxidation), a thermal environment (such as a furnace), or a thermal plasma environment (such as APCVD, SACVD, LPCVD or any suitable CVD Process). The oxidation process can be performed by using an oxygen-containing gas mixture in the processing environment to cause the multi-material layer 212 to react. In one embodiment, the oxygen-containing gas mixture includes at least one of oxygen-containing gases with or without inert gas. Suitable examples of oxygen-containing gas include O ₂ , O ₃ , H ₂ O, NO ₂ , N ₂ O, steam, water vapor, and the like. Suitable examples of the inert gas supplied with the process gas mixture include at least one of Ar, He, Kr, and the like. In an exemplary embodiment, the oxygen-containing gas supplied in the oxygen-containing gas mixture is O ₂ gas having a flow rate between about 50 sccm and about 1000 sccm.

During the oxidation process, several process parameters can be adjusted to control the oxidation process. In an exemplary embodiment, the process pressure is adjusted to be between about 0.1 Torr and about atmospheric pressure (eg, 760 Torr). In one example, the oxidation process as performed at operation 304 is configured to have a relatively high deposition pressure, such as a pressure greater than 100 Torr, such as between about 300 Torr and atmospheric pressure. Suitable techniques that can be used to perform the selective oxidation process at operation 304 may include decoupling plasma oxidation process (DPO), plasma enhanced chemical vapor deposition process (PECVD), low pressure chemical vapor deposition process (LPCVD), Sub-atmospheric pressure chemical vapor deposition process (SACVD), atmospheric pressure chemical vapor deposition process (APCVD), hot furnace process, oxygen annealing process, plasma immersion process or any suitable process. In one embodiment, the oxidation process may be performed under ultraviolet (UV) light irradiation.

In one embodiment, the oxidation process is completed when the oxide layer 407 of the desired thickness is formed on the sidewall 406 of the second layer 212b. In one example, the oxide layer 407 may have a thickness between about 1 nm and about 10 nm. The total process time of the oxidation process can be determined by a time pattern after a desired part of silicon atoms mainly react with oxygen atoms to form an oxide layer 407 with a desired thickness. In one example, the substrate 502 is subjected to a selective oxidation process for about 5 seconds to about 5 minutes, depending on the oxidation rate of the second layer 212b, the pressure and flow rate of the gas. In an exemplary embodiment, the substrate 502 is exposed to the oxidation process for about 600 seconds or less.

In addition, in an example in which the liner layer 404 is formed on the sidewall 405 of the multi-material layer 212, when the selective oxidation process is performed at operation 304, similarly, the oxide layer 416 may be selectively formed only on the second layer. On the side wall 406 of 212b, the lining layer 404 is in contact therewith, as shown in FIG. 4B2'. As discussed above, the GeSi alloy in the second layer 212b is more active than the Si material present in the first layer 212a. During the oxidation process, Ge atoms can be activated by thermal energy from the oxidation process, thereby forming interface vacancies that allow oxygen atoms to be drawn in to bond with silicon atoms. Thus, oxygen atoms from the selective oxidation process pass through the liner layer 404 to react with silicon atoms from the second layer 212b, thereby forming an oxide layer 416 on the sidewall 406 of the second layer 212b. Since the liner layer 404 provides a substantially flat surface on the sidewall 405 of the multi-material layer 212, the oxide layer 416 formed in the second layer 212b below the liner layer 404 can still maintain the substantially flat surface on the sidewall 405. A flat surface to provide a straight sidewall profile for the nanowire structure as needed. In one embodiment, the liner layer 404 combined with the oxide layer 416 may have a thickness between about 3 nm and about 15 nm, such as between about 7 nm and about 8 nm.

After the oxide layers 416 and 407 are formed in the thin film stack 401, the first layer 212a and the multi-material layer 212 having the second layer 212b with the oxide layers 416 and 407 formed to the bottom can be used as having reduced parasitic capacitance and minimum The device leaks the nanowire 403 in the FET.

At operation 306, a gentle surface cleaning process is performed to selectively remove oxide residues 411 (if present) from the film stack 401 without damaging the surface of the film stack 401, as shown in FIG. 4C. The oxide residue 411 can be removed by a dry etching process or a wet etching process as needed.

FIG. 5A depicts a schematic diagram of a multi-material layer 212 having a paired first layer 212 a and a second layer 212 b in which an oxide layer 407 is formed for use in a horizontal surround gate (hGAA) structure 500. The horizontal wrap-around gate (hGAA) structure 500 uses a multi-material layer 212 as the source/drain anchor 508 (also shown as source anchor and drain anchor 508a, 508b respectively) and the gate structure 510 Nanowires (for example, channels). As shown by the enlarged view of the multi-material layer 212 in FIG. 5B indicated by the circle 514, the oxide layer 407 formed at the bottom (for example, or end) of the second layer 212b (or as previously shown in FIG. 4B2' The oxide layer 416) can help manage the interface where the second layer 212b contacts the gate structure 510 and/or the source/drain anchors 508a, 508b in order to reduce parasitic capacitance and maintain minimal device leakage.

Therefore, a method for forming a nanowire structure with reduced parasitic capacitance and minimum device leakage for forming a horizontal surround gate (hGAA) structure is provided. These methods use a selective oxidation process to selectively form an oxide layer on certain types of materials from multiple material layers in order to form a nanowire structure with reduced parasitic capacitance and minimal device leakage at the interface. It can be used later to form a horizontal surround gate (hGAA) structure. Therefore, a horizontal wrap-around gate (hGAA) structure with desired types of materials and device electrical performance can be obtained, especially for applications in horizontal wrap-around gate field effect transistors (hGAA FET).

Although the above content is directed to the embodiments of the present invention, other and additional embodiments of the present invention can be designed without departing from the basic scope of the present invention, and the scope of the present invention is determined by the appended claims.

100‧‧‧Processing chamber 101‧‧‧Side 102‧‧‧Vacuum pump 106‧‧‧Power 110‧‧‧Controller 112‧‧‧Central Processing Unit (CPU) 114‧‧‧Support circuit 116‧‧‧Memory 118‧‧‧Signal Bus 120‧‧‧Spray head 122‧‧‧Bottom wall 124‧‧‧Top 126‧‧‧Internal volume 128‧‧‧Porosity 130‧‧‧Gas panel 132‧‧‧Processing system 138‧‧‧matching network 140‧‧‧RF power source 150‧‧‧Support base 152‧‧‧Water vapor generation (WVG) system 170‧‧‧Embedded heater element 172‧‧‧Temperature sensor 190‧‧‧Substrate 191‧‧‧surface 200‧‧‧System 202‧‧‧Front platform 206‧‧‧Tandem processing chamber 209‧‧‧Load lock chamber 211‧‧‧Transport Chamber 212‧‧‧Multi-material layer 212‧‧‧Multi-material layer 213‧‧‧Processor 214‧‧‧FOUP 244‧‧‧Central Processing Unit (CPU) 218‧‧‧Substrate Box 240‧‧‧Controller 242‧‧‧Memory 246‧‧‧Support circuit 300‧‧‧Method 302‧‧‧Operation steps 303‧‧‧Operation steps 304‧‧‧Operation steps 306‧‧‧Operation steps 401‧‧‧Film Stack 403‧‧‧Nanowire 404‧‧‧Inner lining 405‧‧‧Wall 406‧‧‧Wall 407‧‧‧Oxide layer 408‧‧‧Wall 411‧‧‧Oxide residue 416‧‧‧Oxide layer 500‧‧‧Horizontal surround gate (hGAA) structure 502‧‧‧Substrate 504‧‧‧Insulation layer 508‧‧‧Source/Drain Anchor 508a‧‧‧Source/Drain Anchor 508b‧‧‧Source/Drain Anchor 510‧‧‧Gate structure 514‧‧‧Circle

In order to be able to understand the above-mentioned features of the present invention in detail, the present invention briefly summarized above can be described in more detail by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention, as the present invention may allow other equivalent embodiments.

Figure 1 depicts a plasma processing chamber that can be used to perform a deposition process on a substrate;

Figure 2 depicts a processing system that may include the plasma processing chamber of Figure 1 to be incorporated therein;

Figure 3 depicts a flowchart of a method for manufacturing a nanowire structure formed on a substrate;

4A-4C depict cross-sectional views of an example of a sequence for forming a nanowire structure with a desired material during the manufacturing process of FIG. 3; and

Figures 5A-5B depict schematic diagrams of an example of a horizontal surround gate (hGAA) structure.

To facilitate understanding, the same element symbols have been used where possible to designate the same elements that are common to the various figures. It should be conceived that the elements and features of one embodiment can be advantageously incorporated into other embodiments without further description.

However, it should be noted that the drawings only show exemplary embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention, as the present invention may allow other equivalent embodiments.

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212‧‧‧Multi-material layer

406‧‧‧Wall

407‧‧‧Oxide layer

408‧‧‧Wall

500‧‧‧Horizontal surround gate (hGAA) structure

502‧‧‧Substrate

504‧‧‧Insulation layer

508‧‧‧Source/Drain Anchor

508a‧‧‧Source/Drain Anchor

508b‧‧‧Source/Drain Anchor

510‧‧‧Gate structure

Claims (18)

A method of forming a nanowire structure on a substrate, the method comprising the steps of: supplying an oxygen-containing gas mixture to a multi-material layer on the substrate in a processing chamber, wherein the multi-material layer includes a repeated first layer And a second layer pair, the first layer and the second layer have a first set of sidewalls and a second set of sidewalls respectively exposed through openings defined in the multi-material layer; an oxide layer is selectively formed on the second On the second set of sidewalls in the layer; and using the openings defined in the multi-material layer to form a horizontal surround gate (hGAA) structure. The method according to claim 1, wherein the step of supplying the oxygen-containing gas mixture further includes the step of: forming an inner liner layer on the first layer and the second layer before supplying the oxygen-containing gas to the substrate Layer on the first set of side walls and the second set of side walls. The method according to claim 2, wherein the lining layer is silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxynitride, or a silicon material with dopants. The method according to claim 2, wherein the liner layer is manufactured by an ALD process. The method according to claim 2, wherein the inner liner has There is a thickness between about 0.5 nm and about 5 nm. The method according to claim 2, wherein the inner liner layer has a substantially planar surface substantially parallel to the oxide layer. The method according to claim 1, wherein the oxygen-containing gas mixture includes at least one oxygen-containing gas selected from the group consisting of O ₂ , O ₃ , H ₂ O, NO ₂ , N ₂ O, steam or water vapor. The method according to claim 1, wherein the first layer in the multi-material layer is an intrinsic silicon layer, and the second layer in the multi-material layer is a SiGe layer, and the substrate is a silicon substrate. The method according to claim 1, wherein the step of supplying the oxygen-containing gas mixture further includes the step of: performing a decoupling plasma process to form the oxide layer on the second set of sidewalls in the second layer . The method according to claim 1, further comprising the step of: performing a cleaning process to remove oxide residues from the substrate. The method according to claim 1, wherein the multi-material layer includes at least four repeated pairs. The method according to claim 1, wherein the oxide layer has a thickness between about 1 nm and about 10 nm. The method according to claim 1, wherein the step of supplying the oxygen-containing gas mixture further includes the following steps: Maintain the substrate temperature between about 200 degrees Celsius and about 1000 degrees Celsius. The method according to claim 1, wherein the oxide layer is selectively formed by an ultraviolet (UV) light irradiation process. A method of forming a nanowire structure on a substrate, the method comprising the following steps: mainly forming an oxide layer on a part of a multi-material layer provided on the substrate, wherein the multi-material layer includes repeated first and second layers A pair of layers, the first layer and the second layer have a first set of sidewalls and a second set of sidewalls respectively exposed through openings defined in the multi-material layer, wherein the oxide layer is selectively formed on the second layer On the second set of sidewalls in, the multi-material layer is used to form nanowires or channels in a horizontal wrap-around gate (hGAA) structure. The method according to claim 15, wherein the first layer in the multi-material layer is an intrinsic silicon layer, and the second layer in the multi-material layer is a SiGe layer, and the substrate is a silicon substrate. The method according to claim 15, further comprising the step of: before forming the oxide layer, forming an inner liner layer on the first set of sidewalls and the second set of sidewalls of the first layer and the second layer. A method for forming a nanowire structure on a substrate. The method includes the following steps: An oxide layer is mainly formed on a part of a multi-material layer provided on a substrate, wherein the multi-material layer includes a repeated pair of a silicon layer and a SiGe layer, and the silicon layer and the SiGe layer have openings respectively defined in the multi-material layer. The exposed first group of sidewalls and second group of sidewalls, wherein the portion on which the oxide layer is selectively formed is located on the second group of sidewalls in the SiGe layer.

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