TW201724500A - Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications - Google Patents

Abstract

The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.

Description

Method for fabricating a nanowire for a horizontal wraparound gate device for semiconductor applications

Embodiments of the present invention generally relate to a method for forming vertically stacked nanowires on a semiconductor substrate using a desired material, and more particularly, for forming vertically stacked nanowires in a semiconductor using a desired material A method for use in field effect transistor (FET) semiconductor fabrication applications on a substrate.

Reliable production of sub-half micron and smaller features is one of the key technical challenges for next-generation ultra-large integrated circuits (VLSI) and ultra-large integrated circuits (ULSI) semiconductor devices. However, as circuit technology advances, shrink-sized VLSI and ULSI technologies have additional demands on processing power. The reliable formation of gate structures on the substrate is successful for VLSI and ULSI and is important for continued efforts to increase circuit density and quality of individual substrates and dies.

As the circuit density of next-generation devices increases, the width of interconnects (such as vias, trenches, contacts, gate structures and other features, and dielectric materials between them) is reduced to 25 nm and 20 nm. The size is smaller and the thickness of the dielectric layer remains substantially constant, whereby the aspect ratio of the feature is increased. In addition, the reduced channel length typically results in significant short channel effects in conventional planar MOSFET architectures. In order to be able to manufacture next generation devices and structures, three dimensional (3D) device structures are commonly used to improve the performance of transistors. In particular, fin field effect transistors (FinFETs) are commonly used to enhance device performance. FinFET devices typically include a semiconductor fin having a high aspect ratio in which the channel and source/drain regions for the transistor are formed on the semiconductor fins. Subsequently, the gate electrode utilizes the advantages of the increased surface area of the channel and source/drain regions over and along the sides of a portion of the fin device to produce a faster, more reliable, and better controlled semiconductor. Transistor device. Additional advantages of FinFETs include reducing short channel effects and providing higher currents. Device configurations with hGAA configurations typically provide superior static control by surrounding the gates to suppress short channel effects and associated leakage currents.

In some applications, horizontal wraparound gate (hGAA) structures are used in next generation semiconductor device applications. The hGAA device structure includes a number of lattice matching channels (eg, nanowires) suspended in a stacked configuration and connected by source/drain regions.

In hGAA structures, different materials are typically used to form channel structures (eg, nanowires), which would undesirably increase manufacturing in integrating all of these materials into the nanowire structure without reducing device performance. Difficulty. For example, one of the challenges associated with hGAA structures involves the presence of large parasitic capacitances between the metal gate and the source/drain. Improper management of such parasitic capacitance can result in a significant reduction in device performance.

Accordingly, there is a need for an improved method for forming a channel structure for forming an hGAA device structure on a substrate with good profile and size.

The present disclosure provides a method for forming a nanowire structure of a horizontal wraparound gate (hGAA) structure of a semiconductor wafer using a desired material. In one example, a method of forming a nanowire structure on a substrate includes: supplying an oxygen-containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes a repeating first layer and a second layer pair, the first layer and the second layer having a first set of sidewalls and a second set of sidewalls exposed through openings defined in the multi-material layer, respectively; and a layer selectively forming the oxide layer in the second layer On the side walls of the two groups.

In another example, a method of forming a nanowire structure on a substrate includes: forming an oxide layer primarily on a portion of a multi-material layer disposed on a substrate, wherein the multi-material layer includes a repeating first layer and a second a pair of layers, the first layer and the second layer having a first set of sidewalls and a second set of sidewalls exposed via openings defined in the multi-material layer, respectively, wherein the oxide layer is selectively formed in the second group of the second layer On the side wall.

In yet another example, a method of forming a nanowire structure on a substrate includes: forming an oxide layer primarily on a portion of a multi-material layer disposed on a substrate, wherein the multi-material layer comprises a repeating layer of tantalum and SiGe layers The germanium layer and the SiGe layer have a first set of sidewalls and a second set of sidewalls exposed via openings defined in the multi-material layer, respectively, wherein the portion of the oxide layer selectively formed thereon is located in the second portion of the SiGe layer On the side wall of the group.

A method of fabricating a nanowire structure having a controlled parasitic capacitance for fabricating a horizontal wraparound gate (hGAA) semiconductor device structure is provided. In one example, a superlattice structure including different materials (eg, a first material and a second material) arranged in an alternating stacked configuration may be formed on a substrate to be used later as a horizontal wraparound A nanowire (eg, channel structure) of a gate (hGAA) semiconductor device structure. A selective oxidation process can be performed to selectively form an oxide layer on the sidewalls of the first material in the superlattice structure with minimal oxidation occurring on the second material. The oxidation selectivity on the sidewalls of the first material and the second material in the superlattice structure is greater than 5:1. By this, the interface in which the parasitic device is formed between the nanowire and the source/drain region is maintained and controlled to effectively reduce the parasitic capacitance.

FIG. 1 is a cross-sectional view of an illustrative processing system 132 suitable for performing a selective oxidation process as further described below. Treatment system 132 can be a CENTURA® and Producer® SE or Producer® GT deposition system, all of which are commercially available from Applied Materials Inc., Santa Clara, California. It is contemplated that other processing systems, including those that are available from other manufacturers, may be adapted to practice the invention.

Processing system 132 includes a processing chamber 100 that is coupled to gas panel 130 and controller 110. Processing chamber 100 generally includes a top portion 124, side portions 101, and a bottom wall 122 that define an interior volume 126.

Support base 150 is provided in interior volume 126 of chamber 100. The susceptor 150 can be made of aluminum, ceramic, and other suitable materials. In one embodiment, the susceptor 150 is made of a ceramic material, such as aluminum nitride, which is suitable for use in a high temperature environment, such as a plasma processing environment, without causing a susceptor to the susceptor 150. Thermal damage. The susceptor 150 can be moved in the vertical direction within the chamber 100 using a lifting mechanism (not shown).

The pedestal 150 can include an embedded heater element 170 that is adapted to control the temperature of the substrate 190 supported on the susceptor 150. In one embodiment, the susceptor 150 can be resistively heated by applying a current from the power source 106 to the heater element 170. In one embodiment, the heater element 170 can be made of a nickel-chromium wire encapsulated in a nickel-iron-chromium alloy (eg, INCOLOY®) sheath. The current supplied from the power source 106 is regulated by the controller 110 to control the heat generated by the heater element 170, thereby maintaining the substrate 190 and the susceptor 150 substantially constant during film deposition at any suitable temperature range. temperature. In another embodiment, the susceptor can be maintained at room temperature as needed. In yet another embodiment, the susceptor 150 can also include a cooler (not shown) as needed to cool the susceptor 150 in a range below room temperature as desired. The supplied current can be adjusted to selectively control the temperature of the susceptor 150 between about 100 degrees Celsius and about 1100 degrees Celsius, for example, between 200 degrees Celsius and about 1000 degrees Celsius, such as between about 300 degrees Celsius and about 800 degrees Celsius. between.

A temperature sensor 172, such as a thermocouple, can be embedded in the support base 150 to monitor the temperature of the base 150 in a conventional manner. The measured temperature will be used by controller 110 to control the power supplied to heater element 170 to maintain the substrate at a desired temperature.

The vacuum pump 102 is coupled to a bore formed in the wall 101 of the chamber 100. Vacuum pump 102 is used to maintain a desired gas pressure in processing chamber 100. The vacuum pump 102 also evacuates the treated gas from the chamber 100 and by-products of the process.

A showerhead 120 having a plurality of apertures 128 is coupled to the top 124 of the processing chamber 100 above the substrate support pedestal 150. The apertures 128 of the showerhead 120 are used to introduce process gases into the chamber 100. The apertures 128 can have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases for different process requirements. The showerhead 120 is coupled to the gas panel 130 to allow various gases to be supplied to the interior volume 126 during the process. The plasma is formed by a process gas mixture exiting the showerhead 120 to enhance the pyrolysis of the process gas, thereby causing material to deposit on the surface 191 of the substrate 190.

The showerhead 120 and the substrate support pedestal 150 can be formed as a pair of spaced apart electrodes in the interior volume 126. One or more RF power sources 140 provide a bias potential to the showerhead 120 via the matching network 138 to facilitate the generation of plasma between the showerhead 120 and the susceptor 150. Alternatively, the RF power source 140 and the matching network 138 can be coupled to the showerhead 120, the substrate support pedestal 150, or to both the showerhead 120 and the substrate support pedestal 150, or coupled to An antenna (not shown) outside the chamber 100. In one embodiment, RF power source 140 can provide between about 10 watts and about 3000 watts at a frequency of about 30 kHz to about 13.6 MHz.

An optional water vapor generation (WVG) system 152 is coupled to the processing system 132 that is in fluid communication with an interior volume 126 defined in the processing chamber 100. The WVG system 152 produces ultra high purity water vapor by catalytic reaction of O ₂ and H ₂ . In one embodiment, the WVG system 152 has a reactor or catalyst cartridge lined with a catalyst wherein water vapor is produced by chemical reaction. The catalyst can include metals or alloys such as palladium, platinum, nickel, combinations thereof, and alloys thereof.

The controller 110 includes a central processing unit (CPU) 112, a memory 116, and a support circuit 114 for controlling the flow of the program and regulating the flow of gases from the gas panel 130 and the WVG system 152. CPU 112 can be any form of general purpose computer processor that can be used in an industrial environment. The software routine can be stored in memory 116 (such as random access memory, read only memory, floppy or hard disk drive, or other form of digital storage device). Support circuitry 114 is conventionally coupled to CPU 112 and may include cache memory, clock circuitry, input/output systems, power supplies, and the like. Bidirectional communication between controller 110 and various components of processing system 132 is processed via a number of signal cables (collectively referred to as signal busses 118, some of which are shown in Figure 1).

2 depicts a plan view of a semiconductor processing system 200 in which the methods described herein can be practiced. A benefit of the present invention is suitable for processing from the system are commercially available from Applied Materials, Santa Clara, Calif. Company business 300mm Producer ^TM processing system. The processing system 200 generally includes a front platform 202 in which a substrate cassette 218 included in the FOUP 214 is supported and the substrate is loaded into and unloaded from the load lock chamber 209; the transfer chamber 211, the transfer The chamber houses the substrate processor 213; and a series of tandem processing chambers 206 on which the tandem processing chambers are mounted.

Each of the series processing chambers 206 includes two process areas for processing the substrate. The two process zones share a common gas supply, shared pressure control, and a shared process gas discharge/pumping system. The modular design of the system enables rapid conversion from any configuration to any other configuration. The arrangement and combination of chambers can be altered for the purpose of performing a particular process step. In accordance with aspects of the present invention, any of the tandem processing chambers 206 can include a cover as described below that includes one or more chamber configurations as described above with respect to the processing chamber 100 depicted in FIG. It should be noted that the processing chamber 100 can be configured to perform a deposition process, an etching process, a curing process, or a heating/annealing process as needed. In one embodiment, the processing chamber 100, shown as a single chamber designed, can be incorporated into the semiconductor processing system 200.

In one embodiment, the processing system 132 can be adapted with one or more of a series of processing chambers having known adaptations to various other known processes, such as chemical vapor deposition (CVD). Support chamber hardware for physical vapor deposition (PVD), etching, curing or heating/annealing, etc. For example, system 200 can be configured with one of processing chambers 100 as a plasma deposition chamber for depositing, for example, a dielectric film on a substrate. This configuration maximizes research and development manufacturing utilization and, if desired, reduces exposure of the etched film to the atmosphere.

Controller 240, including central processing unit (CPU) 244, memory 242, and support circuitry 246, is coupled to various components of semiconductor processing system 200 to facilitate control of the process of the present invention. Memory 242 can be any computer readable medium, such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage device (whether semiconductor processing system 200) Or the local end of the CPU 244 is still remote). Support circuitry 246 is coupled to CPU 244 to support the CPU in a conventional manner. These circuits include cache memory, power supplies, clock circuits, input/output circuits and subsystems, and the like. The software routine or series of program instructions stored in the memory 242, when executed by the CPU 244, executes the serial processing chamber 206.

3 is a flow diagram of one example of a method 300 for fabricating a nanowire structure (eg, a via structure) using a composite material for a horizontal wraparound gate (hGAA) semiconductor device structure. 4A-4C are cross-sectional views of a portion of a composite substrate corresponding to various stages of method 300. The method 300 can be used to form a nanowire structure of a desired structure of a horizontal wraparound gate (hGAA) semiconductor device structure on a substrate that can later be used to form a field effect transistor (FET). Alternatively, method 300 can be beneficially used to fabricate other types of structures.

The method 300 begins at operation 302 by providing a substrate, such as the substrate 502 depicted in FIG. 2 having the thin film stack 401 formed thereon as shown in FIG. 4A. The substrate 502 can be a material such as crystalline germanium (eg, Si<100> or Si<111>), germanium oxide, strained germanium, germanium telluride, germanium, doped or undoped poly germanium, doped or undoped. Tantalum wafers and germanium (SOI), carbon doped yttria, tantalum nitride, doped ytterbium, ytterbium, gallium arsenide, glass or sapphire on patterned or unpatterned wafer insulators. The substrate 502 can have various dimensions, such as 200 mm, 300 mm, 450 mm, or other diameters, and can be a rectangular or square panel. The examples described herein were performed on a substrate having a diameter of 200 mm, a diameter of 300 mm, or a diameter of 450 mm, unless otherwise indicated.

The film stack 401 includes a multi-material layer 212 disposed on an optional material layer 504. In embodiments in which optional material layer 504 is absent, thin film stack 401 can be formed directly on substrate 502 as desired. In one example, the optional material layer 504 is an insulating material. Suitable examples of the insulating material may include a cerium oxide material, a tantalum nitride material, a cerium oxynitride material, or any suitable insulating material. Alternatively, optional material layer 504 can be any suitable material, including conductive or non-conductive materials, as desired. The multi-material layer 212 includes at least one pair of layers, each pair including a first layer 212a and a second layer 212b. Although the example depicted in FIG. 4A shows four pairs, each pair including a first layer 212a and a second layer 212b (alternating pairs, each pair including a first layer 212a and a second layer 212b), it should be noted that the logarithm (per The pair including the first layer 212a and the second layer 212b) may vary based on different process needs. In one particular embodiment, four pairs of first layer 212a and second layer 212b can be deposited to form a multi-material layer 212 on substrate 502. In one embodiment, the thickness of each individual first layer 212a can be between about 20 Å and about 200 Å, such as about 50 Å, and the thickness of each individual second layer 212b can be between about 20 Å and about 200 Å, such as about 50 Å. . The multi-material layer 212 can have a total thickness between about 10 Å and about 5000 Å, such as between about 40 Å and about 4000 Å.

The first layer 212a may be a crystalline germanium layer formed by an epitaxial deposition process, such as a single crystalline germanium layer, a polycrystalline germanium layer, or a monocrystalline germanium layer. Alternatively, the first layer 212a may be a doped germanium layer, including a p-type doped germanium layer or an n-type doped germanium layer. Suitable p-type dopants include B dopants, Al dopants, Ga dopants, In dopants, and the like. Suitable n-type dopants include N dopants, P dopants, As dopants, Sb dopants, and the like. In yet another example, the first layer 212a can be a Group III-V material, such as a GaAs layer. The second layer 212b can be a Ge-containing layer, such as a SiGe layer, a Ge layer, or other suitable layer. Alternatively, the second layer 212b may be a doped germanium layer, including a p-type doped germanium layer or an n-type doped germanium layer. In yet another example, the second layer 212b can be a Group III-V material, such as a GaAs layer. In yet another example, the first layer 212a can be a tantalum layer and the second layer 212b is a metallic material having a high dielectric constant material coating on the outer surface of the metallic material. Suitable examples of high dielectric constant materials include hafnium oxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), hafnium oxyhydroxide (HfSiO ₄ ), hafnium aluminum oxide (HfAlO), zirconium oxysulfate (ZrSiO ₄ ), Cerium oxide (TaO ₂ ), aluminum oxide, aluminum-doped cerium oxide, barium titanate (BST) or platinum zirconium titanate (PZT), and the like. In a particular embodiment, the coating is a layer of hafnium oxide (HfO ₂ ).

In the particular example depicted in FIG. 4A, the first layer 212a is a crystalline germanium layer, such as a single crystal germanium layer, a polycrystalline germanium layer, or a single crystalline germanium layer. The second layer 212b is a SiGe layer.

In some examples, a hard mask layer (not shown in FIG. 4A) and/or a patterned photoresist layer can be disposed over the multi-material layer 212 to pattern the multi-material layer 212. In the example illustrated in FIG. 4A, the multi-material layer 212 has been patterned in a previous patterning process to form openings 402 in the multi-material layer 212, which may later have source/drain anchor formation In it.

In embodiments where the substrate 502 is a crystalline germanium layer and the insulating layer 504 is a hafnium oxide layer, the first layer 212a can be an intrinsic epitaxial layer and the second layer 212b is a SiGe layer. In another embodiment, the first layer 212a can be a layer containing doped germanium, and the second layer 212b can be an intrinsic epitaxial layer. The layer containing the erbium-doped layer may be a p-type dopant or an n-type dopant, or a SiGe layer as needed. In yet another embodiment in which the substrate 502 is a Ge or GaAs substrate, the first layer 212a can be a GeSi layer and the second layer 212b can be an intrinsic epitaxial Ge layer, or vice versa. In yet another embodiment in which the substrate 502 is a GaAs layer having predominantly a crystal plane at <100>, the first layer 212a can be an intrinsic Ge layer and the second layer 212b can be a GaAs layer, or vice versa. It should be noted that the substrate material and the selection of the first layer 212a and the second layer 212b in the multi-material layer 212 may be in various combinations utilizing the materials listed above.

At optional operation 303, an inner liner layer 404 can be formed on sidewall 405 of multi-material layer 212, as shown in Figure 4B2. The inner liner layer 404 can provide a substantially planar (e.g., uniform) surface that allows the oxide layer to be later formed thereon with good interface adhesion and flatness. The process for forming the oxide layer will be described later at operation 304. Thus, in embodiments where the sidewall 405 of the multi-material layer 212 is a substantially planar having a desired straightness, the liner layer 404 can be attenuated, and at operation 304, an oxide layer can be formed directly on the multi-material layer 212. On the side wall 405.

In one example, the inner liner layer 404 can be selected from materials that can help bridge the oxide layer to the sidewalls 405 of the multi-material layer 212 with good adhesion at the interface. Additionally, the inner liner layer 404 can have a sufficient thickness to be filled from the sidewalls 405 of the multi-material layer 212 in the nano-scale rough surface to provide a substantially planar surface that allows the oxide layer to be later at a desired level The flatness and flatness are formed thereon. In one example, the inner liner layer 404 can have a thickness between about 0.5 nm and about 5 nm.

In one embodiment, the inner liner layer 404 is a germanium-containing dielectric layer, such as a tantalum nitride-containing layer, a tantalum carbide-containing layer, a hafnium oxide-containing layer, such as SiN, SiON, SiC, SiCN, SiOC, or oxygen. Niobium carbonitride or tantalum material with dopants, and the like. The dopant formed in the germanium-containing dielectric layer may have a relatively low concentration and have a thin film-rich film property. In one example, the inner liner layer 404 is a tantalum nitride layer or tantalum oxynitride (SiON) having a thickness between about 5 Å and about 50 Å, such as about 10 Å. The liner layer 404 can be formed by a CVD process, an ALD process, or any suitable deposition technique in a PVD, CVD, ALD, or other suitable plasma processing chamber.

At operation 304, after the optional liner layer 404 is formed on the sidewall 405 of the multi-material layer 212, selective oxide deposition may be performed to selectively form an oxide layer on certain regions of the multi-material layer 212. . In an example in which the optional operation 303 is not performed and the inner liner layer 404 is not formed on the substrate, the selective oxide deposition process can be performed directly on the substrate, as mentioned in FIG. 4B1.

Since the first layer 212a and the second layer 212b of the multi-material layer 212 are made of different materials, when a selective oxide deposition process is performed, the oxidation process can occur mainly on one material with respect to another material. In the example depicted in FIG. 4B1, where the first layer 212a is a germanium layer and the second layer 212b is a SiGe layer, the selective oxidation process can occur primarily on the sidewall 406 of the second layer 212b rather than in the first layer. On 212a. The selective oxidation process occurring on sidewall 406 of second layer 212b primarily forms oxide layer 407 on sidewall 406 of second layer 212b. It is believed that the SiGe alloy has a higher activity than the main bismuth-containing material. Therefore, when oxygen atoms are supplied, the oxygen atoms tend to react with Si atoms in the SiGe alloy at a faster reaction rate than with Si atoms from the main germanium-containing material, thereby providing a selective deposition process for the main An oxide layer 407 is formed on the sidewall 406 of the second layer 212b of the SiGe alloy rather than on the first layer 212a. A minimum oxide residue 411 can be present on the sidewall 408 of the first layer 212a.

The oxidation process consumes germanium atoms from the SiGe alloy in the second layer 212b, thereby pulling the germanium atoms outward to react with the oxygen atoms to form the oxide layer 407. Since the Ge atoms can be relatively easily activated and moved during the oxidation process, the germanium atoms in the second layer 212b are gradually pulled out and react with the oxygen atoms to form an oxide layer 407 on the sidewalls 406.

In contrast, the oxidation in the first layer 212a is due to the fact that the germanium atoms in the first layer 212a do not have Ge atoms as active drives in order to actively push the germanium atoms outwardly to a position that allows the reaction to react with the oxygen atoms. The layer formation rate is significantly lower than the oxide layer formation rate in the second layer 212b, thereby providing a selective oxidation process that primarily forms oxidation on the sidewall 406 of the second layer 212b rather than on the first layer 212a. Layer 407. In one example, the selectivity of the oxidation rate between the second layer 212b (eg, a SiGe layer) and the first layer 212a (eg, a germanium layer) is greater than 5:1, such as about 6:1 and 10:1.

In one embodiment, the selective oxidation process can be performed in a suitable plasma processing chamber, including a processing chamber, such as the processing chamber 100 depicted in FIG. 1 or other suitable plasma chamber. The processing temperature is controlled within a low temperature range, such as less than 1200 degrees Celsius. It is believed that the low temperature process can provide mild thermal energy to deplete helium atoms and push the helium atoms toward the surface of the sidewall where oxygen atoms are present to form the hafnium oxide 407 without damaging the crystal lattice formed by the Ge atoms in the thin film stack 401. structure. By this, a part of the germanium atom can be gradually converted into the oxide layer 407 without forming an interface portion or an atomic vacancy. In one embodiment, the process temperature can be achieved between about 100 degrees Celsius and about 1100 degrees Celsius, for example between 200 degrees Celsius and about 1000 degrees Celsius, such as between about 300 degrees Celsius and about 800 degrees Celsius.

In one embodiment, the oxidation process can be in a plasma containing environment (such as decoupled plasma oxidation or rapid thermal oxidation), a thermal environment (such as a furnace), or a thermoplasm environment (such as APCVD, SACVD, LPCVD, or any suitable CVD). Execution in the process). The oxidation process can be performed by using an oxygen-containing gas mixture in a processing environment to cause the multi-material layer 212 to react. In one embodiment, the oxygen-containing gas mixture includes at least one of an oxygen-containing gas with or without an inert gas. Suitable examples of oxygen-containing gases include O ₂ , O ₃ , H ₂ O, NO ₂ , N ₂ O, steam, water vapor, and the like. Suitable examples of the inert gas supplied with the treatment gas mixture include at least one of Ar, He, Kr, and the like. In an exemplary embodiment, the oxygen-containing gas supplied in the oxygen-containing gas mixture is an O ₂ gas having a flow rate between about 50 sccm and about 1000 sccm.

During the oxidation process, several process parameters can be adjusted to control the oxidation process. In an exemplary embodiment, the process pressure is adjusted to be between about 0.1 Torr and about atmospheric pressure (eg, 760 Torr). In one example, the oxidation process as performed at operation 304 is configured to have a relatively high deposition pressure, such as a pressure greater than 100 Torr, such as between about 300 Torr and atmospheric pressure. Suitable techniques that can be used to perform the selective oxidation process at operation 304 can include decoupling plasma oxidation processes (DPO), plasma enhanced chemical vapor deposition processes (PECVD), low pressure chemical vapor deposition processes (LPCVD), Sub-atmospheric chemical vapor deposition process (SACVD), atmospheric pressure chemical vapor deposition process (APCVD), hot furnace process, oxygen annealing process, plasma immersion process, or any suitable process. In one embodiment, the oxidation process can be performed under ultraviolet (UV) light illumination.

In one embodiment, the oxidation process is completed when the desired thickness of oxide layer 407 is formed on sidewall 406 of second layer 212b. In one example, oxide layer 407 can have a thickness between about 1 nm and about 10 nm. The total processing time of the oxidation process can be determined by the time pattern after the desired portion of the germanium atoms primarily reacts with the oxygen atoms to form the oxide layer 407 of the desired thickness. In one example, substrate 502 is subjected to a selective oxidation process of from about 5 seconds to about 5 minutes, depending on the rate of oxidation of second layer 212b, the pressure of the gas, and the flow rate. In an exemplary embodiment, substrate 502 is exposed to an oxidation process for about 600 seconds or less.

Further, in an example in which the inner liner layer 404 is formed on the sidewall 405 of the multi-material layer 212, when the selective oxidation process is performed at operation 304, similarly, the oxide layer 416 may be selectively formed only on the second layer. The sidewall 406 of 212b is in contact with the inner liner layer 404 as shown in Figure 4B2'. As discussed above, the GeSi alloy in the second layer 212b is more active than the Si material present in the first layer 212a. During the oxidation process, the Ge atoms can be activated by thermal energy from the oxidation process to form interface vacancies that allow the oxygen atoms to be pulled in to bond with the germanium atoms. Thus, oxygen atoms from the selective oxidation process pass through the inner liner layer 404 to react with the germanium atoms from the second layer 212b to form an oxide layer 416 on the sidewalls 406 of the second layer 212b. Since the inner liner layer 404 provides a substantially planar surface on the sidewall 405 of the multi-material layer 212, the oxide layer 416 formed in the second layer 212b below the inner liner layer 404 can still maintain substantially the sidewall 405. A planar surface to provide a straight sidewall profile for the nanowire structure as needed. In one embodiment, the inner liner layer 404 in combination with the oxide layer 416 can have a thickness between about 3 nm and about 15 nm, such as between about 7 nm and about 8 nm.

After the oxide layers 416, 407 are formed in the thin film stack 401, the multi-material layer 212 of the first layer 212a and the second layer 212b having the oxide layers 416, 407 formed to the bottom thereof can be used as having a reduced parasitic capacitance and a minimum The nanowire 403 in the field effect transistor (FET) that the device leaks.

At operation 306, a gentle surface cleaning process is performed to selectively remove oxide residue 411 (if present) from film stack 401 without damaging the surface of film stack 401, as shown in Figure 4C. The oxide residue 411 can be removed by a dry etching process or a wet etching process as needed.

FIG. 5A depicts a schematic diagram of a multi-material layer 212 having a pair of first layers 212a and a second layer 212b having oxide layers 407 formed therein in a horizontal wraparound gate (hGAA) structure 500. Horizontal wraparound gate (hGAA) structure 500 uses multi-material layer 212 as source/drain anchor 508 (also shown as source and drain anchor heads 508a, 508b, respectively) and gate structure 510 The nanowire (for example, the channel). As shown in the enlarged view of the multi-material layer 212 in FIG. 5B indicated by circle 514, an oxide layer 407 is formed at the bottom (eg, or end) of the second layer 212b (or as previously shown in FIG. 4B2') The oxide layer 416) can help manage the interface in which the second layer 212b is in contact with the gate structure 510 and/or the source/drain anchor heads 508a, 508b in order to reduce parasitic capacitance and maintain minimal device leakage.

Accordingly, a method for forming a horizontal wraparound gate (hGAA) structure with a reduced parasitic capacitance and minimal device leakage nanowire structure is provided. The methods utilize a selective oxidation process to selectively form an oxide layer on certain types of materials from a multi-material layer to form a nanowire structure having reduced parasitic capacitance and minimal device leakage at the interface. It can be used later to form a horizontal wraparound gate (hGAA) structure. Thus, a horizontal wraparound gate (hGAA) structure with the desired type of material and device electrical performance can be obtained, particularly for horizontal wraparound gate field effect transistors (hGAA FETs).

While the foregoing is directed to embodiments of the present invention, other and additional embodiments of the present invention may be devised without departing from the scope of the invention.

100‧‧‧Processing chamber
101‧‧‧ side
102‧‧‧vacuum pump
106‧‧‧Power supply
110‧‧‧ Controller
112‧‧‧Central Processing Unit (CPU)
114‧‧‧Support circuit
116‧‧‧ memory
118‧‧‧Signal bus
120‧‧‧Sprinkler
122‧‧‧ bottom wall
124‧‧‧ top
126‧‧‧ internal volume
128‧‧‧ pores
130‧‧‧ gas panel
132‧‧‧Processing system
138‧‧‧match network
140‧‧‧RF power source
150‧‧‧Support base
152‧‧‧Water Vapor Generation (WVG) System
170‧‧‧Embedded heater components
172‧‧‧temperature sensor
190‧‧‧Substrate
191‧‧‧ surface
200‧‧‧ system
202‧‧‧Front platform
206‧‧‧Sequential processing chamber
209‧‧‧Load lock chamber
211‧‧‧Transfer chamber
212‧‧‧Multiple material layers
212‧‧‧Multiple material layers
213‧‧‧ processor
214‧‧‧FOUP
244‧‧‧Central Processing Unit (CPU)
218‧‧‧Substrate box
240‧‧‧ Controller
242‧‧‧ memory
246‧‧‧Support circuit
300‧‧‧ method
302‧‧‧Operating steps
303‧‧‧Operation steps
304‧‧‧Operating steps
306‧‧‧Operating steps
401‧‧‧ film stacking
403‧‧‧Nami Line
404‧‧‧Inner lining
405‧‧‧ side wall
406‧‧‧ side wall
407‧‧‧Oxide layer
408‧‧‧ side wall
411‧‧‧Oxide residues
416‧‧‧Oxide layer
500‧‧‧ horizontal wraparound gate (hGAA) structure
502‧‧‧Substrate
504‧‧‧Insulation
508‧‧‧Source/Bungee Anchor Head
508a‧‧‧Source/Bungee Anchor Head
508b‧‧‧Source/Bungee Anchor Head
510‧‧ ‧ gate structure
514‧‧‧ circle

The invention briefly summarized above will be described in detail by reference to the embodiments of the invention. It is to be understood, however, that the appended claims are in the

Figure 1 depicts a plasma processing chamber that can be used to perform a deposition process on a substrate;

2 depicts a processing system that can include the plasma processing chamber of FIG. 1 to be incorporated therein;

3 depicts a flow chart of a method for fabricating a nanowire structure formed on a substrate;

4A-4C depict cross-sectional views of one example of a sequence for forming a nanowire structure with a desired material during the fabrication process of FIG. 3;

5A-5B depict schematic diagrams of examples of horizontal wraparound gate (hGAA) structures.

To promote understanding, the same component symbols have been used where possible to designate the same components that are common to the various figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

It is to be understood, however, that the appended claims

Domestic deposit information (please note according to the order of the depository, date, number)

Foreign deposit information (please note in the order of country, organization, date, number)

(Please change the page separately) No

212‧‧‧Multiple material layers

406‧‧‧ side wall

407‧‧‧Oxide layer

408‧‧‧ side wall

500‧‧‧ horizontal wraparound gate (hGAA) structure

502‧‧‧Substrate

504‧‧‧Insulation

508‧‧‧Source/Bungee Anchor Head

508a‧‧‧Source/Bungee Anchor Head

508b‧‧‧Source/Bungee Anchor Head

510‧‧ ‧ gate structure

Claims (20)

A method of forming a nanowire structure on a substrate, the method comprising the steps of: supplying an oxygen-containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer comprises a repeating first layer And a second layer pair, the first layer and the second layer having a first set of sidewalls and a second set of sidewalls exposed through openings defined in the multi-material layer, respectively; and selectively forming an oxide layer thereon On the second set of sidewalls in the second layer. The method of claim 1, wherein the step of supplying the oxygen-containing gas mixture further comprises the step of: forming an inner liner layer on the first layer and the second before supplying the oxygen-containing gas to the substrate The first set of sidewalls of the layer and the second set of sidewalls. The method of claim 2, wherein the inner liner is tantalum nitride, hafnium oxynitride, tantalum carbonitride, niobium carbonitride or hafnium oxynitride or tantalum material having a dopant. The method of claim 2, wherein the inner liner is fabricated by an ALD process. The method of claim 2, wherein the inner liner layer has a thickness between about 0.5 nm and about 5 nm. The method of claim 2 wherein the inner liner has a substantially planar surface that is substantially parallel to the oxide layer. The method of claim 1, wherein the oxygen-containing gas mixture comprises at least one oxygen-containing gas selected from the group consisting of O ₂ , O ₃ , H ₂ O, NO ₂ , N ₂ O, steam, or water vapor. The method of claim 1, wherein the first layer of the multi-material layer is an intrinsic germanium layer, and the second layer of the multi-material layer is a SiGe layer while the substrate is a germanium substrate. The method of claim 1, further comprising the step of: forming a horizontal wraparound gate (hGAA) structure using the openings defined in the multi-material layer. The method of claim 1, wherein the step of supplying the oxygen-containing gas mixture further comprises the step of: performing a decoupling plasma process to form the oxide layer on the second set of sidewalls in the second layer . The method of claim 1, further comprising the step of: performing a cleaning process to remove oxide residues from the substrate. The method of claim 1, wherein the multi-material layer comprises at least four repeating pairs. The method of claim 1, wherein the oxide layer has a thickness between about 1 nm and about 10 nm. The method of claim 1, wherein the step of supplying the oxygen-containing gas mixture further comprises the step of: maintaining the substrate temperature between about 200 degrees Celsius and about 1000 degrees Celsius. The method of claim 1, wherein the oxide layer is selectively formed by an ultraviolet (UV) light irradiation process. A method of forming a nanowire structure on a substrate, the method comprising the steps of: forming an oxide layer on a portion of a multi-material layer disposed on a substrate, wherein the multi-material layer comprises a repeating first layer and a second a pair of layers, the first layer and the second layer having a first set of sidewalls and a second set of sidewalls exposed via openings defined in the multi-material layer, respectively, wherein the oxide layer is selectively formed on the second layer On the second set of side walls. The method of claim 16, wherein the first layer of the multi-material layer is an intrinsic germanium layer, and the second layer of the multi-material layer is a SiGe layer while the substrate is a germanium substrate. The method of claim 16, further comprising the step of: forming an inner liner layer on the first set of sidewalls and the second set of sidewalls of the first layer and the second layer prior to forming the oxide layer. The method of claim 16 wherein the multi-material layer is used to form a nanowire or channel in a horizontal wraparound gate (hGAA) structure. A method of forming a nanowire structure on a substrate, the method comprising the steps of: forming an oxide layer on a portion of a multi-material layer disposed on a substrate, wherein the multi-material layer comprises a repeating layer of tantalum and SiGe layers The germanium layer and the SiGe layer have a first set of sidewalls and a second set of sidewalls exposed through openings defined in the multi-material layer, respectively, wherein the portion of the oxide layer selectively formed thereon is located in the SiGe On the second set of sidewalls in the layer.