CN102148184B

CN102148184B - Method for improving roughness of side wall of shallow trench isolation

Info

Publication number: CN102148184B
Application number: CN201110061647.1A
Authority: CN
Inventors: 张振兴; 奚裴
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-03-15
Filing date: 2011-03-15
Publication date: 2015-06-10
Anticipated expiration: 2031-03-15
Also published as: CN102148184A

Abstract

The invention relates to a method for improving the roughness of the side wall of shallow trench isolation, comprising the following steps of: providing a semiconductor substrate, preparing a hard mask, depositing a bottom anti-reflection coating, and etching a shallow trench. The bottom anti-reflection coating is deposited on the hard mask, and the etching gases and flows of the bottom anti-reflection coating are as follows: the helium-oxygen flow is 4-8sccm, and the flow ratio of carbon tetrafluoride to helium is 1.6-2.0. The thickness of the bottom anti-reflection coating is 500-700A. The hard mask is a silicon nitride layer. An oxygen cushion layer is formed between the hard mask and the semiconductor substrate. In the invention, a thin bottom anti-reflection coating is adopted, the composition and flow of the etching gas of the bottom anti-reflection coating are controlled to improve the roughness of the side wall of shallow trench isolation, and optical loss is reduced.

Description

Improve the method for roughness of side wall of shallow trench isolation

Technical field

The present invention relates to the preparation method of shallow trench isolation from (Shallow Trench Isolation, STI), particularly relate to a kind of method improving roughness of side wall of shallow trench isolation.

Background technology

Along with the development of integrated circuit, present CMOS chip is integrated millions of active device on one piece of common silicon substrate material usually, such as nmos pass transistor and PMOS transistor etc., then connect by specific the logic function or the analog functuion that realize various complexity, and except these specific functions, in the design process of circuit, between the device that hypothesis is different usually, generally there is no influencing each other of other.Therefore must device isolation can be come in integrated circuit fabrication, this just needs isolation technology.

Initial isolation technology adopts local oxidation (Local Oxidation Of Silicon, LOCOS) technique, and it has the simple feature of making, is widely adopted in the technique of 3 ~ 0.35 microns.But can Wu Zui be formed in isolated area due to this technique, reduce the effective length of active area, this just greatly reduces the integration density of device.Therefore along with device develops to deep-submicron, this technique can not meet the requirement in various performance technologies gradually, and this has just occurred that shallow trench isolation is from (Shallow Trench Isolation, STI) technology.

Shallow trench isolation technology take silicon nitride as protective layer; groove is carved with being etched on silicon single crystal substrate by photoetching; insert plasma enhanced CVD (PECVD) high density silica (HDP) again as dielectric material, to realize the electric isolation in integrated circuit between device.

Existing shallow trench isolation from preparation method be that, at high-temperature oxydation boiler tube internal oxidition Silicon Wafer, growth one deck is about the oxygen pad layer (Pad Oxide Layer) of 150 ~ 250A thickness.Oxygen pad layer is generally formed by silicon dioxide.Then, on described oxygen pad layer, deposit thickness is about the silicon nitride layer (NitrideLayer) of 1500 ~ 2000A.Afterwards, perform photomask and etching step, form about 0.4 ~ 0.5 μm of dark groove.Then, the thermal oxide lining (ThermalOxide Liner) of 150 ~ 300A is about at the upper growth thickness of the sidewall (Sidewall) of groove.Then, CVD oxide is formed with chemical vapor deposition (CVD).Then, with CVD oxide described in chemical mechanical polishing method (CMP) polishing.

Refer to Fig. 7 (a) and Fig. 7 (b), Fig. 7 (a) be depicted as the shallow trench isolation that adopts existing shallow trench isolation to obtain from preparation technology from the CDSEM figure of sidewall, Fig. 7 (b) be depicted as described shallow trench isolation from sidewall corresponding to roughness test result figure.As shown in Fig. 7 (b), adopt the roughness of the shallow trench isolated side wall prepared by existing technique to be greater than 16nm, optical loss is up to 17db/cm.Apparently, excessive roughness and optical loss will cause component failure.

For prior art Problems existing, this case designer is by means of being engaged in the industry experience for many years, and active research improves, so there has been the present invention to improve the method for roughness of side wall of shallow trench isolation.

Summary of the invention

The present invention be directed in prior art, roughness and the optical loss of existing shallow trench isolated side wall are excessive, cause the defects such as component failure, provide a kind of method improving roughness of side wall of shallow trench isolation.

In order to solve the problem, the invention provides a kind of method improving roughness of side wall of shallow trench isolation, described method, comprising: provide Semiconductor substrate, the preparation of hard mask, the deposit of bottom antireflective coating, and shallow trench etching.Wherein, described bottom antireflective coating deposit is formed on described hard mask, and the etching gas of described bottom antireflective coating and flow are: helium oxygen flow is 4 ~ 8sccm, and the flow rate ratio of carbon tetrafluoride and helium is 1.6 ~ 2.0.

Optionally, the thickness of described bottom antireflective coating is 500 ~ 700A.

Optionally, described hard mask is silicon nitride layer.

Optionally, oxygen pad layer is formed between described hard mask and described Semiconductor substrate.

In sum, in sum, the present invention by adopting thin bottom antireflective coating, and controls composition and the flow of the etching gas of bottom antireflective coating, to improve the roughness of shallow trench isolated side wall, reduces optical loss simultaneously.

Accompanying drawing explanation

Fig. 1 is the flow chart that the present invention improves the method for roughness of side wall of shallow trench isolation;

Fig. 2 is hard mask, the bottom antireflective coating prepared by the method that adopt the present invention to improve roughness of side wall of shallow trench isolation, and the structural representation of photoresist layer;

Fig. 3 is the structural representation that the method etching adopting the present invention to improve roughness of side wall of shallow trench isolation forms hard mask open;

Fig. 4 is the graph of a relation that the present invention improves for the etching gas composition and flow and roughness of side wall of shallow trench isolation that etch bottom antireflective coating in the method for roughness of side wall of shallow trench isolation;

Fig. 5 be adopt the present invention improve the method for roughness of side wall of shallow trench isolation etch the shallow ditch groove structure schematic diagram of formation;

Fig. 6 (a) be the shallow trench isolation prepared by method that adopts the present invention to improve roughness of side wall of shallow trench isolation from the CDSEM figure of sidewall, Fig. 6 (b) for described shallow trench isolation from sidewall corresponding to roughness test result figure;

Fig. 7 (a) be the shallow trench isolation that adopts existing shallow trench isolation to obtain from preparation technology from the CDSEM figure of sidewall, Fig. 7 (b) be depicted as described shallow trench isolation from sidewall corresponding to roughness test result figure.

Embodiment

By describe in detail the invention technology contents, structural feature, reached object and effect, coordinate accompanying drawing to be described in detail below in conjunction with embodiment.

Refer to Fig. 1, Figure 1 shows that the flow chart of the method improving roughness of side wall of shallow trench isolation.The described method improving roughness of side wall of shallow trench isolation comprises:

Perform step S1: as shown in Figure 2, provide Semiconductor substrate 10.Described Semiconductor substrate 10 is silicon-based substrate, and it can be monocrystalline silicon or polysilicon composition.

Perform step S2: please continue to refer to Fig. 2, deposit forms hard mask 11 in described Semiconductor substrate 10.Described hard mask 11 is silicon nitride layer.The preparation of described hard mask 11 can adopt low-pressure chemical vapor phase deposition method.

Simultaneously, oxygen pad layer (not shown) can be formed by thermal oxidation method between described hard mask 11 and described Semiconductor substrate 10, or by low-pressure chemical vapor phase deposition mode with deposit tetraethoxysilane (TEOS) in Semiconductor substrate 10, to reduce the surface stress in successive process.Described oxygen pad layer is silicon dioxide layer.

Perform step S3: refer to Fig. 2, at the outgrowth bottom antireflective coating 12 differing from Semiconductor substrate 10 of described hard mask 11.Wherein, the thickness of described bottom antireflective coating 12 depends on the optical wavelength used in micro-photographing process.In the present embodiment, the thickness preferably 500 ~ 700A of described bottom antireflective coating 12.

Perform step S4: refer to Fig. 2, on described bottom antireflective coating 12, coating forms photoresist layer 13, and carries out micro-shadow patterning to form photoresistance opening 131.The upper surface of exposed portion bottom antireflective coating 12 bottom described photoresistance opening 131.

Perform step S5: please continue to refer to Fig. 2, and Fig. 3 and Fig. 4 is consulted in combination, described bottom antireflective coating 12 and described hard mask 11 is etched according to described patterning photoresistance opening 131, and utilize reactive ion etching processing procedure with the upper surface of exposed portion Semiconductor substrate 10, and then form hard mask open 14.

Wherein, with patterning photoresistance opening 131 for mask, pattern bottom antireflecting coating 12 can be plasma dry etching method.The composition of the etching gas of pattern bottom antireflecting coating 12 and flow thereof directly affects the roughness quality of shallow trench isolated side wall.As shown in Figure 4, in the present embodiment, the etching gas composition of bottom antireflective coating 12 and flow are preferably: helium oxygen flow is 4 ~ 8sccm, and the flow rate ratio of carbon tetrafluoride and helium is 1.6 ~ 2.0.

Perform step S6: as shown in Figure 5, with hard mask open 14 for mask, etch described Semiconductor substrate 10, to form shallow trench 15.

Refer to Fig. 6 (a), Fig. 6 (b), Fig. 6 (a) be depicted as the shallow trench isolation prepared by method that adopts the present invention to improve roughness of side wall of shallow trench isolation from the CDSEM figure of sidewall, Fig. 6 (b) for described shallow trench isolation from sidewall corresponding to roughness test result figure.As shown in Fig. 6 (b), the roughness of described shallow trench isolated side wall is less than 3nm, and optical loss is less than 4nm/cm, and the roughness of the shallow trench isolated side wall prepared by more existing technique and optical loss have had significant improvement.

In sum, the present invention by adopting thin bottom antireflective coating 12, and controls composition and the flow of the etching gas of bottom antireflective coating, to improve the roughness of shallow trench isolated side wall, reduces optical loss simultaneously.

Those skilled in the art all should be appreciated that, without departing from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thus, if when any amendment or modification fall in the protection range of appended claims and equivalent, think that these amendment and modification are contained in the present invention.

Claims

1. one kind is improved the method for roughness of side wall of shallow trench isolation, comprise and Semiconductor substrate is provided, the preparation of hard mask, the deposit of bottom antireflective coating, and shallow trench etching, described bottom antireflective coating deposit is formed on described hard mask, it is characterized in that, and the etching gas of described bottom antireflective coating and flow are: helium oxygen flow is 4 ~ 8sccm, the flow rate ratio of carbon tetrafluoride and helium is 1.6 ~ 2.0.

2. improve the method for roughness of side wall of shallow trench isolation as claimed in claim 1, it is characterized in that, the thickness of described bottom antireflective coating is

3. improve the method for roughness of side wall of shallow trench isolation as claimed in claim 1, it is characterized in that, described hard mask is silicon nitride layer.

4. improve the method for roughness of side wall of shallow trench isolation as claimed in claim 1, it is characterized in that, between described hard mask and described Semiconductor substrate, form oxygen pad layer.