CN110783461B - Transistor and method for manufacturing the same - Google Patents
Transistor and method for manufacturing the same Download PDFInfo
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- CN110783461B CN110783461B CN201910879619.7A CN201910879619A CN110783461B CN 110783461 B CN110783461 B CN 110783461B CN 201910879619 A CN201910879619 A CN 201910879619A CN 110783461 B CN110783461 B CN 110783461B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/80—Constructional details
- H10K10/82—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/80—Constructional details
- H10K10/82—Electrodes
- H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/60—Forming conductive regions or layers, e.g. electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
Abstract
The application discloses a transistor and a manufacturing method thereof, mainly comprising the following steps: forming carbon nanotubes on a substrate; forming a gate stack structure on the carbon nanotube; forming a side wall covering the gate stack structure; forming a sacrificial layer at least covering the side wall; forming a metal layer covering the carbon nano tube and the sacrificial layer, wherein part of the metal layer positioned in the source-drain region is used as an electric contact with the carbon nano tube; removing a portion of the metal layer to expose the sacrificial layer; and removing the sacrificial layer to expose the side wall. In the manufacturing method, when the metal layer is formed, the metal layer is directly covered on the sacrificial layer and the carbon nano tube, the side wall is prevented from being in direct contact with the metal layer through isolation of the sacrificial layer, the metal layer covered on the sacrificial layer is separated from the device through removal of the sacrificial layer, and a source-drain contact structure is formed, so that source-drain metal can effectively generate good wettability with the carbon nano tube, and ohmic contact with low resistance is realized.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuit device fabrication, and more particularly, to a transistor and a method of fabricating the same.
Background
As semiconductor technology continues to shrink down to technology nodes below 3nm, silicon-based integrated circuits are most likely to reach the limits of silicon materials and physical quantum mechanics. The continued development of microelectronics is pressing to find new and more potential and advantageous materials to replace silicon materials, breaking through the limits of moore's law. Carbon Nanotubes (CNTs) have excellent electrical, thermal, mechanical and chemical stability and unique one-dimensional nanostructures, making them ideal functional materials for applications in micro-nano electronic devices. Carbon Nanotubes (CNTs) have advantages of high speed, low power consumption, etc. compared to conventional silicon-based electronic devices, and are considered as one of the channel materials for constructing field effect transistors optimally in the future.
One of the greatest difficulties in fabricating carbon nanotube devices, compared to the mainstream silicon-based semiconductor technology, is how to efficiently form the source-drain electrodes. For a silicon-based device, the source-drain metal can form silicide material with a silicon substrate through annealing, and the source-drain metal deposited on the surface of the side wall is removed through a subsequent wet cleaning process. For the carbon nanotube device, the source-drain metal is difficult to form good alloy contact with the carbon nanotube, thereby showing similar characteristics as the metal on the side wall. Therefore, a great difficulty is how to remove the metal material deposited on the side wall surface of the side wall with high selectivity, so as to reduce the influence of parasitic capacitance to the greatest extent, which is one of the biggest challenges in the manufacturing process of the carbon nanotube device.
In the prior art, a gate stack structure is formed on a carbon nanotube, then a sidewall structure is formed by deposition and etching, and then a corresponding source-drain metal material is deposited on the whole wafer surface. Then, the metal on the surface of the side wall is removed by combining lithography and proper etching, but the problem of alignment deviation is caused by insufficient precision of the lithography process, so that a controllable source-drain contact region cannot be accurately obtained, namely, the method is a non-self-aligned forming technology, and uncontrollable hidden danger is brought to a subsequent series of processes. In particular, as device dimensions shrink, the alignment bias is not negligible more and more than the size of the gate line dimensions. Therefore, the manufacturing process of the source-drain contact of the carbon nanotube device must be further improved, the difficulty of removing the metal layer on the side wall is reduced, and thus an accurate self-aligned source-drain contact electrode is formed, and good ohmic contact is realized.
Disclosure of Invention
In view of this, the application provides a transistor and a manufacturing method thereof, wherein the sacrificial layer is used for protecting the side wall when the metal layer is formed, so that the surface of the side wall is not covered by the metal layer, and the side wall is prevented from being in direct contact with the metal layer.
According to an aspect of the present application, there is provided a method of manufacturing a transistor, including: forming carbon nanotubes on a substrate; forming a gate stack structure on the carbon nanotubes; forming a side wall covering the side wall of the gate stack structure; forming a sacrificial layer at least covering the side wall; forming a metal layer covering the carbon nanotubes and the sacrificial layer, wherein part of the metal layer positioned in the source-drain region is used as an electric contact with the carbon nanotubes; removing a part of the metal layer by adopting a wet etching process or a dry etching process to expose the sacrificial layer; and removing the sacrificial layer by a wet or dry etching process to expose the side wall, wherein the sacrificial layer has a predetermined selection ratio compared to the carbon nanotube, the gate stack structure, the side wall and the electrical contact when the sacrificial layer is removed by the wet or dry etching process.
Preferably, the step of removing the sacrificial layer includes: and dissolving the sacrificial layer by adopting a solution, wherein a metal layer covering the sacrificial layer enters the solution.
Preferably, the solution dissolves the sacrificial layer at a rate greater than the rate at which the metal layer is dissolved.
Preferably, the rate of dissolution of the sacrificial layer by the solution is greater than the rate of dissolution of the sidewall and the gate stack structure.
Preferably, the step of removing the metal layer includes etching or corroding the metal layer and stopping on the surface of the sacrificial layer.
Preferably, the thickness of the metal layer covering the carbon nanotubes is greater than the thickness of the metal layer at least partially covering the sacrificial layer, and the reaction parameters are controlled such that etching or corrosion is stopped when the sacrificial layer is exposed.
Preferably, a mask layer is formed on the gate stack structure, the side wall covers the side wall of the mask layer, and the sacrificial layer also covers the surface of the mask layer.
Preferably, the sacrificial layer further covers the carbon nanotubes, and before forming the metal layer, the manufacturing method further includes removing a portion of the sacrificial layer to form at least two pattern regions, wherein the at least two pattern regions are respectively located at two sides of the gate stack structure, and at least a portion of the carbon nanotubes are exposed through the pattern regions.
Preferably, the thickness of the sacrificial layer is greater than the thickness of the metal layer at least at the surface of the carbon nanotubes.
Preferably, when the material of the side wall comprises silicon oxide, the material of the sacrificial layer comprises one or a combination of silicon nitride, amorphous silicon, organic material and spin-on medium with high fluidity; when the material of the side wall comprises silicon nitride, the material of the sacrificial layer comprises one or a combination of silicon oxide, amorphous silicon, organic materials and high-fluidity spin-on media.
Preferably, the predetermined selection ratio is not less than 3:1.
According to another aspect of the present application, there is provided a transistor formed using the manufacturing method as described above.
According to the transistor and the manufacturing method thereof, the sacrificial layer covering the side wall is formed, and when the metal layer is formed, the metal layer covers the sacrificial layer and the carbon nano tube, and the side wall is prevented from being in direct contact with the metal layer through isolation of the sacrificial layer. When the sacrificial layer is removed by adopting a wet etching process or a dry etching process, the sacrificial layer has a predetermined selection ratio compared with other functional layers, and the other functional layers are prevented from being damaged when the sacrificial layer is removed. After the sacrificial layer is removed, the metal layer covered on the sacrificial layer is separated from the device, and the rest metal layer is positioned on the carbon nano tube to form a source-drain contact structure, so that the source-drain metal can effectively generate good wettability with the carbon nano tube, and low-resistance ohmic contact is realized. Compared with the prior art, the transistor manufacturing method provided by the application can avoid the formation of the source-drain contact structure by using a non-self-alignment technology, simultaneously conveniently and efficiently remove the redundant metal layer, form an accurate self-alignment source-drain contact electrode and improve the yield of devices.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will make it apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.
Fig. 1 shows a schematic structure of a transistor according to an embodiment of the present application.
Fig. 2a to 2f show cross-sectional views of a method of manufacturing a transistor according to an embodiment of the present application at various stages.
Detailed Description
The application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. For the sake of simplicity, the semiconductor device obtained after several steps may be described in one drawing.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying … … and adjoining" will be used herein.
Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.
The application may be embodied in various forms, some examples of which are described below.
Fig. 1 shows a schematic structure of a carbon nanotube transistor according to an embodiment of the present application.
As shown in fig. 1, a transistor according to an embodiment of the present application includes: a substrate 101, carbon nanotubes 110, a gate stack structure 120, electrical contacts including a source contact structure 130 and a drain contact structure 140, a mask layer 102, and sidewalls 103.
The carbon nanotubes 110 are located on the substrate 101. The gate stack structure 120 covers a portion of the carbon nanotubes 110. Mask layer 102 is located on the surface of gate stack structure 120. The side walls 103 are located on two sides of the gate stack 120 and the mask layer 102. The source contact structure 130 and the drain contact structure 140 cover at least part of the carbon nanotubes 110 and are respectively located at two sides of the gate stack structure 120 and outside the side wall 103, and are spaced apart from the gate stack structure 120 by a certain distance.
In some embodiments, the substrate 101 includes an insulating layer on a support substrate. The support substrate mainly plays a supporting role, and the material can be hard insulating materials such as silicon, sapphire substrate, quartz, glass, alumina and the like, and any substrate capable of bearing the carbon nanotube material, but has a very flat surface, and the uniformity also meets the requirements. In this embodiment, a silicon material is used as a substrate, and is not particularly limited. The insulating layer is made of silicon oxide, silicon nitride, PET, PEN, polyimide and other high-temperature-resistant flexible insulating materials. Different insulating layer materials may be selected according to actual product requirements, and in this embodiment, a silicon oxide material is used as the insulating layer, and is not particularly limited. In another embodiment, the substrate 101 may be grooved and then the carbon nanotubes 110 may be deposited in the grooves as a semiconductor layer, rather than just depositing the semiconductor layer on a flat surface.
The semiconductor layer carbon nanotubes 110 in this embodiment include a carbon nanotube array, a carbon nanotube self-assembled film, a carbon nanotube network array, or a carbon nanotube composite film formed by combining the above-mentioned methods. In addition, the semiconductor layer may be strained silicon or germanium, quantum well, III-V material, two-dimensional material such as graphene, molybdenum disulfide, black phosphorus, etc.
In this embodiment, the gate stack structure 120 includes a gate dielectric layer and a gate conductor stacked on the carbon nanotube 110, wherein the material of the gate dielectric layer may be a conventional gate oxide layer such as silicon oxide, silicon oxynitride, or a high-k (high-k) dielectric material such as hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, aluminum oxide, lanthanum oxide, or lanthanum aluminum oxide, and the thickness is in the range of 1-10 nm. As required, the gate conductor has two cases: when the front grid process is adopted, the front grid is a composite structure composed of single or multiple layers of metals; when the back gate process is adopted, a dummy gate electrode is required to be adopted, and the material of the dummy gate electrode is amorphous silicon, polycrystalline silicon and the like. And then after a series of processing steps, removing the material by adopting a dry etching technology or a wet etching technology, and filling the material such as a metal gate and the like to form a final gate metal conductor.
In this embodiment, when the carbon nanotube transistor is an N-type MOSFET, the materials of the source contact structure 130 and the drain contact structure 140 include metals such as scandium, yttrium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or their alloys or their composites; when the carbon nanotube transistor is a P-type MOSFET, the materials of the source contact structure 130 and the drain contact structure 140 include palladium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, etc. or alloy materials or composite materials thereof.
However, the embodiments of the present application are not limited thereto, and those skilled in the art may perform other arrangements on the materials of the gate stack structure 120, the source contact structure 130, and the drain contact structure 140 as required.
Fig. 2a to 2f show cross-sectional views of a method of manufacturing a transistor according to an embodiment of the present application at various stages.
The method of the embodiment of the present application starts with the substrate 101, and the carbon nanotube 110, the gate stack structure 120, the mask layer 102 and the sidewall 103 are sequentially formed on the substrate 101, as shown in fig. 2a, where the materials and structures of the substrate 101, the carbon nanotube 110, the gate stack structure 120, the mask layer 102 and the sidewall 103 may be described with reference to fig. 1, and are not repeated herein.
In this embodiment, the sidewall 103 may be made of a silicon oxide/silicon nitride multi-layer material or a single material of silicon oxide or silicon nitride, which is required according to different specific process requirements. Then, a proper dry etching process is adopted to form the side wall morphology and width meeting the requirements. Since the morphology of the sidewall 1031 depends on the selection of a specific etching process and the integration process requirements of the gate structure, generally, the morphology of the sidewall 1031 will not always completely take on a steep shape.
Further, a sacrificial layer 104 is formed to cover the carbon nanotube 110, the mask layer 102 and the sidewall 103, as shown in fig. 2 b.
In this step, the thickness of the sacrificial layer 104 is greater than the thickness of the metal film deposited later, and may be made of various materials, depending on the specific sidewall material, that is, the same film as the sidewall material cannot be used, but a high etching selectivity must be present between the two materials to remove the sacrificial layer during the subsequent process without affecting the sidewall material. For example, when silicon oxide is used for the side wall, silicon nitride, amorphous silicon, organic materials such as BARC or spin-on media with high fluidity such as SOG (Spin on glass), SOC (Spin on carbon), etc. can be used for the sacrificial layer; when the side wall is made of silicon nitride, the sacrificial layer can be made of silicon oxide, amorphous silicon, organic materials such as BARC or spin-on media with high fluidity such as SOG (Spin on glass), SOC (Spin on carbon) and the like. They may be formed using chemical vapor deposition (Chemical Vapor Deposition, CVD) processes, atomic layer deposition techniques (Atomic Layer Deposition, ALD), spin-on processes, or the like. However, embodiments of the present application are not limited thereto, and those skilled in the art may make other arrangements of the material of sacrificial layer 104 as desired.
Since the topography of the sidewall 1031 does not fully take on a steep shape, the topography of the sacrificial layer 104 subsequently deposited thereon may also be affected such that the topography of the sacrificial layer sidewall 1041 does not fully take on a steep shape. Further, a portion of sacrificial layer 104 is removed at the source drain regions to form a plurality of patterns, as shown in FIG. 2 c.
In this step, a desired lithographic pattern is formed on sacrificial layer 104, for example, using a suitable lithographic process, defining a pattern and locations of the plurality of openings, and then removing portions of sacrificial layer 104 using a dry etching process to form a plurality of openings 105, by tuning the process parameters of the etching, including: one or more of reaction pressure, reaction time, reaction temperature, radio frequency power, gas flow, etc., control etching to stop when it reaches the carbon nanotubes 110.
In this embodiment, the openings 105 are located in the horizontal region of the device and are located on two sides of the gate stack structure 120, and expose a portion of the carbon nanotubes 110, thereby defining a metal source-drain contact region.
Further, a metal layer 106 is formed to cover the sacrificial layer 104 and the carbon nanotubes 110, as shown in fig. 2 d.
In this step, the metal layer 106 is formed, for example, using an atomic layer deposition (Atomic layer deposition, ALD) process, a physical vapor deposition (Physical Vapor Deposition, PVD) process. A portion of the metal layer is located in the opening in contact with carbon nanotubes 110 and the remaining portion is located on sacrificial layer 104, separated from the sidewall by sacrificial layer 104.
In this embodiment, when the fabricated carbon nanotube transistor is an N-type MOSFET, the deposited metal layer 104 is made of scandium, yttrium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or an alloy thereof, and when the fabricated carbon nanotube transistor is a P-type MOSFET, the deposited metal layer 104 is made of palladium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or an alloy thereof.
However, embodiments of the present application are not limited thereto, and those skilled in the art may make other arrangements of the material of the metal layer 106 as desired.
In this embodiment, since the morphology of the sacrificial layer sidewall 1041 does not completely take on a steep shape, the morphology of the metal layer 106 is affected, for example, when PVD sputtering is used, the thickness of the metal layer formed near the middle (near the steep portion) of the sacrificial layer sidewall 1041 is smaller, and the thickness of the metal layer formed on the horizontal surface (e.g., the carbon nanotube 110) of the device is larger. In this embodiment, the thickness of the metal layer on the horizontal surface of the device is less than the thickness of the sacrificial layer.
Further, a portion of metal layer 106 is removed to expose at least a portion of sacrificial layer 104, as shown in FIG. 2 e.
In this step, a dry etching process or a wet etching process is used to remove a portion of the metal layer 106, and the process parameters of the etching are adjusted, including: one or more of reaction pressure, reaction time, reaction temperature, reaction rate, radio frequency power, gas or liquid flow, etc., control etching to stop when a portion of sacrificial layer 104 is exposed. Because the thickness of the metal layer formed near the middle of the sidewall 1041 is smaller, the metal layer at the middle is removed first, so as to expose the surface of the sacrificial layer 104 near the middle of the sidewall 1041, at this time, the etching or corrosion may be stopped, or the etching or corrosion process may be stopped when the metal in the source/drain opening region is removed to a certain thickness according to the product requirement. Meanwhile, although a portion of the metal layer formed on the horizontal surface of the device is removed, the thickness of the metal layer is the same as that of the metal layer formed at the middle position of the side wall 1041 of the near-sacrificial layer. Since the thickness of the metal layer formed on the horizontal surface of the device is large, the metal layer on the horizontal surface remains when etching or corrosion is stopped.
It should be noted that in this step, the metal layer 106 on the surface of the carbon nanotube 110 is prevented from being completely removed by over etching or over corrosion by controlling the conditions of the reaction time, the reaction temperature, and the like.
Further, sacrificial layer 104 is removed to expose sidewall 103, as shown in FIG. 2 f.
In this step, for example, a specific solution is used to dissolve the sacrificial layer, so that the rate of dissolving the sacrificial layer in the solution is much greater than (e.g., 3:1) the rate of dissolving the metal layer, and when the sacrificial layer is completely dissolved in the solution, the metal layer covering the sacrificial layer falls into the solution, and the metal layer on the carbon nanotube 110 is retained, so as to serve as the source contact structure 130 and the drain contact structure 140, respectively. In some embodiments, dry etching techniques may be used to remove the sacrificial layer, but the rate of removal of the sacrificial layer is required to be much greater (e.g., 3:1) than the rate of removal of the metal layer.
It should be noted that the wet etching process and the dry etching process both require a high selectivity (e.g., 3:1 or more) for the contact metal, the sidewall material, the gate metal, etc. of the source/drain electrode, otherwise the related functional layers will be greatly damaged during the process of removing the sacrificial layer 104.
According to the transistor and the manufacturing method thereof, the sacrificial layer covering the side wall is formed, when the metal layer is formed, the metal layer is covered on the sacrificial layer and the carbon nano tube, through isolation of the sacrificial layer, the side wall is prevented from being in direct contact with the metal layer, when the solution is adopted to dissolve the sacrificial layer, the metal layer covering the sacrificial layer can enter the solution, so that the metal layer covering the sacrificial layer is separated from a device, a source-drain contact structure is formed, and the difficulty of removing the metal layer on the side wall is reduced due to the fact that the metal layer is prevented from being directly deposited on the side wall, and therefore an accurate self-aligned source-drain contact electrode is formed, and good ohmic contact is achieved.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present application are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present application. The scope of the application is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the application.
Claims (8)
1. A method of manufacturing a transistor, comprising:
forming carbon nanotubes on a substrate;
forming a gate stack structure on the carbon nanotubes;
forming a side wall covering the side wall of the gate stack structure;
forming a sacrificial layer at least covering the side wall;
forming a metal layer covering the carbon nanotubes and the sacrificial layer, the metal layer partially located on the carbon nanotubes as an electrical contact with the carbon nanotubes;
wherein the thickness of the metal layer covering the carbon nanotubes is greater than the thickness of the metal layer at least partially covering the sacrificial layer; controlling reaction parameters by etching or corroding a metal layer covering the sacrificial layer, so that the etching or corroding is stopped when the sacrificial layer is exposed; and removing the sacrificial layer by adopting a wet etching process or a dry etching process to expose the side wall,
when the sacrificial layer is removed by adopting a wet etching process or a dry etching process, the sacrificial layer has a selectivity ratio of not less than 3:1 compared with the carbon nanotube, the gate stack structure, the side wall and the electric contact.
2. The method of manufacturing of claim 1, wherein removing the sacrificial layer comprises: and dissolving the sacrificial layer by adopting a solution, wherein a metal layer covering the sacrificial layer enters the solution.
3. The manufacturing method according to claim 2, wherein the solution dissolves the sacrificial layer at a rate greater than a rate at which the metal layer is dissolved.
4. The manufacturing method according to claim 2, wherein the solution dissolves the sacrificial layer at a rate greater than a rate at which the sidewall and the gate stack structure are dissolved.
5. The manufacturing method according to claim 1, wherein the sacrificial layer further covers the carbon nanotubes, and before forming the metal layer, the manufacturing method further comprises removing a portion of the sacrificial layer to form at least two pattern regions, wherein the at least two pattern regions are located on both sides of the gate stack structure, respectively, and at least a portion of the carbon nanotubes are exposed through the pattern regions.
6. The manufacturing method according to claim 5, wherein a thickness of the sacrificial layer is greater than a thickness of the metal layer at least at a surface of the carbon nanotube.
7. The manufacturing method according to any one of claims 1 to 6, wherein when the material of the side wall comprises silicon oxide, the material of the sacrificial layer comprises one or a combination of silicon nitride, amorphous silicon, an organic material, and a spin-on medium having high fluidity;
when the material of the side wall comprises silicon nitride, the material of the sacrificial layer comprises one or a combination of silicon oxide, amorphous silicon, organic materials and high-fluidity spin-on media.
8. A transistor formed using the manufacturing method of any of claims 1-7.
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