CN107978673A - A kind of semiconductor devices and preparation method, electronic device - Google Patents
A kind of semiconductor devices and preparation method, electronic device Download PDFInfo
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- CN107978673A CN107978673A CN201610935796.9A CN201610935796A CN107978673A CN 107978673 A CN107978673 A CN 107978673A CN 201610935796 A CN201610935796 A CN 201610935796A CN 107978673 A CN107978673 A CN 107978673A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
- H10N70/8845—Carbon or carbides
Abstract
The present invention provides a kind of semiconductor devices and preparation method, electronic device.The described method includes Semiconductor substrate is provided, include the sacrifice layer and separation layer stacked gradually formed with multi-layer laminate structure, every layer of laminated construction on the semiconductor substrate；The first epitaxial substrate layer, the first graphene layer, insulating layer, the second epitaxial substrate layer, the second graphene layer and bottom electrode layer are sequentially formed in the Semiconductor substrate and the multi-layer laminate structure；The multi-layer laminate structure is patterned, to form opening, the multi-layer laminate structure is divided into spaced two parts and exposes the Semiconductor substrate；The sacrifice layer exposed in the opening is removed, to form groove between the separation layer；Layer of top electrode material is deposited, to fill the groove and form top electrodes.
Description
Technical field
The present invention relates to technical field of semiconductors, is filled in particular to a kind of semiconductor devices and preparation method, electronics
Put.
Background technology
With the continuous extension of mole (Moore) law and depth so that the device size of si-substrate integrated circuit is from physics
The limit is more and more nearer, and international semiconductor technique circle proposes to surmount silicon (Beyond Silicon) technology one after another, wherein with larger
The graphene of potentiality to be exploited comes into being.
Graphene (Graphene) be in a kind of monolayer honeycomb crystal lattice carbon atom composition two dimensional crystal, individual layer stone
The thickness of black alkene is about 0.35 nanometer, and less than ten layers of graphite is looked at as graphene.Graphene not only has very outstanding
Mechanical property and heat endurance, also with superconduction electrical properties.The theoretical carrier mobility of graphene can be up to 2 ×
105cm2/Vs, is 10 times or so of current silicon materials carrier mobility, and physical with room temperature quantum hall effect etc.
Matter, therefore, graphene are considered being possible to leading semiconductor material of the substitution silicon as a new generation.
Wherein, it is high using graphene in resistive formula memory (Resistive Random Access Memory) at present
Plane external resistance (out-of-plane resistance) reduce operation electric current, but the plane external resistance (out-
Of-plane resistance) higher formation voltage, such as 6V are needed, the formation voltage is compared to routine operation electricity
Press much higher, therefore how to keep plane external resistance (out-of-plane resistance) while eliminate the high formation
Voltage becomes problem to be solved.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of preparation method of semiconductor devices, institute
The method of stating includes：
Semiconductor substrate is provided, on the semiconductor substrate formed with multi-layer laminate structure, every layer of laminated construction
Including the sacrifice layer and separation layer stacked gradually；
The first epitaxial substrate layer, the first graphene are sequentially formed in the Semiconductor substrate and the multi-layer laminate structure
Layer, insulating layer, the second epitaxial substrate layer, the second graphene layer and bottom electrode layer；
Pattern the bottom electrode layer, second graphene layer, second epitaxial substrate layer, the insulating layer,
First graphene layer, first epitaxial substrate layer and the multi-layer laminate structure, to form opening, by the multilayer
Laminated construction is divided into spaced two parts and exposes the Semiconductor substrate；
The sacrifice layer exposed in the opening is removed, to form groove between the separation layer；
Layer of top electrode material is deposited, to fill the groove and form top electrodes.
Alternatively, first epitaxial substrate layer includes SiC layer；
Second epitaxial substrate layer includes SiC layer.
Alternatively, the insulating layer includes metal oxide layer.
Alternatively, the etching top electrodes are still further comprised in the step of forming the top electrodes to open described
The part of bridging in mouthful, to be formed by the mutually isolated top electrodes of the opening.
Alternatively, the method may further include shape in the bottom electrode layer after the bottom electrode is formed
The step of into sacrificial material layer to the top of the bottom electrode layer.
Alternatively, the method still further comprises and removes the sacrificial material layer after the top electrodes are formed
Step.
Present invention also offers a kind of semiconductor devices, the semiconductor devices includes some storage units, the storage
Unit includes：
Semiconductor substrate；
Multi-layer laminate structure, including the top electrodes and separation layer stacked gradually, the multi-layer laminate structure include opposite
The first side wall and second sidewall of setting；
Storage organization, be included in the Semiconductor substrate, the multi-layer laminate structure top and the first side wall on
The first graphene layer, insulating layer and the second graphene layer sequentially formed；
Bottom electrode, above second graphene layer.
Alternatively, the semiconductor devices includes two storage units, the top of storage unit described in two of which
Electrode is opposite and spaced setting.
Alternatively, the insulating layer includes metal oxide layer.
Alternatively, formed with the first epitaxial substrate layer between first graphene layer and the insulating layer；
Formed with the second epitaxial substrate layer between second graphene layer and the insulating layer.
Alternatively, first epitaxial substrate layer includes SiC layer；
Second epitaxial substrate layer includes SiC layer.
Present invention also offers a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
The application is in order to solve the problems, such as that current semiconductor devices exists, there is provided a kind of semiconductor devices and its preparation side
Method, epitaxial substrate is initially formed in the preparation method, and graphene is grown in the epitaxial substrate, and formed graphene-
The RRAM of the 3D structures of insulating layer-graphene (Graphene-Insulator-Graphene, G-I-G), avoids high temperature deposition
The adverse effect brought, further increases the yield and performance of the RRAM.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows the preparation technology flow chart of semiconductor devices of the present invention；
Fig. 2 shows the knot that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
The sectional view of structure；
Fig. 3 shows the knot that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
The sectional view of structure；
Fig. 4 shows the knot that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
The sectional view of structure；
Fig. 5 shows the knot that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
The sectional view of structure；
Fig. 6 shows the knot that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
The sectional view of structure；
Fig. 7 shows the knot that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
The sectional view of structure；
Fig. 8 shows the knot that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
The sectional view of structure；
Fig. 9 shows the knot that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
The sectional view of structure；
Figure 10 shows what a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention was formed
The sectional view of structure；
Figure 11 shows what a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention was formed
The sectional view of structure；
Figure 12 shows what a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention was formed
The sectional view of structure；
Figure 13 shows what a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention was formed
The sectional view of structure；
Figure 14 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, component, area, floor and/or part, these elements, component, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, component, area, floor or part and another
Element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, component, area,
Floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to further include using and
The different orientation of device in operation.For example, if the device upset in attached drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this hair
It is bright to have other embodiment.
A kind of preparation method of semiconductor devices is provided in order to solve the problems, such as presently, there are, the described method includes：
Semiconductor substrate is provided, on the semiconductor substrate formed with multi-layer laminate structure, every layer of laminated construction
Including the sacrifice layer and separation layer stacked gradually；
The first epitaxial substrate layer, the first graphene are sequentially formed in the Semiconductor substrate and the multi-layer laminate structure
Layer, insulating layer, the second epitaxial substrate layer, the second graphene layer and bottom electrode layer；
Pattern the bottom electrode layer, second graphene layer, second epitaxial substrate layer, the insulating layer,
First graphene layer, first epitaxial substrate layer and the multi-layer laminate structure, to form opening, by the multilayer
Laminated construction is divided into spaced two parts and exposes the Semiconductor substrate；
The sacrifice layer exposed in the opening is removed, to form groove between the separation layer；
Layer of top electrode material is deposited, to fill the groove and form top electrodes.
The graphene is the nano material that known world is most thin, most hard, it is almost fully transparent, is only absorbed
2.3% light；The high 5300W/mK of thermal conductivity factor, higher than carbon nanotubes and diamond, its electron mobility exceedes under room temperature
15000cm2/ Vs, but it is higher than carbon nanotubes or silicon crystal, and about 1 Ω m of resistivity, it is lower than copper or silver, for electricity in the world
The material of resistance rate minimum.Because its resistivity is extremely low, the speed of electron transfer is exceedingly fast.
Graphene is the carbon of two dimensional crystal structure, its outstanding electron mobility and other unique nanoelectronics and photon
Function has good prospect.
Wherein, first epitaxial substrate layer includes SiC layer；
Second epitaxial substrate layer includes SiC layer.
The graphene layer can be very good the extension in the SiC layer in the present invention, and need not be too high voltage.
The present invention provides a kind of semiconductor devices, the semiconductor devices includes some storage units, and the storage is single
Member includes：
Semiconductor substrate；
Multi-layer laminate structure, including the top electrodes and separation layer stacked gradually, the multi-layer laminate structure include opposite
The first side wall and second sidewall of setting；
Storage organization, be included in the Semiconductor substrate, the multi-layer laminate structure top and the first side wall on
The first graphene layer, insulating layer and the second graphene layer sequentially formed；
Bottom electrode, above second graphene layer.
Alternatively, the semiconductor devices includes two storage units, wherein storage unit described in the both sides
Top electrodes are opposite and spaced setting.
The application is in order to solve the problems, such as that current semiconductor devices exists, there is provided a kind of semiconductor devices and its preparation side
Method, epitaxial substrate is initially formed in the preparation method, and graphene is grown in the epitaxial substrate, and formed graphene-
The RRAM of the 3D structures of insulating layer-graphene (Graphene-In sulator-Graphene, G-I-G), avoids high temperature and sinks
The adverse effect that product is brought, further increases the yield and performance of the RRAM.
Embodiment one
Below with reference to Fig. 1-Figure 13, wherein, Fig. 1 shows the preparation technology flow chart of semiconductor devices of the present invention；
Fig. 2 shows the section view for the structure that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
Figure；Fig. 3 shows the structure that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
Sectional view；Fig. 4 shows the knot that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
The sectional view of structure；Fig. 5 shows that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
Structure sectional view；Fig. 6 shows a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention
The sectional view of the structure of formation；Fig. 7 shows a kind of correlation of the manufacture method of semiconductor devices in one embodiment of the invention
The sectional view for the structure that step is formed；Fig. 8 shows a kind of manufacture method of semiconductor devices in one embodiment of the invention
The sectional view for the structure that correlation step is formed；Fig. 9 shows a kind of manufacturer of semiconductor devices in one embodiment of the invention
The sectional view for the structure that the correlation step of method is formed；Figure 10 shows a kind of system of semiconductor devices in one embodiment of the invention
Make the sectional view of the structure of the correlation step formation of method；Figure 11 shows a kind of semiconductor devices in one embodiment of the invention
Manufacture method correlation step formed structure sectional view；Figure 12 shows a kind of semiconductor in one embodiment of the invention
The sectional view for the structure that the correlation step of the manufacture method of device is formed；Figure 13 shows a kind of half in one embodiment of the invention
The sectional view for the structure that the correlation step of the manufacture method of conductor device is formed.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the key step bag of the preparation method
Include：
Step S1：Semiconductor substrate is provided, on the semiconductor substrate formed with multi-layer laminate structure, every layer described folded
Rotating fields include the sacrifice layer and separation layer stacked gradually；
Step S2：The first epitaxial substrate layer, are sequentially formed in the Semiconductor substrate and the multi-layer laminate structure
One graphene layer, insulating layer, the second epitaxial substrate layer, the second graphene layer and bottom electrode layer；
Step S3：Pattern the bottom electrode layer, second graphene layer, second epitaxial substrate layer, described
Insulating layer, first graphene layer, first epitaxial substrate layer and the multi-layer laminate structure, will to form opening
The multi-layer laminate structure is divided into spaced two parts and exposes the Semiconductor substrate；
Step S4：The sacrifice layer exposed in the opening is removed, to form groove between the separation layer；
Step S5：Layer of top electrode material is deposited, to fill the groove and form top electrodes.
In the following, the embodiment of the preparation method of the semiconductor devices of the present invention is described in detail.
First, step 1 is performed, there is provided Semiconductor substrate 201, on the semiconductor substrate formed with by sacrifice layer 202
The multi-layer laminate structure stacked gradually with separation layer 203.
Specifically, as shown in Fig. 2, the Semiconductor substrate (not shown) can be in the following material being previously mentioned
It is at least one：Silicon, silicon-on-insulator (SOI), be laminated silicon (SSOI) on insulator, be laminated SiGe (S- on insulator
SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Wherein, the sacrifice layer can select the material for having larger etching selectivity with the separation layer.
Such as the sacrifice layer selects SiN in this embodiment.
Wherein, such as inorganic insulation layer of silicon oxide layer, silicon nitride layer or silicon oxynitride layer can be used in the separation layer,
Insulating layer of layer comprising polyvinyl phenol, polyimides or siloxanes etc. etc. is formed.In addition, polyvinyl phenol, poly-
Acid imide or siloxanes can be formed effectively by droplet discharging method, the art of printing or spin-coating method.Siloxanes can quilt according to its structure
It is categorized into silica glass, alkyl siloxane polymer, alkyl silsesquioxane (alkylsilsesquioxane) polymerization
Thing, silsesquioxane hydride (silsesquioxane hydride) polymer, alkyl silsesquioxane hydride
(alkylsilsesquioxane hydride) polymer etc..
In addition, the separation layer 203 selects oxide, can be formed with by various deposition process commonly used in the art.
203 alternating deposit of the sacrifice layer 202 and separation layer in this step, the present embodiment form three layers of sacrifice layer
202 and three layers of separation layer 203.
Wherein, side is initially formed the sacrifice layer 202 on the semiconductor substrate.
After the stepped construction for stacking gradually sacrifice layer and separation layer composition on the semiconductor substrate, then pattern
The stepped construction, to form square multi-layer laminate structure.
Wherein, the multi-layer laminate structure is cube shaped frame, such as rectangular shape etc., as shown in Figure 3.
Step 2 is performed, the first epitaxial substrate layer is sequentially formed in the Semiconductor substrate and the multi-layer laminate structure
204th, the first graphene layer 205, insulating layer 206, the second epitaxial substrate layer 207, the second graphene layer 208 and bottom electrode layer
209。
Specifically, as shown in figure 4, in this application in order to avoid using high pressure deposition process, in the Semiconductor substrate
With the first epitaxial substrate layer 204 is initially formed on the multi-layer laminate structure, for epitaxial graphene layer.
Wherein, first epitaxial substrate layer includes SiC layer；
The graphene layer can be very good the extension in the SiC layer in the present invention, and need not be too high voltage.
The graphene is the nano material that known world is most thin, most hard, it is almost fully transparent, is only absorbed
2.3% light；The high 5300W/mK of thermal conductivity factor, higher than carbon nanotubes and diamond, its electron mobility exceedes under room temperature
15000cm2/ Vs, but it is higher than carbon nanotubes or silicon crystal, and about 1 Ω m of resistivity, it is lower than copper or silver, for electricity in the world
The material of resistance rate minimum.Because its resistivity is extremely low, the speed of electron transfer is exceedingly fast.
Graphene is the carbon of two dimensional crystal structure, its outstanding electron mobility and other unique nanoelectronics and photon
Function has good prospect.
Wherein, the growing method of the first graphene layer can use epitaxial growth method.
Exemplarily, the epitaxial growth method specifically includes following step：
Semiconductor substrate is successively put into acetone, ethanol and deionized water and is cleaned, each time 10min, from going
Substrate is taken out in ionized water, is dried up with high pure nitrogen (99.9999%)；It is anti-that Semiconductor substrate is put into chemical vapor deposition CVD
Answer in room, extract vacuum to 10-5Torr, reacts indoor residual gas to remove；High-purity Ar, temperature are passed through into reative cell
150 DEG C, 10min is kept, is then evacuated to 10-5Torr, discharges substrate surface adsorbed gas.
H is passed through into reative cell2Progress substrate surface pretreatment, gas flow 1sccm, reative cell vacuum 0.1Torr,
1000 DEG C of underlayer temperature, processing time 1min；H is passed through into reative cell2And CH4, keep H2And CH4Flow-rate ratio be 10: 1, H2
Flow 20sccm, CH4Flow 2sccm, air pressure maintain 0.1atm, 1200 DEG C, heating-up time 20min of temperature, retention time
50min；Keep H2And CH4Flow and air pressure are constant, Temperature fall, complete the growth of graphene layer.
Temperature is down to less than 100 DEG C, closes CH4、H2, Ar is passed through, opens reative cell, takes out sample, as shown in Figure 5.
The step of forming insulating layer is still further comprised after first graphene layer is formed, wherein, the insulation
Such as inorganic insulation layer of silicon oxide layer, silicon nitride layer or silicon oxynitride layer can be used in layer, such as comprising polyvinyl phenol, gathers
Insulating layer of layer of acid imide or siloxanes etc. etc. is formed.In addition, polyvinyl phenol, polyimides or siloxanes can be effective
Ground is formed by droplet discharging method, the art of printing or spin-coating method.Siloxanes can be classified into silica glass, alkane according to its structure
Silicone polymer, alkyl silsesquioxane (alkylsilsesquioxane) polymer, silsesquioxane hydride
(silsesquioxane hydride) polymer, alkyl silsesquioxane hydride (alkylsilsesquioxane
Hydride) polymer etc..
In addition, the insulating layer selects oxide, can be formed by various deposition process commonly used in the art, such as Fig. 6
It is shown.
Then the second epitaxial substrate layer 207 and the second graphene layer 208, second epitaxial substrate layer 207 are sequentially formed
The material of forming method and selection with the second graphene layer 208 can be with the first epitaxial substrate layer and the first graphene layer
It is identical, as Figure 7-8.
Then bottom electrode is formed on second graphene layer, the bottom electrode can select metal material, example
Such as copper.
Step 3 is performed, sacrificial material layer is formed in the bottom electrode layer to the top of the bottom electrode layer.
Specifically, as shown in figure 9, wherein described sacrificial material layer selects not fluorine-containing carbonaceous material (NFC).
The step of forming spacer material layer can include：First at the top of depositing isolation material layer to second graphene layer
More than, to cover second graphene layer and fill the gap between the multi-layer laminate structure, then planarization it is described every
From material layer to the top of the bottom electrode, untill exposing the bottom electrode.
Perform step 4, pattern the bottom electrode layer, second graphene layer, second epitaxial substrate layer,
The insulating layer, first graphene layer, first epitaxial substrate layer and the multi-layer laminate structure, are opened with being formed
Mouthful, by the bottom electrode layer, second graphene layer, second epitaxial substrate layer, the insulating layer, first stone
Black alkene layer, first epitaxial substrate layer and the multi-layer laminate structure are divided into spaced two parts and expose described
Semiconductor substrate.
Specifically, as shown in Figure 10, the bottom electrode layer, second graphene layer, institute are patterned in this step
State the second epitaxial substrate layer, the insulating layer, first graphene layer, first epitaxial substrate layer and the multi-laminate
Rotating fields, are open with being formed in the centre position of the multi-layer laminate structure.
Step 5 is performed, the sacrifice layer exposed in the opening in the multi-layer laminate structure is removed, with described
Groove is formed between separation layer.
Specifically, as shown in figure 11, it is described sacrificial in it can expose the multi-layer laminate structure after forming the opening
The side wall of domestic animal layer and the separation layer, then using wet etching removes the sacrifice layer by the opening, with it is described every
Groove is formed between absciss layer.
The sacrifice layer can be removed using hot phosphoric acid in this step, but be not limited to the example.
Step 6 is performed, layer of top electrode material is deposited, to fill the groove and form top electrodes.
Specifically, as shown in figure 12, in this step, deposition of electrode material layer first, the sacrifice layer is removed with filling
The groove formed afterwards, is forming the multi-laminate identical with shape before removing the sacrifice layer after filling the groove
Rotating fields, to form top electrodes.
The electrode material layer not fully fills the opening in this step, and the top is only formed on side wall
Portion's electrode, so that the top electrodes of the opening both sides are mutually isolated.
Etching top electrodes bridge in said opening is still further comprised in the step of forming the top electrodes
Part even, to be formed by the mutually isolated top electrodes of the opening.
For example, bridging can be being formed described in the bottom of the opening in Semiconductor substrate, then the bottom of the opening is etched,
The part of the bridging is disconnected, to be formed by the mutually isolated top electrodes of the opening.
The method further includes the step of forming interlayer dielectric layer and interconnection layer disposed thereon.
So far, the introduction of the correlation step of the preparation method of the semiconductor devices of the embodiment of the present invention is completed.The side
The step of method can also include forming transistor and other correlation steps, details are not described herein again.Also, except above-mentioned steps it
Outside, the preparation method of the present embodiment can also include other steps among above-mentioned each step or between different steps, this
A little steps can realize that details are not described herein again by the various techniques in current technique.
The application is in order to solve the problems, such as that current semiconductor devices exists, there is provided a kind of semiconductor devices and its preparation side
Method, epitaxial substrate is initially formed in the preparation method, and graphene is grown in the epitaxial substrate, and formed graphene-
The RRAM of the 3D structures of insulating layer-graphene (Graphene-In sulator-Graphene, G-I-G), avoids high temperature and sinks
The adverse effect that product is brought, further increases the yield and performance of the RRAM.
Embodiment two
Present invention also offers a kind of semiconductor devices, the semiconductor devices includes some storage units, the storage
Unit includes：
Semiconductor substrate；
Multi-layer laminate structure, including the top electrodes and separation layer stacked gradually, the multi-layer laminate structure include opposite
The first side wall and second sidewall of setting；
Storage organization, be included in the Semiconductor substrate, the multi-layer laminate structure top and the first side wall on
The first graphene layer, insulating layer and the second graphene layer sequentially formed；
Bottom electrode, above second graphene layer.
Wherein, the semiconductor devices includes two storage units, wherein the top of storage unit described in the both sides
Portion's electrode is opposite and spaced setting.
Wherein, the insulating layer includes metal oxide layer.
Wherein, formed with the first epitaxial substrate layer between first graphene layer and the insulating layer；
Formed with the second epitaxial substrate layer between second graphene layer and the insulating layer.
Wherein, first epitaxial substrate layer includes SiC layer；
Second epitaxial substrate layer includes SiC layer.
First, the multilayer laminated knot stacked gradually on the semiconductor substrate formed with sacrifice layer 202 and separation layer 203
Structure.
The Semiconductor substrate (not shown) can be at least one of following material being previously mentioned：Silicon, insulation
Silicon (SOI) on body, be laminated silicon (SSOI), be laminated SiGe (S-SiGeOI), germanium on insulator SiClx on insulator on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
The graphene layer can be very good the extension in the SiC layer in the present invention, and need not be too high voltage.
The graphene is the nano material that known world is most thin, most hard, it is almost fully transparent, is only absorbed
2.3% light；The high 5300W/mK of thermal conductivity factor, higher than carbon nanotubes and diamond, its electron mobility exceedes under room temperature
15000cm2/ Vs, but it is higher than carbon nanotubes or silicon crystal, and about 1 Ω m of resistivity, it is lower than copper or silver, for electricity in the world
The material of resistance rate minimum.Because its resistivity is extremely low, the speed of electron transfer is exceedingly fast, therefore select the photodetector of graphene
Performance is further improved.
Graphene is the carbon of two dimensional crystal structure, its outstanding electron mobility and other unique nanoelectronics and photon
Function has good prospect.
The application is in order to solve the problems, such as that current semiconductor devices exists, there is provided a kind of semiconductor devices, described half
Conductor device includes epitaxial substrate, and graphene is grown in the epitaxial substrate, and forms graphene-insulating layer-graphene
The RRAM of the 3D structures of (Graphene-In sulator-Graphene, G-I-G), avoids the unfavorable shadow that high temperature deposition is brought
Ring, further increase the yield and performance of the RRAM.
Embodiment three
An alternative embodiment of the invention provides a kind of electronic device, it includes semiconductor devices, which is
Semiconductor devices in previous embodiment two, or half obtained by the preparation method of semiconductor devices according to embodiment one
Conductor device.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or have
The intermediate products of above-mentioned semiconductor device, such as：Cell phone mainboard with the integrated circuit etc..
Due to including semiconductor devices have higher performance, which equally has the advantages that above-mentioned.
Wherein, Figure 14 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, is included in shell 301
In display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing semiconductor devices, or the semiconductor device according to embodiment one
Semiconductor devices obtained by the preparation method of part, the semiconductor devices include Semiconductor substrate；Multi-layer laminate structure, including
The top electrodes and separation layer stacked gradually, the multi-layer laminate structure include opposite the first side wall and second sidewall；Storage
Structure, is included in sequentially formed on the Semiconductor substrate, the top of the multi-layer laminate structure and the first side wall
One graphene layer, insulating layer and the second graphene layer；Bottom electrode, above second graphene layer.Partly led described
Body device includes epitaxial substrate, and graphene is grown in the epitaxial substrate, and forms graphene-insulating layer-graphene
The RRAM of the 3D structures of (Graphene-In sulator-Graphene, G-I-G), avoids the unfavorable shadow that high temperature deposition is brought
Ring, further increase the yield and performance of the RRAM.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
- A kind of 1. preparation method of semiconductor devices, it is characterised in that the described method includes：Semiconductor substrate is provided, is included on the semiconductor substrate formed with multi-layer laminate structure, every layer of laminated construction The sacrifice layer and separation layer stacked gradually；Sequentially formed in the Semiconductor substrate and the multi-layer laminate structure the first epitaxial substrate layer, the first graphene layer, Insulating layer, the second epitaxial substrate layer, the second graphene layer and bottom electrode layer；Pattern the bottom electrode layer, second graphene layer, second epitaxial substrate layer, the insulating layer, described First graphene layer, first epitaxial substrate layer and the multi-layer laminate structure, will be described multilayer laminated to form opening Segmentation of structures is spaced two parts and exposes the Semiconductor substrate；The sacrifice layer exposed in the opening is removed, to form groove between the separation layer；Layer of top electrode material is deposited, to fill the groove and form top electrodes.
- 2. according to the method described in claim 1, it is characterized in that, first epitaxial substrate layer includes SiC layer；Second epitaxial substrate layer includes SiC layer.
- 3. according to the method described in claim 1, it is characterized in that, the insulating layer includes metal oxide layer.
- 4. according to the method described in claim 1, it is characterized in that, also further wrapped in the step of forming the top electrodes The part for etching top electrodes bridging in said opening is included, to be formed by the mutually isolated top electricity of the opening Pole.
- 5. according to the method described in claim 1, it is characterized in that, the method is also into one after the bottom electrode is formed Step be included in the bottom electrode layer formed sacrificial material layer to the bottom electrode layer top the step of.
- 6. according to the method described in claim 5, it is characterized in that, the method is also into one after the top electrodes are formed The step of step includes removing the sacrificial material layer.
- 7. a kind of semiconductor devices, it is characterised in that the semiconductor devices includes some storage units, the storage unit bag Include：Semiconductor substrate；Multi-layer laminate structure, including the top electrodes and separation layer stacked gradually, the multi-layer laminate structure include being oppositely arranged The first side wall and second sidewall；Storage organization, is included on the Semiconductor substrate, the top of the multi-layer laminate structure and the first side wall successively The first graphene layer, insulating layer and the second graphene layer formed；Bottom electrode, above second graphene layer.
- 8. semiconductor devices according to claim 7, it is characterised in that the semiconductor devices includes two storages Unit, the top electrodes of storage unit described in two of which are opposite and spaced setting.
- 9. semiconductor devices according to claim 7, it is characterised in that the insulating layer includes metal oxide layer.
- 10. semiconductor devices according to claim 7, it is characterised in that first graphene layer and the insulating layer Between formed with the first epitaxial substrate layer；Formed with the second epitaxial substrate layer between second graphene layer and the insulating layer.
- 11. semiconductor devices according to claim 10, it is characterised in that first epitaxial substrate layer includes SiC layer；Second epitaxial substrate layer includes SiC layer.
- 12. a kind of electronic device, it is characterised in that the electronic device includes the semiconductor described in one of claim 7 to 11 Device.
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| CN110783461A (en) * | 2019-09-18 | 2020-02-11 | 北京元芯碳基集成电路研究院 | Transistor and method of manufacturing the same |
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| US20110121366A1 (en) * | 2009-04-14 | 2011-05-26 | NuPGA Corporation | System comprising a semiconductor device and structure |
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| TWI549227B (en) * | 2015-05-20 | 2016-09-11 | 旺宏電子股份有限公司 | Memory device and method for fabricating the same |
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| US20110121366A1 (en) * | 2009-04-14 | 2011-05-26 | NuPGA Corporation | System comprising a semiconductor device and structure |
| CN104810476A (en) * | 2015-05-07 | 2015-07-29 | 中国科学院微电子研究所 | Non-volatile resistive switching memory device and manufacturing method thereof |
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| CN110783461A (en) * | 2019-09-18 | 2020-02-11 | 北京元芯碳基集成电路研究院 | Transistor and method of manufacturing the same |
| CN110783461B (en) * | 2019-09-18 | 2023-08-25 | 北京元芯碳基集成电路研究院 | Transistor and method for manufacturing the same |
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