KR102433143B1 - Low-dimensional material device and method - Google Patents

Abstract

In one embodiment, the device comprises: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer comprising a source/drain region and a channel region; source/drain contacts on source/drain regions; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at the top of the gate structure, a second width at the middle of the gate structure, and a third width at the bottom of the gate structure, The second width is smaller than each of the first width and the third width.

Description

LOW-DIMENSIONAL MATERIAL DEVICE AND METHOD

Priority Claims and Cross-References

This application claims the benefit of US Provisional Application No. 62/981,749, filed on February 26, 2020, which is incorporated herein by reference.

BACKGROUND Semiconductor devices are used in various electronic applications such as, for example, personal computers, cellular phones, digital cameras and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing an insulating or dielectric layer, a conductive layer and a semiconductor material layer over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. .

The semiconductor industry continues to improve the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) with the continuous reduction of minimum feature sizes, which allows more components to be integrated within a given area.

Aspects of the present disclosure are best understood by reading the detailed description below in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.
1 illustrates an exemplary low-dimensional FinFET in a three-dimensional view, in accordance with some embodiments.
2A-18D are various diagrams of intermediate steps in the fabrication of a low-dimensional FinFET, in accordance with some embodiments.
11C depicts molecules of a self-assembled monolayer (SAM).
19A-19D illustrate a low-dimensional FinFET, in accordance with some embodiments.
20A-20D illustrate a low-dimensional FinFET, in accordance with some embodiments.
21A-21D illustrate a low-dimensional FinFET, in accordance with some embodiments.

The following disclosure provides a number of different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, this description is by way of example only and not limitation. For example, in the description that follows, the formation of a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, the first feature and the second feature. Embodiments may also include embodiments in which additional features are formed between the features such that the first and second features do not directly contact. In addition, this disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity, and such repetition itself does not indicate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "below", "below", "lower", "above", "super", etc. are used to refer to one element relative to another element(s) or feature(s) as shown in the figures. or may be used herein for ease of description to describe the relationship of features. The spatially relative terms are intended to encompass different orientations of the device in use or operation as well as the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein accordingly may likewise be understood.

In accordance with some embodiments, a low-dimensional FinFET is formed. A low-dimensional FinFET includes a low-dimensional layer used to form a source/drain region and a channel region. By etching the openings for the source/drain contacts through the low-dimensional layer, and then forming the source/drain contacts in the openings and on the low-dimensional layer, the source/drain contacts in contact with the sidewalls and top surfaces of the low-dimensional layer are formed. can be formed. In addition, a gate structure for a low-dimensional FinFET is formed on the channel region. The length of the gate structure can be controlled in a self-aligning manner by forming temporary self-assembling spacers on the source/drain contacts and then forming the gate structure between the self-assembling spacers. By controlling the thickness of the self-assembled spacer, it is possible to control the length of the resulting gate structure.

1 illustrates an exemplary low-dimensional FinFET in a three-dimensional view, in accordance with some embodiments. A low-dimensional FinFET includes a fin 54 on a substrate 50 . The pins 54 protrude above the substrate 50 . Although the fins 54 are shown as being of a different material than the substrate 50 , the fins 54 and/or the substrate 50 may include a single material or a plurality of materials. In this context, the fin 54 refers to a portion extending above the substrate 50 . A low-dimensional layer 56 extends along the sidewalls and top surfaces of the fins 54 .

The low-dimensional layer 56 is formed of a low-dimensional material that acts as both a source/drain material and a channel material for conducting the current of the low-dimensional FinFET. For example, the low-dimensional layer 56 may include a carbon nanotube layer, a transition metal dichalcogenide (TMD) layer, a graphene layer, or the like. A first portion of the low-dimensional layer 56 under the gate structure 80 acts as a channel region 76 . A second portion of the low-dimensional layer 56 on the opposite side of the gate structure 80 acts as a source/drain region 64 .

Gate structure 80 extends along sidewalls and top surfaces of channel region 76 . Gate structure 80 includes a gate dielectric 82 and a gate electrode 84 . The gate dielectric 82 is on the lower dimensional layer 56 , and the gate electrode 84 is on the gate dielectric 82 . Source/drain regions 64 are disposed on opposite sides of gate structure 80 , eg, adjacent channel region 76 . As will be discussed in more detail below, the source/drain contacts are made to the source/drain regions 64 in such a way that they have a low contact resistance and allow the length of the channel region 76 to be determined in a self-aligned manner. ) will be formed.

1 also shows a reference cross-section used in later figures. The cross-section A-A is along the longitudinal axis of the fin 54 , for example in the direction of current flow between the source/drain regions 64 . Section C-C is perpendicular to section A-A and is along the longitudinal axis of gate structure 80 . Section D-D is perpendicular to section A-A and extends through source/drain region 64 . Subsequent drawings refer to this reference section for clarity.

2A-5B are various diagrams of intermediate steps in the fabrication of a low-dimensional FinFET, in accordance with some embodiments. 2A, 3A, 4A and 5A are cross-sectional views taken along the reference cross-section A-A of FIG. 1 . Figures 2b, 3b, 4b and 5b are top views, and Figures 2a, 3a, 4a and 5a are also taken along the respective reference sections A-A in Figures 2b, 3b, 4b and 5b. is shown 2A-5B illustrate processing of a single fin region, it should be understood that multiple fins/FinFETs may be processed simultaneously.

2A and 2B , a substrate 50 is provided. Substrate 50 may be formed of any material that insulates neighboring low-dimensional FinFETs, and may also be referred to as an “isolation layer”. In some embodiments, the substrate 50 includes a semiconductor core 50A and an isolation material 50B on the semiconductor core 50A.

The semiconductor core 50A may be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and may be doped or undoped (eg, with a p-type or n-type dopant). The semiconductor core 50A may be a wafer such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of semiconductor core 50A is silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; mixed crystal semiconductors comprising silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and/or gallium indium arsenide phosphide; or a combination thereof. The semiconductor core 50A may also be formed of other materials such as sapphire, indium tin oxide (ITO), or the like.

The isolation material 50B may be any electrically insulating material. The isolation material 50B includes silicon oxide, aluminum oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), oxides such as tetraethyl orthosilicate (TEOS) based oxides and the like; nitrides such as silicon nitride and the like; or a combination thereof. The isolation material 50B may be a high-k dielectric material, such as a dielectric material having a k value greater than about 7.0, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. have. The isolation material 50B may be spin coated; chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition; LPCVD) and the like; Or it may be formed by a combination thereof or the like. In some embodiments, the isolation material 50B is a nitride, such as silicon nitride, and is formed by a deposition process, such as CVD.

A dielectric layer 52 is formed on the substrate 50 , for example on the isolation material 50B. Dielectric layer 52 will subsequently be patterned to form fins for low-dimensional FinFETs. Dielectric layer 52 may include an oxide such as silicon oxide; nitrides such as silicon nitride; low-dimensional materials such as hexagonal boron nitride (hBN); or a combination thereof. Dielectric layer 52 may be formed of a low-k dielectric material, such as a dielectric material having a k value less than about 3.0, such as PSG, BSG, or the like. The dielectric layer 52 may have a single layer structure or a composite structure comprising a plurality of layers. Dielectric layer 52 may include crystalline layer(s) (monocrystalline or polycrystalline) and/or amorphous layer(s). Dielectric layer 52 may be formed by PECVD, molecular-beam deposition (MBD), atomic layer deposition (ALD), or the like. Dielectric layer 52 may be formed through transfer. For example, if dielectric layer 52 includes hBN, a layer of hBN may be formed on another substrate, such as a sapphire substrate, copper substrate, or the like, and then transferred onto the substrate 50 . In some embodiments, dielectric layer 52 includes a layer of hBN on a layer of low-k dielectric material. Forming the dielectric layer 52 from a low-k dielectric material or a low-dimensional material may help improve electrostatic control by suppressing surface scattering due to an atomically smooth surface. Forming dielectric layer 52 from a low-k dielectric material also allows dielectric layer 52 to be patterned into fins with large width-to-height aspect ratios (discussed in more detail below).

3A and 3B , fins 54 are formed in dielectric layer 52 . Pin 54 is a dielectric strip. Although a single fin 54 is shown, it should be understood that multiple fins 54 may be simultaneously formed on the same substrate 50 and processed using processes similar to those described herein. In some embodiments, the fin 54 may be formed in the dielectric layer 52 by etching a trench in the dielectric layer 52 . The etching may be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), or a combination thereof. The etching may be anisotropic. The etching selectively etches the material of the dielectric layer 52 at a faster rate than the material of the substrate 50 (eg, the isolation material 50B) so that the etching stops at the substrate 50 .

The pins 54 may be patterned by any suitable method. For example, the fins 54 may be patterned using one or more photolithographic processes including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-aligning processes to produce patterns with a smaller pitch than can be achieved using, for example, a single direct photolithography process . For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed and the remaining spacers can be used to pattern the fins 54 . In some embodiments, a mask (or other layer) may remain on the fin 54 .

Fin 54 is formed with a width W ₁ and a height H ₁ . As noted above, the fins 54 may be formed of a low-k dielectric material, which can be easily etched to form the fins 54 with a large width-to-height aspect ratio. For example, the width W ₁ can be in the range of about 1 nm to about 15 nm, and the height H ₁ can be in the range of about 10 nm to about 300 nm.

4A and 4B , low-dimensional layer 56 is conformally formed on fin 54 and substrate 50 . Throughout the description, the term “low dimension” refers to a layer having a small thickness, such as less than about 10 nm, less than about 5 nm, or less than about 1 nm. In some embodiments, the low-dimensional layer 56 has a thickness T ₁ in a range from about 0.3 nm to about 1 nm. The low-dimensional layer 56 may be as thin as one monolayer.

Low-dimensional materials can maintain high intrinsic mobility even at very small thicknesses. The atomically thin channel material provides an ideal geometry for good static control. In addition, atomically thin channel materials can have reasonable band gap sizes, such as in the range of about 1 eV to about 2 eV, to provide semiconducting performance. The low-dimensional material may be formed to have metallic or insulating performance. Several types of low-dimensional materials may be used to form the low-dimensional layer 56 . Exemplary low-dimensional material layers include semiconducting two-dimensional (2D) material layers such as carbon nanotube networks, ordered carbon nanotubes, transition metal dichalcogenides (TMD), graphene nanoribbons, and the like. The low-dimensional material layer may be formed as described in U.S. Patent Application Serial No. 16/837,261, which is incorporated herein by reference in its entirety. The carbon nanotube network may be formed of single-wall carbon nanotube (SWCNT) grown by an immersion process. In a plan view, the carbon nanotube network can look like a plurality of randomly arranged straight (or slightly curved) tubes (of different lengths). Aligned carbon nanotubes can be grown using carbon-containing precursors at high temperatures so that the precursors are decomposed to grow carbon. In plan view, aligned carbon nanotubes generally have longitudinal directions aligned in the same direction and may have similar lengths. The TMD layer includes a compound of a group VIA element and a transition metal formed by a deposition process such as PECVD. The transition metal may be W, Mo, Ti, V, Co, Ni, Zr, Tc, Rh, Pd, Hf, Ta, Re, Ir, Pt, or the like. The group VIA element may be sulfur (S), selenium (Se), tellurium (Te), or the like. Exemplary TMD layers include MoS ₂ , MoSe ₂ , WS ₂ , WSe ₂ , and the like. The graphene nanoribbon is a graphene strip that can be formed by a film formation process such as graphite nanotomy, epitaxy, or CVD. It should be understood that other acceptable low-dimensional materials may be used. In embodiments in which the low-dimensional material layer includes individual elements such as carbon nanotubes or graphene nanoribbons, the low-dimensional material layer may further include a dielectric material to fill spaces between the individual elements. Thus, the low-dimensional layer 56 may be a carbon nanotube layer (e.g., a network of carbon nanotubes in a dielectric material, an ordered carbon nanotube, etc.), a transition metal dichalcogenide (TMD) layer (e.g., of a TMD). one or more layers), a graphene layer (eg, graphene nanoribbons in a dielectric material), or the like.

5A and 5B , low-dimensional layer 56 is patterned to remove a portion of low-dimensional layer 56 extending along a major surface of substrate 50 to expose substrate 50 . The remainder of the lower dimensional layer 56 covers the fins 54 . The low-dimensional layer 56 may be patterned using acceptable photolithography and etching techniques. The remainder of the low-dimensional layer 56 will form the channel regions and source/drain regions of the resulting low-dimensional FinFET.

6A-18D are various diagrams of additional intermediate steps in the fabrication of a low-dimensional FinFET, in accordance with some embodiments. 6a, 7a, 8a, 9a, 10a, 11a, 12a, 13a, 14a, 15a, 16a, 17a and 18a are views along the reference section A-A of FIG. is a cross-sectional view. 6b, 7b, 8b, 9b, 10b, 11b, 12b, 13b, 14b, 15b, 16b, 17b and 18b are plan views, and FIGS. 6a, 7a, 8a Figures 9a, 10a, 11a, 12a, 13a, 14a, 15a, 16a, 17a and 18a are also shown in Figures 6b, 7b, 8b, 9b, 10b, 11b, 12B, 13B, 14B, 15B, 16B, 17B and 18B are shown along the reference section A-A, respectively. FIG. 18C is a cross-sectional view taken along the reference cross-section C-C of FIG. 1 . FIG. 18D is a cross-sectional view taken along the reference cross-section D-D of FIG. 1 . 6A-18D illustrate processing of a single fin region, it should be understood that multiple fins/FinFETs may be processed simultaneously.

As discussed in greater detail below, FIGS. 6A-10B illustrate an embodiment process in which source/drain contacts to source/drain regions are formed through a regrowth process. Specifically, a portion of the lower dimensional layer 56 (and optionally the fins 54 ) is removed to form the openings 60 (see FIGS. 7A and 7B ). A conductive material is regrown in opening 60 to form source/drain contacts 62 (see FIGS. 10A and 10B ) that connect to source/drain regions 64 of lower dimensional layer 56 . For example, if lower dimensional layer 56 comprises aligned carbon nanotubes, the portion of lower dimensional layer 56 comprising the ends of the nanotubes acts as source/drain regions 64 , The drain contact 62 may be connected (eg, contacted) to an end of the nanotube. However, this process may also be used when the low-dimensional layer 56 is another type of low-dimensional layer, such as a transition metal dichalcogenide (TMD) layer, a graphene layer, or the like.

6A and 6B , a mask 58 is formed over the low-dimensional layer 56 and the substrate 50 . The mask 58 has a pattern of openings 60 exposing the underlying low-dimensional layer 56 . Opening 60 exposes a portion of low-dimensional layer 56 that will serve as a source/drain region for the resulting low-dimensional FinFET and defines where source/drain contacts will be formed. Mask 58 may be formed of a photoresist, such as a single layer photoresist, a double layer photoresist, a triple layer photoresist, or the like. In some embodiments, the mask 58 includes a bottom layer (eg, a bottom anti-reflective coating (BARC) layer), an intermediate layer (eg, a nitride, oxide, oxynitride, etc.) and It is a triple layer mask comprising a top layer (eg, photoresist). The type of mask used (eg, single layer mask, double layer mask, triple layer mask, etc.) may depend on the photolithography process used to subsequently pattern mask 58 . For example, in an extreme ultraviolet (EUV) lithography process, the mask 58 may be a single layer mask or a double layer mask. The mask 58 may be formed by spin coating, a deposition process such as CVD, a combination thereof, or the like.

Mask 58 may be patterned using acceptable photolithography techniques to form openings 60 . Opening 60 is a boundary opening that is laterally bounded on all sides by the material(s) of mask 58 . In embodiments where the mask 58 is a photoresist, the photoresist is exposed to the patterned light source by exposing the photoresist to a patterned energy source (eg, a patterned light source) to induce a chemical reaction. It can be patterned by inducing physical changes in the photoresist portion. The photoresist can then be developed by applying a developer to the exposed photoresist using physical changes and selectively removing exposed or unexposed portions of the photoresist according to the desired pattern. Exemplary photoresist developers include methyl isobutyl ketone (MIBK), diluted isopropyl alcohol, and the like.

The opening 60 is formed with a width W _{2 -A} measured along the first direction D ₁ and a width W _{3 -A} measured along the second direction D ₂ . The first direction D ₁ is parallel to the longitudinal axis of the pin 54 . The second direction D ₂ is perpendicular to the first direction D ₁ and parallel to the latitude axis of the fin 54 . The width W _{3 -A} may (or may not) be greater than the width W _{2 -A} , and may also be greater than the width W ₄ of the low dimensional layer 56 (or it may not). ). For example, the width W _{2 -A} can range from about 1 nm to about 50 nm, the width W _{3 -A} can be up to about 20 nm, and the width W ₄ can be up to about 20 nm. may be nm.

7A and 7B , low-dimensional layer 56 is etched using mask 58 as an etch mask to extend opening 60 through low-dimensional layer 56 to expose fins 54 . The etching may be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), or a combination thereof. The etching may be anisotropic. For example, the etching may be dry etching performed with argon, boron trichloride, sulfur hexafluoride, oxygen, or the like. In the illustrated embodiment, fins 54 are also etched using mask 58 as an etch mask to extend openings 60 through fins 54 to expose substrate 50 . The fins 54 may be etched by continuing the process to etch the lower dimensional layer 56 or by performing another etch with a different etchant. The etching may be anisotropic. For example, the etching may be a dry etching performed with argon. In another embodiment (discussed further below), the opening 60 does not extend through the pin 54 .

8A and 8B , the opening 60 of the mask 58 is widened to expose a further portion of the lower dimensional layer 56 . Widening the opening 60 exposes an additional portion of the low-dimensional layer 56 that will act as source/drain regions for the resulting low-dimensional FinFET. In embodiments where the mask 58 is a photoresist, the opening 60 of the mask 58 may be widened by repeating the process for developing the photoresist. For example, the developer may be reapplied to the remainder of the photoresist. The remaining portion of the photoresist is the portion of the photoresist that is not exposed to the patterned light source, but the developer can still remove the unaltered portion of the photoresist at a slower rate than the portion of the photoresist that has been physically altered by exposure. . As such, the removal rate when widening the opening 60 in the mask 58 is slower than the removal rate when the opening 60 of the mask 58 is initially patterned. Likewise, the mask 58 may be exposed to the developer for a longer duration when widening the apertures 60 than when initially patterning the apertures 60 .

The opening 60 of the mask 58 has an increased width W _{2 -B} measured along a first direction D ₁ (discussed above) and along a second direction D ₂ (discussed above). It widens with the measured increased width (W _{3 -B} ). However, the openings 60 of the lower dimensional layer 56 and the fins 54 do not widen. As such, the increased width W _2-B , W _3-B of the opening 60 of the mask 58 is equal to the original width W _2-A , W _3-A of the opening 60 of the mask 58 . ) is greater than each. After the opening 60 is widened, the width W _{3 -B is greater than the width W 2 -B} . For example, the width W _{2 -B} can range from about 1 nm to about 50 nm, and the width W _{3 -B} can be up to about 20 nm.

In some embodiments, the opening 60 widens along the first direction D ₁ and the second direction D ₂ , such that the corner region 58C is the mask 58 at the corner of the opening 60 in plan view. remains in Corner region 58C is disposed over substrate 50 and does not overlap low-dimensional layer 56 or fin 54 . The distance between adjacent corner regions 58C along the first direction D ₁ is the original width W _{2 -A} . The distance between adjacent corner regions 58C along the second direction D ₂ is the original width W _{3 -A} .

The widened opening 60 of the mask 58 exposes the top surface of the lower dimensional layer 56 where the source/drain contacts will contact. The width of the opening 60 in the mask 58 determines the width of the source/drain contact, and the width of the source/drain contact is the channel length L _ch of the resulting low-dimensional FinFET (see FIG. 13A , in more detail below). discussed). According to some embodiments, the opening 60 of the mask 58 widens with the desired channel length L _ch . For example, when a shorter channel length L _ch is desired, a wider opening 60 is formed in the mask 58 . When re-applying the developer to widen the opening 60, the duration for re-applying can be selected according to the desired channel length (L _ch ), the longer duration being the shorter channel length (L _ch ). cause Details regarding the control of the channel length (L _ch ) are discussed in more detail below.

9A and 9B , source/drain contacts 62 are formed in opening 60 . Source/drain contacts 62 extend through lower dimensional layer 56 . In embodiments where the opening 60 extends through the fin 54 , the source/drain contact 62 also extends through the fin 54 and contacts the substrate 50 . The source/drain contacts 62 are formed by depositing (eg, top-down) or growing (eg, bottom-up) a conductive material in the openings 60 . The conductive material may be a metal or a low-dimensional material formed to have metallic capabilities. Exemplary conductive materials for source/drain contacts 62 include scandium, titanium, niobium, chromium, tungsten, nickel, palladium, platinum, silver, gold, aluminum, combinations thereof, and the like. In some embodiments, source/drain contact 62 is a low-dimensional material that can be grown from substrate 50 or fin 54 by an immersion process, or is formed on another substrate and then substrate 50 or It is a low-dimensional material that can be transferred to the pins 54 . In the illustrated embodiment, source/drain contacts 62 are grown from substrate 50 . In embodiments where the source/drain contact 62 does not extend through the fin 54 , the source/drain contact 62 is grown from the fin 54 .

The source/drain contacts 62 are physically and electrically coupled to the portion of the lower dimensional layer 56 that serves as the source/drain region 64 . Accordingly, the source/drain contacts 62 are in physical contact with the sidewalls and top surfaces of the source/drain regions 64 . When the source/drain regions 64 are part of a carbon nanotube layer, forming source/drain contacts 62 in contact with the sidewalls of the source/drain regions 64 means that the source/drain contacts 62 are carbon nanotubes. to be directly connected to the end of the Forming the source/drain contacts 62 in contact with the sidewalls of the source/drain regions 64 may increase the contact area. Accordingly, the contact resistance to the source/drain regions 64 can be reduced.

10A and 10B, the mask 58 is removed. If mask 58 includes photoresist, the photoresist may be removed, for example, by an acceptable ashing process. If the mask 58 includes other layers (eg, a BARC layer, a nitride layer, etc.), an acceptable etching process may be used to remove the layer.

As shown in FIG. 10A , in a cross-sectional view, the source/drain contact 62 has a lower portion 62L and an upper portion 62U. A lower portion 62L of the source/drain contact 62 extends through the fin 54 and/or the lower dimensional layer 56 . An upper portion 62U of the source/drain contacts 62 extends through the mask 58 and contacts the top surface of the lower dimensional layer 56 . That is, the upper portion 62U is above the lower dimensional layer 56 . The lower portion 62L of the source/drain contact 62 has a width W _{2 -A} along the first direction D ₁ (see FIG. 9A ), and the upper portion 62U of the source/drain contact 62 . ) has a width W _{2 -B} along the first direction D ₁ (see FIG. 9A ).

As shown in FIG. 10B , in a plan view, each source/drain contact 62 has a central portion 62C, a pair of first projecting portions 62P ₁ , and a pair of second projecting portions 62P ₂ . has The central portion 62C is disposed between the first protruding portions 62P ₁ so that the first protruding portions 62P ₁ extend away from the central portion 62C along the first direction D ₁ . The central portion 62C is also disposed between the second projecting portions 62P ₂ such that the second projecting portions 62P ₂ extend away from the central portion 62C along the second direction D ₂ . The central portion 62C has a width W _{2 -A} along a first direction D ₁ and a width W _{3 -A} along a second direction D ₂ (see FIG. 9B ).

The first protruding portion 62P ₁ is directly above and in contact with a top surface of the lower dimensional layer 56 , such as a top surface of the source/drain regions 64 . The first protruding portion 62P ₁ may also contact the top surface of the substrate 50 . The first protruding portion 62P ₁ has a width W ₄ measured along the first direction D ₁ , which is equal to half the difference between the width W _{2 -B} and the width W _{2 -A} . the same (see Fig. 9a). The combined width of the central portion 62C and the first protruding portion 62P ₁ is equal to the width W _{2 -B} (see FIG. 9B ).

The second protruding portion 62P ₂ is directly above and in contact with the top surface of the substrate 50 . The second protruding portion 62P ₂ does not contact the top surface of the lower dimensional layer 56 . The second protruding portion 62P ₂ has a width W ₅ measured along the second direction D ₂ , which is equal to half the difference between the width W _{3 -B} and the width W _{3 -A} . the same (see Fig. 9b). The combined width of the central portion 62C and the second protruding portion 62P ₂ is equal to the width W _{3 -B} (see FIG. 9B ).

After formation, the source/drain contacts 62 are spaced apart by a distance D ₃ along the first direction D ₁ . The distance D ₃ may range from about 1 nm to about 50 nm. The distance D ₃ between the source/drain contacts 62 is the width W ₂ of the opening 60 which affects the width W ₄ of the first protruding portion 62P ₁ of the source/drain contact 62 . _-B ) (see Fig. 8a) can be controlled. Specifically, forming the source/drain contact 62 to have the first protruding portion 62P ₁ having a large width W ₄ may reduce the distance D ₃ between the source/drain contacts 62 . let it be As discussed further below, the distance D ₃ between the source/drain contacts 62 corresponds to the channel length L _ch of the resulting low-dimensional FinFET (see FIG. 13A , discussed in more detail below). . Controlling the distance D ₃ between the source/drain contacts 62 allows the channel length L _ch to be determined in a self-aligning manner.

11A and 11B , spacers 70 are formed over source/drain contacts 62 . The spacer 70 is formed of a self-assembled monolayer (SAM) of molecules, also referred to as a self-assembled spacer. As shown in FIG. 11C , each molecule of SAM includes a head group, a tail and an end group. The head group may be a thiol, phosphonate, silane, etc. anchored to the surface of the spacer 70 . The end group can be any functional group. The tail comprises one or more methylene bridges connecting the head group to the terminal group. The length of the SAM is determined by the chain length of the tail and the attraction between the head and end groups.

The molecules of the SAM are oriented to extend in a vertical direction away from the surface of the source/drain contact 62 . Thus, the length of the SAM determines the thickness of the spacer 70 . After formation, the vertical portion of the spacer 70 has a thickness T ₂ , and the horizontal portion of the spacer 70 has a thickness T ₃ . According to some embodiments, the end groups are selected such that the SAM has a desired length, and thus the spacer 70 has a desired thickness (T ₂ , T ₃ ). The spacers 70 may be grown by adsorbing (eg, by chemisorption) each of the head groups on the surface of the source/drain contacts 62 . The tail can be constructed and assembled into an ordered two-dimensional or three-dimensional structure. The terminal group of the tail can then be functionalized with the selected terminal group. The end groups are octadecyltrichloro silane, SiMeCl ₃ , SiMe ₂ Cl ₂ , SiMe ₃ Cl, SiMe ₃ Br, SiMe ₃ I, hexamethyldisilazane, n-BuSiCl ₃ , iso-BuSiCl ₃ , tert-BuSiCl ₃ , Benzyl-SiCl ₃ , perfluorooctyltrichlorosilane, and the like.

The spacers 70 are separated by a distance D ₄ . The distance D ₄ may range from about 1 nm to about 20 nm. The distance D ₄ between the spacers 70 may be controlled by controlling the thickness T ₂ of the spacers 70 . Specifically, forming the thickness T ₂ of the spacers 70 to be thick allows the distance D ₄ between the spacers 70 to be reduced. As discussed further below, the distance D ₄ between the spacers 70 corresponds to the gate length L _g of the resulting low-dimensional FinFET (see FIG. 13A , discussed in more detail below). Controlling the distance D ₄ between the spacers 70 allows the gate length L _g to be determined in a self-aligning manner. When growing the spacer 70, the end groups of the SAM can be selected according to the desired gate length (L _g ), with a longer SAM forming a thicker spacer ( 70 ) and consequently a shorter gate length (L _{g )} . ) results in

The SAM of the spacer 70 may not be formed in a completely uniform manner. Specifically, the growth of SAM may be hampered in dense regions, such as at the interface of source/drain contact 62 and source/drain region 64 and at the corner of source/drain contact 62 . As such, the thicknesses T ₂ , T ₃ may be non-uniform. Specifically, the thickness T ₂ of the vertical portion of the spacer 70 may increase in a direction away from the low-dimensional layer 56 , but increase only to one point, and then begin to decrease along the same direction. Likewise, the thickness T ₃ of the horizontal portion of the spacer 70 may be greater at the center of the top surface of the source/drain contact 62 , and may decrease at the edge of the top surface of the source/drain contact 62 . have. Accordingly, the spacer 70 may have a rounded surface, such as a concave top surface.

12A and 12B, a gate dielectric layer 72 is formed. The gate dielectric layer 72 includes a low-dimensional layer 56 and one or more layers deposited on top surfaces and sidewalls of the spacers 70 . A gate dielectric layer 72 may also be formed on the top surface of the substrate 50 . In some embodiments, gate dielectric layer 72 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layer 72 is an interfacial layer of silicon oxide formed by thermal or chemical oxidation, and hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. an overlying high-k dielectric material such as a metal oxide or silicate of Gate dielectric layer 72 may include a dielectric layer having a k value greater than about 7.0. A method of forming the gate dielectric layer 72 may include Molecular Beam Deposition (MBD), ALD, PECVD, or the like. The gate dielectric layer 72 may also be formed of a low-dimensional insulating material with a large band gap, such as hexagonal boron nitride (hBN), which may be grown in a bottom-up manner. The gate dielectric layer 72 may be formed to a thin thickness, such as in the range of about 0.5 nm to about 15 nm. In some embodiments, gate dielectric layer 72 is thicker than low dimensional layer 56 .

A gate electrode layer 74 is then formed on the gate dielectric layer 72 . A gate electrode layer 74 may be deposited over the gate dielectric layer 72 . The gate electrode layer 74 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although a single gate electrode layer 74 is shown, the gate electrode layer 74 may include any number of liner layers, any number of work function tuning layers, and fill materials.

The gate dielectric layer 72 and gate electrode layer 74 are then patterned to remove portions of the gate dielectric layer 72 and gate electrode layer 74 extending along the major surface of the substrate 50, The substrate 50 is exposed. The remaining portions of the gate dielectric layer 72 and the gate electrode layer 74 cover the lower dimension layer 56 and the spacers 70 . Gate dielectric layer 72 and gate electrode layer 74 may be patterned using acceptable photolithography and etching techniques.

13A and 13B, gate dielectric layer 72 and gate electrode layer 74 are patterned to form gate dielectric 82 and gate electrode 84, respectively. The patterning removes portions of the gate dielectric layer 72 and gate electrode layer 74 over the spacers 70 to form openings 78 exposing portions of the spacers 70 and lower dimensional layer 56 . . Gate dielectric 82 and gate electrode 84 form the gate structure 80 of the resulting low-dimensional FinFET. Gate structure 80 may also be referred to as a “gate stack”.

Gate dielectric layer 72 and gate electrode layer 74 may be patterned by any acceptable process. In some embodiments, gate dielectric layer 72 and gate electrode layer 74 may be patterned using acceptable photolithography and etching techniques. In some embodiments, gate dielectric layer 72 and gate electrode layer 74 are patterned using an adhesion lithography process. In the adhesive lithography process, an adhesive tape (not shown) is adhered to the gate electrode layer 74 , such as the top surface of the gate electrode layer 74 . The tape is then peeled off from the gate electrode layer 74 by pulling the tape in a direction perpendicular to the major surface of the substrate 50 . Thus, the peeling edge of the tape moves laterally across the substrate 50 . When peeling off the tape, a thin portion of the gate dielectric layer 72 and gate electrode layer 74 (eg, the portion on the spacers 70) comes off and adheres to the tape, but the gate dielectric layer 72 and the gate A thick portion of the electrode layer 74 (eg, a portion on the lower dimensional layer 56 ) remains without falling off.

Gate structure 80 covers a portion of low-dimensional layer 56 that acts as channel region 76 . Specifically, the gate structure 80 extends along, for example, sidewalls and top surfaces of the low-dimensional layer 56 of the channel region 76 . The channel region 76 of the lower dimensional layer 56 is the portion of the lower dimensional layer 56 that extends between the source/drain regions 64 and underlies the gate structure 80 . The channel length L _ch of the channel region 76 is determined by the distance D ₃ between the source/drain contacts 62 (see FIGS. 10A and 10B ). The distance D ₃ (see FIGS. 10A and 10B ) between the source/drain contacts 62 can be selected based on the desired channel length L _ch , with the smaller distance D ₃ being the smaller channel length. (L _ch ) The channel length (L _ch ) may range from about 1 nm to about 20 nm.

The gate structure 80 has a gate length L _g determined by the distance D ₄ between the spacers 70 (see FIGS. 11A and 11B ). The gate length L _g can be controlled in two processing steps. First, the distance D ₃ (see FIGS. 10A and 10B ) between the source/drain contacts 62 can be selected based on the desired gate length L _g , with the smaller distance D ₃ being the smaller resulting in a gate length (L _g ). Second, the thickness T ₂ of the spacer 70 can be selected based on the desired gate length L _g , with a higher thickness T ₂ of the spacer 70 resulting in a smaller gate length L _g . do. The gate length (L _g ) may range from about 1 nm to about 20 nm.

Because spacer 70 has a concave surface, gate structure 80 (eg, gate electrode 84) has convex sidewalls. Specifically, the gate length L _g of the gate structure 80 may decrease in a direction away from the lower dimensional layer 56 , but decrease only to one point, and then begin to increase along the same direction. This shape may also be referred to as a “footer” or “hourglass” shape. With this shape, each gate structure 80 has a top width at the top of the gate structure 80 , a central width at the center of the gate structure 80 , and a bottom width at the bottom of the gate structure 80 , and has a central width. is smaller than the upper and lower widths, respectively. In some embodiments, the distance between the gate electrode 84 and the source/drain region 62 is less than the distance between the corresponding gate dielectric 82 and the source/drain region 62 .

14A and 14B , spacers 70 are removed to expose source/drain contacts 62 at openings 78 . The spacer 70 is formed by selectively etching the material of the spacer 70 at a higher rate than the material of the lower dimensional layer 56, the source/drain contacts 62, the gate dielectric 82, and the gate electrode 84. It can be removed by the same acceptable etching process. The etching may be isotropic. For example, the etching may include a wet etching. The etchant may be selected based on the molecules of the SAM used to form the spacers 70 .

15A and 15B , source/drain extensions 86 are formed in lower dimension layer 56 . Source/drain extensions 86 may also be referred to as heavily doped extended source/drain regions. The source/drain extensions 86 are in exposed portions of the lower dimensional layer 56, such as the portion of the lower dimensional layer 56 between the gate structure 80 (see FIG. 13A ) and the source/drain contacts 62 . may be formed by implanting appropriate impurities (eg, p-type or n-type dopants). Exemplary n-type impurities include phosphorus, arsenic, antimony, and the like, which may be implanted by TiOx solution doping, Cl solution doping, SiNx layer doping, or the like. Exemplary p-type impurities include boron, boron fluoride, indium, and the like, which may be implanted by nitric oxide gas doping, AuCl ₃ solution doping, WOx and MoOx layer doping, and the like. Although shown separately, each source/drain region 64 and corresponding source/drain extension 86 may collectively function as a source/drain region.

16A and 16B , a first interlayer dielectric (ILD) layer 92 includes source/drain contacts 62 , source/drain extensions 86 , gate dielectric 82 and gate electrode 84 . is deposited on top The first ILD layer 92 may be formed of a dielectric material and deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), and the like. Other insulating materials formed by any acceptable process may be used. For example, the first ILD layer 92 may also include a passivating material such as carbon doped oxide, an extremely low permittivity dielectric such as porous carbon doped silicon dioxide, polyimide, solder resist, polybenzoxazole (PBO), It may be formed of a benzocyclobutene (BCB)-based polymer, a polymer such as a molding compound, or a combination thereof. The passivation material may be formed by a spin coating, lamination, deposition process, or a combination thereof, or the like. The passivation material can also be formed of a low-dimensional insulating material with a large band gap, such as hexagonal boron nitride (hBN), which can be grown in a bottom-up manner.

17A and 17B , a second source/drain contact 94 is formed in the source/drain contact 62 through the first ILD layer 92 . An opening for a second source/drain contact 94 is formed through the first ILD layer 92 . The opening may be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesive layer, etc., and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the top surface of the first ILD layer 92 . The remaining liner and conductive material form a second source/drain contact 94 in the opening. The second source/drain contact 94 is physically and electrically coupled to the source/drain contact 62 . After formation, the top surfaces of the second source/drain contact 94 and the gate electrode 84 are coplanar (within process variations). In some embodiments, prior to forming the second source/drain contact 94 , an additional planarization process, such as CMP, to remove excess material of the first ILD layer 92 from the top surface of the gate electrode 84 . This is done. In another embodiment, the planarization process performed when forming the second source/drain contacts 94 also removes excess material of the first ILD layer 92 from the top surface of the gate electrode 84 .

18A-18D , a second ILD layer 96 is deposited over the first ILD layer 92 . In some embodiments, the second ILD layer 96 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD layer 96 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method, such as CVD and PECVD. In some embodiments, an etch stop layer is formed between the first ILD layer 92 and the second ILD layer 96 .

A third source/drain contact 98 and a gate contact 100 are formed on the second source/drain contact 94 and the gate electrode 84, respectively. Openings for the third source/drain contact 98 and the gate contact 100 are formed through the second ILD layer 96 . The opening may be formed using acceptable photolithography and etching techniques. A liner and conductive material such as a diffusion barrier layer, an adhesive layer, and the like are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD layer 96 . The remaining liner and conductive material form a third source/drain contact 98 and a gate contact 100 in the opening. Third source/drain contact 98 is physically and electrically coupled to second source/drain contact 94 , and gate contact 100 is physically and electrically coupled to gate electrode 84 . The third source/drain contact 98 and the gate contact 100 may be formed by different processes or may be formed by the same process. Although shown as being formed in the same cross-section, it should be understood that each of the third source/drain contact 98 and gate contact 100 may be formed in a different cross-section, which may avoid shorting the contacts.

19A-19D illustrate a low-dimensional FinFET, in accordance with some embodiments. This embodiment is similar to the embodiment of FIGS. 18A-18D , except that the source/drain contacts 62 are formed only through the lower dimensional layer 56 and not extending into/through the fin 54 . do. For example, this embodiment may be formed where the opening 60 described with respect to FIGS. 7A and 7B does not extend through the pin 54 . The source/drain contacts 62 can be formed at a lower cost. In this embodiment, the lower portion of the source/drain contact 62 is above the fin 54 .

20A-20D illustrate a low-dimensional FinFET, in accordance with some embodiments. This embodiment is similar to the embodiment of FIGS. 18A-18D , except that the source/drain contacts 62 are formed on the lower dimensional layer 56 and do not extend into/through the lower dimensional layer 56 . do. For example, this embodiment obtains a structure similar to that of FIGS. 6A and 6B , at the opening 60 of the mask 58 , eg, directly on the low-dimensional layer 56 , source/drain. It may be formed by depositing or growing the contact 62 . The source/drain contact 62 according to the present embodiment may be formed when the low-dimensional layer 56 is formed of a low-dimensional material that does not have a structure having an end for connecting to the source/drain contact 62 . . For example, the low-dimensional layer 56 of this embodiment may be a transition metal dichalcogenide (TMD) layer, a graphene layer, or the like. In this embodiment, all of the source/drain contacts 62 are over the low-dimensional layer 56 .

21A-21D illustrate a low-dimensional FinFET, in accordance with some embodiments. This embodiment is similar to the embodiment of FIGS. 18A-18D except that a second source/drain contact 102 is formed extending through both the first ILD layer 92 and the second ILD layer 96 . similar. The second source/drain contact 102 may be formed in the same process as the gate contact 100 . An opening for the second source/drain contact 102 may be formed through both the first ILD layer 92 and the second ILD layer 96 , the second source/drain contact 102 being shown in FIGS. 18A and 18A and FIG. It may be formed in the opening in a manner similar to that discussed with respect to 18b. That is, in this embodiment, contact to the source/drain contacts 62 is achieved by forming a single continuous conductive feature through the first ILD layer 92 and the second ILD layer 96 , although FIGS. In the embodiment of FIG. 18D contact to the source/drain contacts 62 is achieved by forming separate conductive features through the first ILD layer 92 and the second ILD layer 96 . It should be understood that a similar second source/drain contact 102 may also be formed in the embodiments of FIGS. 19A-19D and 20A-20D.

Embodiments may achieve advantages. Forming the source/drain contacts 62 through the low-dimensional layer 56 may increase the contact area and decrease the contact resistance, and also the source/drain contacts 62 may reduce the carbon in the low-dimensional layer 56 . to be connected to the end of the nanotube. Accordingly, the performance of the resulting low-dimensional FinFET can be improved. Also, forming the spacers 70 as self-assembled spacers allows the length of the resulting gate structures 80 to be controlled in a self-aligning manner. Accordingly, the flexibility of manufacturing can be improved.

In one embodiment, a method includes: forming a dielectric fin on a substrate; forming a low-dimensional layer on the dielectric fin; forming a first source/drain contact and a second source/drain contact on the low-dimensional layer; growing a first self-assembling spacer and a second self-assembling spacer on the first source/drain contact and the second source/drain contact, respectively, a channel of a low-dimensional layer between the first self-assembling spacer and the second self-assembling spacer area is placed - ; forming a gate structure on the channel region; and after forming the gate structure, removing the first self-assembling spacer and the second self-assembling spacer.

In some embodiments of the method, forming the low-dimensional layer comprises: growing a carbon nanotube network by an immersion process; decomposing the carbon-containing precursor to grow aligned carbon nanotubes; or depositing a plurality of transition metal dichalcogenide (TMD) layers. In some embodiments of the method, forming the gate structure comprises: depositing a gate dielectric layer over the first self-assembling spacer, the second self-assembling spacer, and the channel region; depositing a gate electrode layer over the gate dielectric layer; and removing a portion of the gate dielectric layer and gate electrode layer on the first self-assembling spacer and the second self-assembling spacer using an adhesion lithography process. In some embodiments of the method, the adhesive lithography process comprises: adhering a tape to the gate electrode layer; and peeling the tape from the gate electrode layer by pulling the tape in a direction perpendicular to the major surface of the substrate. In some embodiments of the method, growing the first self-assembling spacer and the second self-assembling spacer comprises: growing a self-assembled monolayer of molecules on the first source/drain contact and the second source/drain contact. wherein each molecule comprises a head group, a tail and a terminal group, the head group anchored to the surface of one of the first source/drain contact or the second source/drain contact, the tail comprising the head group connected to the terminal group. In some embodiments of the method, growing a self-assembled monolayer of a molecule comprises: selecting an end group according to a desired length of the gate structure; For each molecule: adsorbing the head group on the surface; assembling the tail; and functionalizing the terminal group of the tail with the selected terminal group. In some embodiments of the method, forming the first source/drain contact and the second source/drain contact comprises: forming a photoresist on the low-dimensional layer; exposing the photoresist to a patterned light source; applying a developer to the photoresist to form openings in the photoresist exposing the lower dimensional layer; and forming a conductive material in the opening and on the lower dimensional layer. In some embodiments of the method, forming the first source/drain contact and the second source/drain contact comprises: forming a photoresist on the low-dimensional layer; exposing the photoresist to a patterned light source; applying a developer to the photoresist to form openings in the photoresist exposing the lower dimensional layer; etching the lower dimensional layer using the photoresist as an etch mask to extend the opening into the lower dimensional layer; re-applying a developer to the photoresist to widen the openings in the photoresist; and forming a conductive material in the opening in the photoresist and in the opening in the lower dimensional layer. In some embodiments of the method, forming the conductive material includes forming the conductive material on the dielectric fin. In some embodiments, the method further comprises: etching the dielectric fin using a photoresist as an etch mask to extend the opening into the dielectric fin, wherein forming the conductive material in the opening of the dielectric fin forming a conductive material. In some embodiments of the method, re-applying the developer to the photoresist comprises: selecting a duration according to a desired length of the channel region; and re-applying the developer to the photoresist for the selected duration.

In one embodiment, the device comprises: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer comprising a source/drain region and a channel region; source/drain contacts on source/drain regions; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at the top of the gate structure, a second width at the middle of the gate structure, and a third width at the bottom of the gate structure, The second width is smaller than each of the first width and the third width.

In some embodiments of the device, the entirety of the source/drain contact overlies the low-dimensional layer. In some embodiments of the device, the source/drain contact has a first portion and a second portion, the first portion overlying the low-dimensional layer, the second portion extending through the low-dimensional layer and overlying the dielectric fin. , and the first portion has a greater width than the second portion. In some embodiments of the device, the source/drain contact has a first portion and a second portion, the first portion overlying the lower dimensional layer, the second portion extending through the lower dimensional layer and the dielectric fin; The first portion has a greater width than the second portion. In some embodiments, the device further comprises a source/drain extension in the lower dimensional layer, the source/drain extension disposed laterally between the source/drain contact and the gate structure.

In one embodiment, the device comprises: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin; a gate dielectric on the lower dimensional layer; a gate electrode on the gate dielectric, the gate electrode having convex sidewalls; and a source/drain contact adjacent the gate electrode and the gate dielectric, the source/drain contact having a first portion and a second portion, the first portion in contact with a top surface of the lower dimensional layer, the second portion having a lower dimensional layer extending through the dimensional layer and in contact with sidewalls of the lower dimensional layer, the first portion being wider than the second portion, and source/drain contacts being electrically connected to the lower dimensional layer.

In some embodiments of the device, the low-dimensional layer is a carbon nanotube layer. In some embodiments of the device, the low-dimensional layer is a transition metal dichalcogenide (TMD) layer. In some embodiments of the device, the gate electrode has a first width at the top of the gate electrode, a second width at the middle of the gate electrode, and a third width at the bottom of the gate electrode, wherein the second width comprises the first width and smaller than each of the third widths.

In order that aspects of the present disclosure may be better understood by those skilled in the art, features of several embodiments have been outlined above. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. should know Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and substitutions may be made by those skilled in the art without departing from the spirit and scope of the present disclosure. and variations may be made in the present invention.

Examples

Example 1. A method comprising:

forming a dielectric fin on the substrate;

forming a low-dimensional layer on the dielectric fin;

forming a first source/drain contact and a second source/drain contact on the low-dimensional layer;

growing a first self-assembling spacer and a second self-assembling spacer on the first source/drain contact and the second source/drain contact, respectively, between the first self-assembling spacer and the second self-assembling spacer; a channel region of a low-dimensional layer is disposed;

forming a gate structure on the channel region; and

After forming the gate structure, removing the first self-assembled spacer and the second self-assembled spacer

How to include.

Example 2. The method of Example 1,

The step of forming the low-dimensional layer comprises:

growing a carbon nanotube network by an immersion process;

growing aligned carbon nanotubes by decomposing the carbon-containing precursor; or

depositing a plurality of transition metal dichalcogenide (TMD) layers;

A method comprising:

Example 3. The method of Example 1,

Forming the gate structure includes:

depositing a gate dielectric layer on the first self-assembling spacer, the second self-assembling spacer, and the channel region;

depositing a gate electrode layer on the gate dielectric layer; and

removing portions of the gate dielectric layer and the gate electrode layer on the first self-assembled spacer and the second self-assembled spacer using an adhesion lithography process;

A method comprising:

Example 4. The method of Example 3,

The adhesion lithography process comprises:

adhering a tape to the gate electrode layer; and

peeling the tape from the gate electrode layer by pulling the tape in a direction perpendicular to the major surface of the substrate;

A method comprising:

Example 5. The method of Example 1,

Growing the first self-assembling spacer and the second self-assembling spacer may include:

growing a self-assembled monolayer of molecules on the first source/drain contact and the second source/drain contact;

wherein each said molecule comprises a head group, a tail and an end group, wherein the head group comprises one of the first source/drain contact or the second source/drain contact. and anchored to the surface of one source/drain contact, wherein the tail connects the head group to the end group.

Example 6. The method of Example 5,

Growing a self-assembled monolayer of the molecule comprises:

selecting the end group according to the desired length of the gate structure;

For each of these molecules:

adsorbing the head group on the surface;

assembling the tail; and

functionalizing the terminal group of the tail with the selected terminal group;

A method comprising:

Example 7. The method of Example 1,

Forming the first source/drain contact and the second source/drain contact may include:

forming a photoresist on the low-dimensional layer;

exposing the photoresist to a patterned light source;

applying a developer to the photoresist to form an opening in the photoresist exposing the low-dimensional layer; and

forming a conductive material in the opening and on the low-dimensional layer;

A method comprising:

Example 8. The method of Example 1,

Forming the first source/drain contact and the second source/drain contact may include:

forming a photoresist on the low-dimensional layer;

exposing the photoresist to a patterned light source;

applying a developer to the photoresist to form an opening in the photoresist exposing the low-dimensional layer;

etching the lower dimensional layer using the photoresist as an etch mask to extend the opening into the lower dimensional layer;

re-applying the developer to the photoresist to widen the opening of the photoresist; and

forming a conductive material in the opening in the photoresist and in the opening in the low-dimensional layer;

A method comprising:

Example 9. The method of Example 8,

and forming the conductive material comprises forming the conductive material on the dielectric fin.

Example 10. The method of Example 8,

etching the dielectric fin using the photoresist as an etch mask to extend the opening into the dielectric fin;

and wherein forming the conductive material comprises forming the conductive material in the opening of the dielectric fin.

Example 11. The method of Example 8,

Re-applying the developer to the photoresist comprises:

selecting a duration according to a desired length of the channel region; and

re-applying the developer to the photoresist for the selected duration.

A method comprising:

Example 12.

In the device,

dielectric pins on the substrate;

a low-dimensional layer on the dielectric fin, the low-dimensional layer comprising source/drain regions and a channel region;

source/drain contacts on the source/drain region; and

a gate structure on the channel region adjacent to the source/drain contact

wherein the gate structure has a first width at an upper portion of the gate structure, a second width at the middle of the gate structure, and a third width at a lower portion of the gate structure, wherein the second width is the second width less than each of the first width and the third width.

Example 13. The method of Example 12,

and the entirety of the source/drain contacts overlies the lower dimensional layer.

Example 14. The method of Example 12,

the source/drain contact has a first portion and a second portion, the first portion overlying the lower dimensional layer, the second portion extending through the lower dimensional layer and overlying the dielectric fin, the wherein the first portion has a greater width than the second portion.

Example 15. The method of Example 12,

The source/drain contact has a first portion and a second portion, the first portion overlying the lower dimensional layer, the second portion extending through the lower dimensional layer and the dielectric fin, wherein the first portion and the portion has a greater width than the second portion.

Example 16. The method of Example 12,

Source/drain extensions in the lower dimensional layer

and wherein the source/drain extension is laterally disposed between the source/drain contact and the gate structure.

Embodiment 17. A device comprising:

dielectric pins on the substrate;

a low-dimensional layer on the dielectric fin;

a gate dielectric on the lower dimensional layer;

a gate electrode on the gate dielectric, the gate electrode having a convex sidewall; and

Source/drain contacts adjacent the gate electrode and the gate dielectric

wherein the source/drain contact has a first portion and a second portion, the first portion in contact with a top surface of the lower dimensional layer, the second portion extending through the lower dimensional layer and the and in contact with a sidewall of the lower dimensional layer, the first portion being wider than the second portion, and wherein the source/drain contacts are electrically connected to the lower dimensional layer.

Example 18. The method of Example 17,

wherein the low-dimensional layer is a carbon nanotube layer.

Example 19. The method of Example 17,

wherein the low-dimensional layer is a transition metal dichalcogenide (TMD) layer.

Example 20. The method of Example 17,

The gate electrode has a first width at an upper portion of the gate electrode, a second width at a middle portion of the gate electrode, and a third width at the lower portion of the gate electrode, wherein the second width includes the first width and the second width less than each of the third widths.

Claims (10)

In the method,
forming a dielectric fin on the substrate;
forming a low-dimensional layer on the dielectric fin;
forming a first source/drain contact and a second source/drain contact on the low-dimensional layer;
growing a first self-assembling spacer and a second self-assembling spacer on the first source/drain contact and the second source/drain contact, respectively, between the first self-assembling spacer and the second self-assembling spacer; a channel region of a low-dimensional layer is disposed;
forming a gate structure on the channel region; and
After forming the gate structure, removing the first self-assembled spacer and the second self-assembled spacer
How to include. The method of claim 1,
The step of forming the low-dimensional layer comprises:
growing a carbon nanotube network by an immersion process;
growing aligned carbon nanotubes by decomposing the carbon-containing precursor; or
depositing a plurality of transition metal dichalcogenide (TMD) layers;
A method comprising: The method of claim 1,
Forming the gate structure includes:
depositing a gate dielectric layer on the first self-assembling spacer, the second self-assembling spacer, and the channel region;
depositing a gate electrode layer on the gate dielectric layer; and
removing portions of the gate dielectric layer and the gate electrode layer on the first self-assembled spacer and the second self-assembled spacer using an adhesion lithography process;
A method comprising: 4. The method of claim 3,
The adhesion lithography process comprises:
adhering a tape to the gate electrode layer; and
peeling the tape from the gate electrode layer by pulling the tape in a direction perpendicular to the major surface of the substrate;
A method comprising: The method of claim 1,
Growing the first self-assembling spacer and the second self-assembling spacer may include:
growing a self-assembled monolayer of molecules on the first source/drain contact and the second source/drain contact;
wherein each said molecule comprises a head group, a tail and an end group, wherein the head group comprises one of the first source/drain contact or the second source/drain contact. and anchored to the surface of one source/drain contact, wherein the tail connects the head group to the end group. 6. The method of claim 5,
Growing a self-assembled monolayer of the molecule comprises:
selecting the end group according to the desired length of the gate structure;
For each of these molecules:
adsorbing the head group on the surface;
assembling the tail; and
functionalizing the terminal group of the tail with the selected terminal group;
A method comprising: The method of claim 1,
Forming the first source/drain contact and the second source/drain contact may include:
forming a photoresist on the low-dimensional layer;
exposing the photoresist to a patterned light source;
applying a developer to the photoresist to form an opening in the photoresist exposing the low-dimensional layer; and
forming a conductive material in the opening and on the low-dimensional layer;
A method comprising: The method of claim 1,
Forming the first source/drain contact and the second source/drain contact may include:
forming a photoresist on the low-dimensional layer;
exposing the photoresist to a patterned light source;
applying a developer to the photoresist to form an opening in the photoresist exposing the low-dimensional layer;
etching the lower dimensional layer using the photoresist as an etch mask to extend the opening into the lower dimensional layer;
re-applying the developer to the photoresist to widen the opening of the photoresist; and
forming a conductive material in the opening in the photoresist and in the opening in the low-dimensional layer;
A method comprising: In the device,
dielectric pins on the substrate;
a low-dimensional layer on the dielectric fin, the low-dimensional layer comprising source/drain regions and a channel region;
source/drain contacts on the source/drain region; and
a gate structure on the channel region adjacent to the source/drain contact
wherein the gate structure has a first width at an upper portion of the gate structure, a second width at a middle portion of the gate structure, and a third width at a lower portion of the gate structure, wherein the second width is the second width less than each of the first width and the third width. In the device,
dielectric pins on the substrate;
a low-dimensional layer on the dielectric fin;
a gate dielectric on the lower dimensional layer;
a gate electrode on the gate dielectric, the gate electrode having a concave sidewall; and
Source/drain contacts adjacent the gate electrode and the gate dielectric
wherein the source/drain contact has a first portion and a second portion, the first portion in contact with a top surface of the lower dimensional layer, the second portion extending through the lower dimensional layer and the and in contact with a sidewall of the lower dimensional layer, the first portion being wider than the second portion, and wherein the source/drain contacts are electrically connected to the lower dimensional layer.

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