CN110571332B

CN110571332B - Transistor and method for manufacturing the same

Info

Publication number: CN110571332B
Application number: CN201910711187.9A
Authority: CN
Inventors: 梁世博; 樊晨炜; 邱晨光; 孟令款
Original assignee: Beijing Yuanxin Carbon Based Integrated Circuit Research Institute; Beijing Hua Tan Yuan Xin Electronics Technology Co Ltd
Current assignee: Beijing Yuanxin Carbon Based Integrated Circuit Research Institute; Beijing Hua Tan Yuan Xin Electronics Technology Co Ltd
Priority date: 2019-08-02
Filing date: 2019-08-02
Publication date: 2023-06-23
Anticipated expiration: 2039-08-02
Also published as: CN110571332A

Abstract

The application discloses a transistor and a manufacturing method thereof, wherein the manufacturing method of the transistor comprises the following steps: forming carbon nanotubes on a substrate; forming a gate stack structure on the carbon nanotube; and forming an electrical contact on the carbon nanotube, wherein the step of forming the electrical contact comprises: and (3) growing a conductive material on the surface of the carbon nano tube by adopting an electroplating process, wherein the gate stack structure is used as a mask in the electroplating process. The manufacturing method takes the gate stack structure as a mask, and adopts an electroplating process to selectively grow conductive materials from bottom to top on the source/drain regions on the surface of the carbon nano tube to form electric contact, and simultaneously solves the problem of holes and the problem of side wall deposition of source/drain metals caused by using deposition means such as sputtering, vapor deposition and the like in the prior art.

Description

Transistor and method for manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor integrated circuit device fabrication, and more particularly, to a transistor and a method of fabricating the same.

Background

Carbon Nanotubes (CNTs) have advantages in terms of high speed, low power consumption, etc., and are considered as one of the best channel materials for constructing field effect transistors in the future.

In the prior art, when manufacturing a carbon nanotube transistor, for example, a sputtering method and an evaporation method are adopted to deposit source-drain metal on the surface of the carbon nanotube from top to bottom. During the deposition process, the contact electrode area cannot be perfectly filled due to the secondary sputtering effect, so that holes affecting the device performance appear.

When a self-aligned process is used to deposit the source and drain metals, the deposition process inevitably occurs simultaneously on the source and drain regions, the gate and the sidewalls. For a silicon-based device, the source-drain metal can form silicide material with a silicon substrate through annealing, and the source-drain metal deposited on the surface of the side wall is removed through a subsequent wet cleaning process. For the carbon nanotube device, when the source and drain metals are deposited by using deposition means similar to sputtering, vapor deposition and the like, the metals deposited on the gate and the side wall cannot be completely removed, thereby polluting the side wall and increasing parasitic capacitance.

When the source and drain metals are deposited by a non-self-aligned process, the problem of pollution of the side wall can be avoided, but the problem of holes caused by the secondary sputtering effect cannot be avoided.

Therefore, there is a need to further improve the manufacturing process of the source-drain contact of the carbon nanotube device, and solve the hole problem, the sidewall deposition problem of the source-drain metal, and the problem of excessive device occupation space.

Disclosure of Invention

In view of the above, the present invention provides a transistor and a method for manufacturing the same, in which a gate stack structure is used as a mask, and an electroplating process is used to selectively grow a conductive material from bottom to top on a source/drain region on a carbon nanotube surface to form an electrical contact, so as to solve the problem of holes, the problem of sidewall deposition of source/drain metals, and the problem of excessively large device occupation space.

According to an aspect of the present invention, there is provided a method of manufacturing a transistor, including: forming carbon nanotubes on a substrate; forming a gate stack structure on the carbon nanotubes; and forming an electrical contact on the carbon nanotube, wherein the step of forming the electrical contact comprises: and growing a conductive material on the surface of the carbon nano tube by adopting an electroplating process, wherein the grid stack structure is used as a mask in the electroplating process.

Preferably, before forming the electrical contact, a protective structure is further formed covering the gate stack structure, the protective structure comprising an insulating material.

Preferably, the step of forming the gate stack structure includes: forming a gate dielectric covering the carbon nanotubes; forming a gate conductor over the gate dielectric; patterning the gate conductor; and removing a portion of the gate dielectric to expose a portion of the carbon nanotubes, wherein the gate dielectric comprises an oxide of a group IIIB element, the gate dielectric acting as a stop layer when patterning the gate conductor.

Preferably, the material of the gate dielectric comprises yttria.

Preferably, the patterning includes removing a portion of the gate conductor using an etching process, the etchant including a fluorine-based gas.

Preferably, the step of forming the protective structure comprises: forming a mask layer on the gate conductor; forming an oxide layer covering the mask layer, the gate conductor, and the gate dielectric; forming a protective layer covering the oxide layer; and etching the mask layer, the oxide layer and the protective layer, wherein the etching is stopped when the protective layer forms a side wall morphology, and the rest of the mask layer, the oxide layer and the protective layer form the protective structure.

Preferably, the mask layer, the oxide layer and the protective layer are etched using fluorine-based and chlorine-based gases.

Preferably, the step of removing a portion of the gate dielectric comprises: converting the oxide into chloride using a chlorine-based gas; and dissolving the chloride in a solvent.

Preferably, after the electrical contact is formed, further comprising: forming an interlayer dielectric layer covering the electrical contact and the protection structure; removing part of the interlayer dielectric layer and part of the protective layer to expose the gate conductor; and forming an electrical connection structure through the interlayer dielectric layer in contact with the electrical contact.

Preferably, the conductive material comprises one or a combination of palladium, scandium, yttrium, aluminum, titanium, gold, molybdenum, platinum, potassium, and calcium.

According to another aspect of the present invention, there is provided a transistor formed using the manufacturing method as described above.

According to the transistor and the manufacturing method thereof provided by the invention, the conductive material grows on the surface of the carbon nano tube from bottom to top by adopting an electroplating method, so that the problem of holes in the deposition process is solved. In the electroplating process, the grid stack structure is used as a mask, and a self-alignment process is adopted to form electric contact in the source-drain contact area of the carbon nano tube, so that the problem of overlarge occupied space of the device is solved.

Further, by forming the insulating protection structure covering the gate stack structure, during the electroplating process, the source-drain region of the carbon nanotube is exposed to the electroplating solution, and the gate region is covered by the gate stack structure and the protection structure, only the carbon nanotube exposed to the electroplating solution is conductive, so that the protection structure and the gate stack structure can be avoided, and the conductive material can be selectively formed in the source-drain region of the carbon nanotube.

Compared with the prior art, the bottom-up selective growth mode provided by the application can avoid the deposition effect of the gate and the gate side wall, and greatly reduces the process complexity and the cost.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will make it apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

Fig. 1 shows a schematic structure of a transistor according to an embodiment of the present invention.

Fig. 2a to 2i show cross-sectional views of a method of manufacturing a transistor according to an embodiment of the present invention at various stages.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. For the sake of simplicity, the semiconductor device obtained after several steps may be described in one drawing.

It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.

If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying … … and adjoining" will be used herein.

Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The invention may be embodied in various forms, some examples of which are described below.

Fig. 1 shows a schematic structure of a carbon nanotube transistor according to an embodiment of the present invention.

As shown in fig. 1, a transistor according to an embodiment of the present invention includes: the device includes a substrate 101, a carbon nanotube 110, a gate stack 120, electrical contacts including a source contact structure 130 and a drain contact structure 140, an oxide layer 103, a sidewall 104, an interlayer dielectric layer 106, and a plurality of electrical connection structures 160.

The carbon nanotubes 110 are located on the substrate 101. The gate stack structure 120 covers a portion of the carbon nanotube 110, wherein the gate stack structure 120 includes a gate dielectric 121 and a gate conductor, and the gate dielectric 121 is located on the surface of the carbon nanotube 110. The gate conductor includes a functional layer 122 and an extraction layer 123, which are sequentially stacked on the gate dielectric 121 so as to cover a portion of the gate dielectric 121. The surface of the gate dielectric 121 not covered by the gate conductor is covered by the oxide layer 103, and the oxide layer 103 also covers the sidewalls of the gate conductor. The sidewalls 104 are located on both sides of the gate conductor and contact the oxide layer 103. The source contact structure 130 and the drain contact structure 140 cover at least a portion of the carbon nanotube 110, and are respectively located on two sides of the gate stack structure 120 and outside the sidewall 104. The interlayer dielectric layer 106 covers the carbon nanotubes 110, the sidewall 104, the source contact structure 130, and the drain contact structure 140. The plurality of electrical connection structures 160 penetrate through the interlayer dielectric layer 106 and respectively contact the source contact structure 130 and the drain contact structure 140.

In some embodiments, the substrate 101 includes an insulating layer on a support substrate. The supporting substrate mainly plays a supporting role, and the material can be hard insulating materials such as silicon, sapphire substrate, quartz, glass, alumina and the like, and any substrate capable of bearing carbon nano tube materials, so long as the substrate is very flat and has good uniformity. In this embodiment, a silicon material is used as a substrate, and is not particularly limited. The insulating layer is made of silicon oxide, silicon nitride, PET, PEN, polyimide and other high-temperature-resistant flexible insulating materials.

In this embodiment, the material of gate dielectric 121 includes an oxide of a group IIIB element, preferably yttria. In other embodiments, the material of gate dielectric 121 includes one or a combination of silicon oxide, silicon oxynitride, high-k (high-k) dielectric materials. The gate conductor is a metal conductor, wherein the material of the functional layer 122 includes but is not limited to titanium nitride, and the material of the extraction layer 123 includes tungsten, cobalt, copper, aluminum, and other metal materials. The material of oxide layer 103 includes, but is not limited to, silicon oxide. The material of the sidewall 104 includes, but is not limited to, silicon nitride. The material of the interlayer dielectric layer 106 includes silicon oxide, a low-k dielectric material, or other insulating material, and the material of the electrical connection structure 160 includes a metal material such as tungsten, cobalt, copper, or aluminum.

However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements on the materials of the gate stack structure 120, the oxide layer 103, the sidewall 104, and the interlayer dielectric layer 106 according to the needs.

In this embodiment, when the carbon nanotube transistor is an N-type MOSFET, the materials of the source contact structure 130 and the drain contact structure 140 include scandium, yttrium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or their alloys or their composites, and when the carbon nanotube transistor is a P-type MOSFET, the materials of the source contact structure 130 and the drain contact structure 140 include palladium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or their alloys or their composites.

However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements on the materials of the source contact structure 130 and the drain contact structure 140 as required.

The method of the embodiment of the present invention starts with a substrate 101, a carbon nanotube 110 is formed on the substrate 101, then a gate dielectric 121, a functional layer 122 and an extraction layer 123 for forming a gate conductor, and a mask layer 102 are sequentially stacked on the carbon nanotube 110, and finally a photoresist 10 is coated on the mask layer 102, as shown in fig. 2 a.

In some embodiments, the substrate 101 includes an insulating layer on a support substrate. The material of the supporting substrate mainly plays a supporting role, and can be hard insulating materials such as silicon, sapphire substrate, quartz, glass, alumina and the like, and any substrate capable of bearing carbon nano tube materials, so long as the substrate is very flat and has good uniformity. In this embodiment, a silicon material is used as a substrate, and is not particularly limited. The insulating layer is made of silicon oxide, silicon nitride, PET, PEN, polyimide and other high-temperature-resistant flexible insulating materials. However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements of the materials of the support substrate and the insulating layer as required.

In this embodiment, the material of gate dielectric 121 includes an oxide of a group IIIB element, preferably yttria. In other embodiments the material of gate dielectric 121 includes materials that are silicon oxide, silicon oxynitride, high-k (high-k) dielectrics. The gate conductor is a metal conductor, wherein the material of the functional layer 122 includes but is not limited to titanium nitride, and the material of the extraction layer 123 includes tungsten, cobalt, copper, aluminum, and other metal materials. The material of the mask layer 102 includes, but is not limited to, silicon oxide. The photoresist 10 is preferably hydrogen silsesquioxane (Hydrogen silsesquioxane, HSQ) and is preferably 100nm thick.

In this step, after the photoresist is coated, the photoresist is patterned using an electron beam lithography process, thereby defining a gate region.

However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements on the material of the gate stack structure 120 according to need, for example, when the front gate process is used, the dummy gate electrode may be made of amorphous silicon, polysilicon, or the like.

Further, the gate conductor is patterned, defining the gate conductor in a defined gate region, as shown in fig. 2 b.

In this step, for example, an inductively coupled plasma etching (Inductively Coupled Plasma Etch, ICPE) process is used to remove a portion of the gate conductor, and the etchant includes fluorine-based inductively coupled plasma (F-based ICP), and since the material of the gate dielectric 121 in this embodiment includes yttria, the gate dielectric 121 can serve as a stop layer to protect the carbon nanotubes 110 from being damaged by the etchant when etching the gate conductor, because the material has a higher etching selectivity with respect to the gate conductor.

Further, an oxide layer 103 is formed covering the mask layer 102, the gate conductor and the gate dielectric 121, as shown in fig. 2 c.

In this step, the oxide layer 103 conformally coats the surface of the gate dielectric 121, the surface of the mask layer 102, and the sidewalls of the functional layer 122, the extraction layer 123, and the mask layer 102. In this embodiment, the material of the oxide layer 103 includes silicon oxide, and the thickness is preferably 3nm.

However, embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements of the material and thickness of the oxide layer 103 as desired.

Further, a protective layer 104 is formed to cover the oxide layer 103, as shown in fig. 2 c.

In this step, the protective layer 104 is formed, for example, using a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) process. In this embodiment, the material of the protective layer 104 includes silicon nitride, and the thickness is preferably 50nm.

Further, the protection layer 104, the oxide layer 103 and the mask layer 102 are etched, so that the protection layer forms a sidewall morphology, as shown in fig. 2 d.

In this step, portions of protective layer 104, oxide layer 103, and mask layer 102, and gate dielectric 121 are removed, for example, using an inductively coupled plasma etch ICPE process, with the etchant comprising fluorine-based and chlorine-based inductively coupled plasmas (F-based & Cl-based ICPs). The process parameters of the etching are adjusted, and the method comprises the following steps: and controlling one or more of reaction pressure, reaction time, reaction temperature, reaction speed, radio frequency power, gas or liquid flow and the like to stop etching when the protective layer forms a side wall morphology. In this embodiment, the remaining mask layer 102, oxide layer 103 and protective layer 104 (sidewall) form a protective structure covering the surface of the gate stack, and when the F-based & Cl-based ICP contacts the exposed gate dielectric 121, the yttrium oxide material undergoes a chlorination reaction to form yttrium chloride, which is dissolved by water or other organic solution to expose a portion of the carbon nanotubes 110. By utilizing the very water or ethanol soluble nature of yttrium chloride, the exposed gate dielectric 121 can be removed while ensuring that the carbon nanotubes 110 are not damaged or contaminated.

Further, electrical contacts are formed on the surface of the carbon nanotube 110, including a source contact structure and a drain contact structure. In this step, an electroplating process is first used to grow a conductive material on the surface of the carbon nanotube 110 to form an electrical contact in the source-drain region, and then a suitable process is also used to completely remove the contact metal in some regions between the devices, so as to achieve insulation between the devices, which would otherwise cause a short circuit between the devices.

Specifically, the device is first immersed in a salt solution containing a pre-metal, the salt solution containing a plurality of pre-metal ions 1051, as shown in fig. 2 e. The pre-plated metal ions 1051 in the plating solution are then converted to conductive material 1052 by electrolysis using the carbon nanotubes 110 as electrodes and deposited on the surface of the carbon nanotubes 110 as shown in fig. 2 f. Since the gate stack structure is used as a mask in the electroplating process and is covered by the protective layer 150, the material forming the protective layer 150 is an insulating material, in the electroplating process, only the conductive carbon nanotube 110 surface grows the conductive material 105 from bottom to top, and the protective layer 150 is insulating and is not covered by the conductive material 105, thereby achieving the purpose of selective growth, avoiding the deposition effect of the gate and the gate sidewall, and greatly reducing the complexity and cost of the process. Thereafter, portions of the conductive material on the carbon nanotubes 110 are removed, for example, using photolithography and etching processes, to form the source contact structure 130 and the drain contact structure 140 as shown in fig. 2 g.

Further, an interlayer dielectric layer 106 is formed to cover the carbon nanotube 110, the source contact structure 130, the drain contact structure 140 and the protection structure 150, as shown in fig. 2 h.

In this step, for example, a PECVD process or a Spin-on process is used to form the interlayer dielectric layer 106, where portions of both sides of the interlayer dielectric layer 106 corresponding to the gate structure and corresponding to the source-drain contact structure. In this embodiment, the material of the interlayer dielectric layer 106 includes silicon oxide, a low-k (low-k) dielectric material, or other insulating material.

However, embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements on the material of the interlayer dielectric layer 106 as needed.

Further, the mask layer and a portion of the interlayer dielectric layer 106 are removed to expose the gate conductor, as shown in fig. 2 i.

In this step, interlayer dielectric layer 106 is etched, for example, using an ICPE process, with an etchant comprising fluorine-based inductively coupled plasma (F-based ICP), by tuning the process parameters of the etch, including: one or more of reaction pressure, reaction time, reaction temperature, reaction rate, radio frequency power, gas or liquid flow, etc., control etching stops when the extraction layer 123 is completely exposed after removal of the mask layer.

In this embodiment, although the oxide layer 103 and the sidewall 104 are also partially etched, after the etching is completed, the oxide layer 103 and the sidewall 104 still cover the sidewall of the gate conductor to protect the gate conductor, and the extraction layer 123 is higher than the portion of the interlayer dielectric layer 106 corresponding to the source-drain contact structure.

Further, a plurality of electrical connection structures 160 are formed through the interlayer dielectric layer 106 in contact with the source contact structure 130 and the drain contact structure 140, as shown in fig. 1.

After the plurality of electrical connection structures 160 are formed, the plurality of electrical connection structures 160 are etched using an ICPE process such that the surfaces of the plurality of electrical connection structures 160 are recessed. Wherein the etchant comprises (F-based ICP).

Since the extraction layer 123 in the gate is higher than the electrical connection structure 160, and the sidewalls of the gate conductor are protected by the oxide layer 102, the sidewall 103, and the interlayer dielectric layer 106, a breakdown problem between the electrical connection structure 160 and the gate conductor is prevented.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present invention are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A method of manufacturing a transistor, comprising:

forming carbon nanotubes on a substrate;

forming a gate stack structure including a gate dielectric and a gate conductor on the carbon nanotube; and

electrical contacts are formed on the carbon nanotubes,

wherein the step of forming the electrical contact comprises: growing a conductive material on the surface of the carbon nano tube by adopting an electroplating process, wherein the grid stack structure is used as a mask in the electroplating process;

wherein prior to forming the electrical contact, further comprising forming a protective structure overlying the gate stack structure, the protective structure comprising an insulating material;

wherein the step of forming the protective structure comprises:

forming a mask layer on the gate conductor;

forming an oxide layer covering the mask layer, the gate conductor, and the gate dielectric;

forming a protective layer covering the oxide layer; and

etching the mask layer, the oxide layer and the protective layer by adopting fluorine-based and chlorine-based gases,

and stopping etching when the protective layer forms a side wall morphology, and forming the protective structure by the rest mask layer, the oxide layer and the protective layer.

2. The method of manufacturing of claim 1, wherein forming the gate stack structure comprises:

forming a gate dielectric covering the carbon nanotubes;

forming a gate conductor over the gate dielectric;

patterning the gate conductor;

and removing a portion of the gate dielectric to expose a portion of the carbon nanotubes,

wherein the gate dielectric comprises an oxide of a group IIIB element, the gate dielectric acting as a stop layer when patterning the gate conductor.

3. The method of manufacturing of claim 2, wherein the material of the gate dielectric comprises yttria.

4. The method of manufacturing of claim 2, wherein the patterning comprises removing a portion of the gate conductor using an etching process, the etchant comprising a fluorine-based gas.

5. The method of manufacturing of claim 2, wherein removing a portion of the gate dielectric comprises:

converting the oxide into chloride using a chlorine-based gas;

and dissolving the chloride in a solvent.

6. The method of manufacturing of claim 1, further comprising, after forming the electrical contact:

forming an interlayer dielectric layer covering the electrical contact and the protection structure;

removing part of the interlayer dielectric layer and part of the protective layer to expose the gate conductor; and

and forming an electric connection structure which is contacted with the electric contact through the interlayer dielectric layer.

7. The method of manufacturing of any of claims 1-6, wherein the conductive material comprises one or a combination of palladium, scandium, yttrium, aluminum, titanium, gold, platinum, molybdenum, potassium, and calcium.

8. A transistor formed using the manufacturing method of any of claims 1-7.